JP2001308193A - Semiconductor device and method of fabrication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device comprising lateral J-FETs having a high mutual conductance and bipolar transistors having a high cut-off frequency, and a method for fabricating the semiconductor device with a small number of steps. SOLUTION: A junction field effect transistor has a tunnel region of first conductivity type semiconductor layer provided on one major surface of a substrate, an upper gate region of heavily doped second conductivity type first diffusion layer provided in a specified region of the substrate, a source electrode and a drain electrode provided on the opposite sides of the upper gate region, and an extension gate region of lightly doped second conductivity type second diffusion layer provided in the upper gate region to extend toward the drain electrode side. A bipolar transistor comprises an outer base region of second conductivity type diffusion layer having density and depth substantially equal to those of the first diffusion layer, and an active base region of second conductivity type diffusion layer having density and depth substantially equal to those of the second diffusion layer. The semiconductor device comprises lateral junction field effect transistors and bipolar transistors fabricated on a second conductivity type semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device (hereinafter referred to as I).
C) (hereinafter abbreviated as C) and a junction type field effect transistor (hereinafter referred to as “J-FET”).

[0002]

2. Description of the Related Art In general, bipolar ICs are widely used for signal processing of analog radio waves such as televisions and radios. In recent years, as ICs used in analog radio receivers have become higher in frequency and more multifunctional, the same semiconductor chip has been used to integrate a high withstand voltage output stage in an IC including high frequency bipolar transistors. An IC in which a high-frequency bipolar transistor and a high breakdown voltage lateral J-FET are integrated has been developed.

An IC in which an ultra-high frequency bipolar transistor and a lateral J-FET are integrated is disclosed in Japanese Patent Application Laid-Open No. H11-87240 as a prior example, and will be described below. FIG. 9 is a cross-sectional view of a conventional IC, which has a bipolar transistor and a J-FET, and has a collector of the bipolar transistor and a J-FET.
In the IC which is connected to the source of J-FET,
A gate electrode 77G connected to the upper gate region 74,
The drain electrode 78D connected to the drain region 68
The gate electrodes 77G are formed as different electrodes of the same electrode material or different electrode materials, and the arrangement surface of the edge on the drain side of the gate electrode 77G is positioned lower than the arrangement surface of the edge on the gate side of the drain electrode 78D. I do.

In a conventional IC configured as described above,
The gate-drain distance is shortened by arranging the gate electrode 77G and the drain electrode 78D of the J-FET sufficiently close to or overlapping each other. Further, an insulated gate field effect transistor (hereinafter, referred to as "MIS type FET") structure is provided by disposing the gate electrode 77G over the drain region 63 via the insulating film 69. Since the pinch-off voltage is reduced by the electric field effect generated by this structure, a J-FET having low on-resistance and high transconductance is realized.

[0005]

However, a conventional semiconductor device having a lateral J-FET and a bipolar transistor on a semiconductor substrate has the following problems. The gate electrode 77G connected to the upper gate region 74 of the J-FET is formed at the same time as the base extraction electrode (base electrode) 77B connected to the external base region 72G of the bipolar transistor.
7B has a structure that overhangs the collector region 76 with the insulating film 69 interposed therebetween. Therefore, the parasitic capacitance between the base electrode 77B and the collector region 76 (parasitic capacitance via the insulating film) increases. Since this parasitic capacitance increases the base-collector capacitance (Ccb), the cutoff frequency (fT) of the bipolar transistor decreases. In particular,
In order to more effectively reduce the pinch-off voltage of the J-FET and improve the transconductance (gm), the insulating film 6
When 9 is made thinner, the base-collector capacitance of the transistor further increases. As a result, the cutoff frequency (fT) of the bipolar transistor further decreases.

In the conventional method of manufacturing a semiconductor device, the external base region 72 of the bipolar transistor is not provided.
g, forming an upper gate region 74 of the J-FET, forming an insulating film 69 on the semiconductor substrate, then opening a contact window in the insulating film 69, and forming the upper gate through the opened contact window. A photoetching step for forming the region 74 was required. In this manufacturing method, the number of photoetching steps is one more than that in a normal bipolar transistor manufacturing step. Since the base region 72 of the bipolar transistor is also formed at the same time in this photoetching step, the base region 72 is
It is formed inside the collector region 76 separated by a distance at least in view of a margin for mask alignment than the collector region 76 surrounded by. Therefore, collector region 76 is larger than base region 72, and the element area of the bipolar transistor increases.

That is, a horizontal J-FET is formed on a semiconductor substrate.
The conventional semiconductor device having a bipolar transistor and a bipolar transistor has a problem that it is difficult to improve the cutoff frequency of the bipolar transistor by improving the mutual conductance of the J-FET.
Further, the conventional method of manufacturing a semiconductor device requires a photo-etching step for forming an external base region of a bipolar transistor and an upper gate region of a J-FET. Therefore, it has been difficult to increase the number of manufacturing steps of the semiconductor device and to improve the productivity. Further, since the conventional semiconductor device has an increased element area, it has been difficult to reduce the cost of the semiconductor device. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems, and to provide a semiconductor device having a simple configuration having a lateral J-FET having a high transconductance and a bipolar transistor having a high cutoff frequency, and a method of manufacturing the same. That is. It is another object of the present invention to provide a semiconductor device having a lateral J-FET and a bipolar transistor having a small element area, and a method of manufacturing the same. Still another object of the present invention is to provide a horizontal J-FE that can be manufactured with a small number of steps.
An object of the present invention is to provide a semiconductor device having a T and a bipolar transistor and a method of manufacturing the same.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor device having a lateral junction field effect transistor and a bipolar transistor on a semiconductor substrate of a second conductivity type. The junction field-effect transistor includes a channel region provided on one main surface of the substrate and formed of a semiconductor layer of a first conductivity type, and a channel region provided on a predetermined region of the substrate and having a second conductivity type and high concentration. An upper gate region made of one diffusion layer, a source electrode and a drain electrode provided on both sides of the upper gate region, and a second conductivity type provided to extend on the drain electrode side of the upper gate region. An extended gate region made of a low-concentration second diffusion layer, wherein the bipolar transistor has a second diffusion layer having substantially the same concentration and substantially the same depth as the first diffusion layer. An external base region comprising a diffusion layer of an electric conductivity type; and an active base region comprising a diffusion layer of a second conductivity type having substantially the same concentration and substantially the same depth as the second diffusion layer. A semiconductor device.

The present invention has the effect of realizing a lateral J-FET having a high transconductance and a bipolar transistor having a high cutoff frequency. The extended gate region of the semiconductor device of the present invention is
Similarly to the gate electrode 77G extending above, the pinch-off voltage of the J-FET is reduced, and a J-FET with low on-resistance and high transconductance is realized. Since the semiconductor device of the present invention does not have the gate electrode 77G on the insulating film 69 unlike the conventional semiconductor device, even if the insulating film 69 is made thick to reduce the base-collector capacitance of the bipolar transistor. , J-FET has no effect on the pinch-off voltage or transconductance. Therefore, the present invention provides a low pinch-off voltage, low on-resistance and high transconductance J-
This has an effect that a semiconductor device having an FET can be realized.

By manufacturing the extended gate region of the semiconductor device of the present invention in the same process as the active base region of the bipolar transistor, the depth of the extended gate region can be reduced. It is effectively thicker than the channel region below the upper gate region. Therefore, the J-FET of the semiconductor device of the present invention has a high transconductance. Further, the upper gate region of the semiconductor device of the present invention can be manufactured in the same process as the external base region of the bipolar transistor, and the extended gate region of the semiconductor device of the present invention is the same as the active base region of the bipolar transistor. Manufacturing is possible in the same process. The external base region 10a and the upper gate region 10b of the semiconductor device of the present invention are self-aligned based on the shape of the base electrode 7a (the base electrode 7a and the isolation region 5 in the third aspect of the invention) and the upper gate electrode 7b. (Photoetching for forming an external base region and the like is not required.) Therefore, in the method of manufacturing an IC according to the present invention, the number of photo-etching steps can be reduced by one compared with the conventional method. Therefore, the present invention
It has an effect that a semiconductor device which is easy to manufacture and has high productivity can be realized.

According to a second aspect of the present invention, there is provided a semiconductor device having a lateral junction type field effect transistor and a bipolar type transistor on a semiconductor substrate of a second conductivity type, wherein the junction type field effect transistor is provided. The transistor includes a channel region provided on one main surface of the substrate and formed of a semiconductor layer of a first conductivity type, and a second transistor provided on a predetermined region of the substrate.
An upper gate region made of a first diffusion layer of a conductivity type of the above, a junction type upper gate electrode provided on the upper gate region, and a source electrode and a drain electrode provided on both sides of the upper gate region, respectively. And an insulating gate electrode provided on the channel region on the drain electrode side of the upper gate region and made of a semiconductor film of a first conductivity type, wherein the bipolar transistor is provided with the first diffusion layer. An external base region comprising a diffusion layer of a second conductivity type having substantially the same concentration and substantially the same depth as the layer; and a first conductivity type having substantially the same composition and substantially the same thickness as the semiconductor film. And an emitter electrode formed of a semiconductor film.

The present invention has the effect of realizing a lateral J-FET having a high transconductance and a bipolar transistor having a high cutoff frequency. Insulated gate electrode (pseudo gate electrode) of the semiconductor device of the present invention
Is formed on the channel region adjacent to the upper gate region of the J-FET via an insulating film. The insulated gate electrode constitutes a MIS FET together with the channel region, the drain region, the source region, and the like. The insulated gate electrode is a channel region (semiconductor layer) below the insulated gate electrode
The pinch-off voltage of the J-FET is reduced by the electric field effect of the depletion layer that spreads, and a J-FET with low on-resistance and high transconductance is realized. Therefore, the present invention provides a low pinch-off voltage, low on-resistance and high transconductance J
-Has the effect of realizing a semiconductor device having an FET.

Further, the upper gate region of the semiconductor device of the present invention can be manufactured in the same process as the external base region of the bipolar transistor, and the insulated gate electrode of the semiconductor device of the present invention is formed by the emitter of the bipolar transistor. It can be manufactured in the same process as the electrode. External base region 10a and upper gate region 10 of the semiconductor device of the present invention
b denotes the base electrode 7a (the base electrode 7a and the isolation region 5 in the third aspect of the invention) and the upper gate electrode 7a.
It can be generated in a self-aligned manner based on the shape of b (photoetching for forming an external base region or the like is unnecessary). Therefore, in the method of manufacturing an IC according to the present invention, the number of photo-etching steps can be reduced by one compared with the conventional method. Therefore, the present invention has an effect that a semiconductor device which is easy to manufacture and has high productivity can be realized.

The invention according to claim 3 of the present invention is the semiconductor device according to claim 1 or 2, wherein an outer peripheral portion of the external base region is surrounded by an insulating film.

The external base region of the semiconductor device of the present invention
Since the outer peripheral portion has a walled base structure surrounded by an insulating film, the side surface capacitance of the base-collector junction surface is small,
In addition, since there is a distance between the base electrode and the collector electrode, the base-collector capacitance (Ccb) is small. Accordingly, the present invention has an effect that a semiconductor device including a bipolar transistor having a high cutoff frequency (fT) can be realized.

By providing a base lead electrode on a thick insulating film around the external base region,
Parasitic MIS capacitance between collectors (metal insul
attor semiconductor capacity) can be further reduced. The external base region 10a of the semiconductor device of the present invention can be generated in a self-aligned manner based on the shapes of the base electrode 7a and the isolation region 5 (photoetching for forming the external base region and the like is unnecessary. ). Therefore, in the method of manufacturing an IC of the present invention,
The number of photo-etching steps can be reduced by one as compared with the related art. Therefore, the present invention has an effect that a semiconductor device which is easy to manufacture and has high productivity can be realized. Also, because the external base region is made self-aligned,
It is not necessary to form a collector region with a margin for mask alignment unlike the conventional example. Therefore, the present invention has an effect that a semiconductor device having a small element area can be realized.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a lateral junction field-effect transistor and a bipolar transistor on a semiconductor substrate of a second conductivity type. Forming a first conductive type semiconductor layer constituting a region including a channel region of the junction field effect transistor and a collector region of the bipolar transistor on one main surface; and forming the semiconductor layer in a predetermined region of the substrate. Forming a high-concentration first diffusion layer of a second conductivity type forming a region including an upper gate region of the junction field effect transistor and an external base region of the bipolar transistor; and a drain of the upper gate region. Extended gate region of the junction field effect transistor provided to extend to the region side and the bipolar transistor Forming a low-concentration second diffusion layer of a second conductivity type forming a region including an active base region; and including a source region and a drain region of the junction field effect transistor on both sides of the upper gate region. Forming a third diffusion layer of a first conductivity type forming a region.

The method of manufacturing a semiconductor device according to the present invention uses a horizontal J-FET having a high transconductance and a bipolar transistor having a high cutoff frequency in the same manufacturing process as that of an ultra-high-frequency bipolar transistor and using a normal manufacturing technique. This has the effect of realizing a manufacturing method capable of manufacturing a semiconductor device in which integrated type transistors are integrated. The semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention is J-type.
An FET has an extended gate region, and the extended gate region reduces the pinch-off voltage of the J-FET, thereby realizing a J-FET with low on-resistance and high transconductance. Since the semiconductor device manufactured by the method for manufacturing a semiconductor device of the present invention does not have the gate electrode 77G on the insulating film 69 unlike the conventional semiconductor device, the insulating film 69 is made thicker and the base of the bipolar transistor is formed. Reducing the collector-to-collector capacitance does not affect the pinch-off voltage or the transconductance of the J-FET. Therefore, the present invention has an effect that a method of manufacturing a semiconductor device having a bipolar transistor having a high fT and a J-FET having a low pinch-off voltage, a low on-resistance, and a high transconductance can be realized.

In the method of manufacturing a semiconductor device according to the present invention, since the extension gate region is formed in the same step as the active base region of the bipolar transistor, the depth of the extension gate region is small, and the extension gate region is below the extension gate region of the J-FET. Channel region has a thickness that is effectively greater than the channel region below the upper gate region. Therefore, the J-FET of the semiconductor device manufactured by the method of manufacturing a semiconductor device of the present invention
Have a high transconductance. Further, in the method of manufacturing a semiconductor device according to the present invention, the upper gate region of the J-FET and the external base region of the bipolar transistor are manufactured in the same process, and the extended gate region of the J-FET and the activation of the bipolar transistor are activated. The base region is manufactured in the same process. Further, in the present invention, the external base region 10a and the upper gate region 10b are self-aligned based on the shapes of the base electrode 7a (the base electrode 7a and the isolation region 5 in the invention of claim 7) and the upper gate electrode 7b. (Photo-etching for forming the external base region and the like is not required.) In the conventional example, the external base region 72g and the upper gate region 74 are formed in a region formed by photo-etching the insulating film 69 (the base electrode 77b and the upper gate electrode 77g are spread over the insulating film. Due to its shape, it can only be generated after photo-etching of the insulating film.) Therefore, the IC manufacturing method of the present invention has one less photoetching step than the conventional method. Therefore, the present invention
It has an effect that a method of manufacturing a semiconductor device which is easy to manufacture and has high productivity can be realized.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a lateral junction field-effect transistor and a bipolar transistor on a semiconductor substrate of a second conductivity type, the method comprising: Forming a first conductive type semiconductor layer constituting a region including a channel region of the junction field effect transistor and a collector region of the bipolar transistor on one principal surface of the junction field effect transistor; Forming a semiconductor film of a second conductivity type forming a portion including a base upper gate electrode and a base electrode of the bipolar transistor; and forming an upper gate region of the junction field effect transistor in a predetermined region of the substrate. Forming a first diffusion layer of a second conductivity type forming a region including an external base region of the bipolar transistor; And forming a portion including a portion including an insulated gate electrode of the junction field effect transistor and an emitter electrode of the bipolar transistor provided on the channel region on the drain region side of the upper gate region. Forming a semiconductor film of a first conductivity type, and forming a second diffusion layer of a first conductivity type forming a region including a source region and a drain region of the junction field effect transistor on both sides of the first diffusion layer The process of
A method for manufacturing a semiconductor device, comprising:

The method of manufacturing a semiconductor device according to the present invention uses a horizontal J-FET having a high transconductance and a bipolar transistor having a high cutoff frequency by using the same manufacturing process as that of the ultrahigh-frequency bipolar transistor and using a normal manufacturing technique. This has the effect of realizing a manufacturing method capable of manufacturing a semiconductor device in which integrated type transistors are integrated. The semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention is J-type.
The FET has an insulated gate electrode (pseudo gate electrode).
The insulated gate electrode constitutes a MIS FET together with the channel region, the drain region, the source region, and the like.
Due to the electric field effect of the depletion layer spreading in the channel region (semiconductor layer) under the insulated gate electrode, J-
A pinch-off voltage of the FET is reduced to realize a J-FET having low on-resistance and high transconductance. Therefore, the present invention has an effect that a method of manufacturing a semiconductor device having a J-FET having a low pinch-off voltage, a low on-resistance, and a high transconductance can be realized.

Further, in the method of manufacturing a semiconductor device according to the present invention, the upper gate region of the J-FET and the external base region of the bipolar transistor are manufactured in the same step, and the insulated gate electrode of the J-FET and the bipolar transistor are formed. The emitter electrode of the transistor is manufactured in the same process. Further, in the present invention, the external base region 10a and the upper gate region 10b are self-aligned based on the shapes of the base electrode 7a (the base electrode 7a and the isolation region 5 in the invention of claim 7) and the upper gate electrode 7b. (Photo-etching for forming the external base region and the like is not required.) In the conventional example, the external base region 72g and the upper gate region 74 are formed in a region formed by photo-etching the insulating film 69 (the base electrode 77b and the upper gate electrode 77g are spread over the insulating film. Due to its shape, it can only be generated after photo-etching of the insulating film.) Therefore, the IC manufacturing method of the present invention has one less photoetching step than the conventional method. Therefore, the present invention has an effect that a semiconductor device manufacturing method which is easy to manufacture and has high productivity can be realized.

According to a sixth aspect of the present invention, the external base region is formed by diffusing an impurity of a second conductivity type from a first polycrystalline silicon film constituting the base electrode of the bipolar transistor. 6. The semiconductor device according to claim 4, wherein the emitter electrode is formed by diffusing an impurity of a first conductivity type into a second polycrystalline silicon film.
3. The method for manufacturing a semiconductor device according to (1).

In the method of manufacturing a semiconductor device according to the present invention, the external base region is formed in a self-aligned manner without using a mask. No photo-etching step for forming the external base region is required. Therefore, the present invention has an effect that a semiconductor device manufacturing method which is easy to manufacture and has high productivity can be realized.

According to a seventh aspect of the present invention, the step of forming an insulating film surrounding an outer peripheral portion of the external base region is performed.
The method of manufacturing a semiconductor device according to any one of claims 4 to 6, further comprising:

In the method of manufacturing a semiconductor device according to the present invention, the outer peripheral portion of the external base region of the bipolar transistor is surrounded by an insulating film (walled base structure). As a result, a distance can be provided between the base electrode and the collector electrode and the side surface capacitance of the base-collector junction surface can be reduced, so that a semiconductor device having a small base-collector capacitance (Ccb) can be provided. Can be manufactured. The present invention has an effect that a semiconductor device manufacturing method capable of manufacturing a semiconductor device including a bipolar transistor having a high cutoff frequency (fT) can be realized. More preferably, in the method of manufacturing a semiconductor device of the present invention, a base lead electrode is provided on a thick insulating film around an external base region. Thereby, the present invention provides a parasitic MIS capacitance (met) between the base and the collector.
al insulator semiconductor
r capacity) can be further reduced.

In the method of manufacturing a semiconductor device according to the present invention, the external base region 10a can be generated in a self-aligned manner based on the shapes of the base electrode 7a and the isolation region 5 (for forming the external base region and the like). No photo-etching is required.) Therefore, the method of manufacturing an IC according to the present invention has an effect that the number of photo-etching steps can be reduced by one compared with the conventional method. In addition, since the external base region can be formed in a self-aligned manner, there is no need to form a collector region with a margin for mask alignment unlike the conventional example. Therefore, the present invention has an effect that a semiconductor device manufacturing method capable of manufacturing a semiconductor device having a small element area can be realized.

[0028]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a preferred embodiment of the present invention. << Embodiment 1 >> A first embodiment of the present invention will now be described with reference to FIGS.
This will be described with reference to FIG. [Explanation of Semiconductor Device of First Embodiment (FIG. 1)] FIG. 1 is a sectional structural view of a semiconductor device having a lateral J-FET and a bipolar transistor according to a first embodiment of the present invention. . In FIG. 1, 1 is a P- type single crystal silicon substrate (hereinafter abbreviated as Si substrate), 2 is an N + type collector buried layer of a bipolar transistor, 3 is a P + type channel stopper layer, 4 is a collector region of the bipolar transistor and N constituting the channel region of the J-FET
A negative type epitaxial layer, 5 is a silicon oxide film (hereinafter abbreviated as SiO2 film) forming an isolation region, 6 is an N + type diffusion layer forming a collector wall of a bipolar transistor, and 7a and 7b are each a base lead of a bipolar transistor. P + -type polycrystalline silicon film (hereinafter abbreviated as poly-Si film) constituting an electrode and a gate electrode of J-FET, 8
Is a CVD-SiO2 film constituting an interlayer insulating film.

Reference numeral 9 denotes a SiO2 film constituting a surface protection film. Reference numerals 10a and 10b denote P + type diffusion layers which constitute the external base region of the bipolar transistor and the upper gate region of the J-FET, respectively. The external base region 10a and the upper gate region 10b have substantially the same concentration and substantially the same depth by being formed in one process. 11
Reference numerals a and 11b denote P which constitutes an active base region of a bipolar transistor and an extended gate region of a J-FET, respectively.
It is a shaped diffusion layer. The active base region 11a and the extension gate region 11b have substantially the same concentration and substantially the same depth by being formed in one step. 12 is a silicon nitride film (hereinafter abbreviated as Si3N4 film) constituting a surface protective film for improving moisture resistance, and 13 is a side wall poly constituting a spacer for forming an ultra-high frequency bipolar transistor in a self-aligned manner. Si film, 14a, 1
4b and 14c are poly-Si films constituting an emitter electrode and a collector electrode of a bipolar transistor, and a source electrode and a drain electrode of a J-FET, respectively.
Reference numerals 15b and 15c denote an emitter region, a collector contact, and a J-FET of a bipolar transistor, respectively.
Reference numeral 16 denotes a CVD-SiO2 film constituting an interlayer insulating film. Reference numeral 17 denotes an aluminum alloy wiring (Al
-Si-Cu) (the wiring shows only the electrode connection portion).

In the semiconductor device of the present embodiment configured as described above, the extended gate region 11b of the J-FET and the active base region 1 of the ultra-high frequency bipolar transistor are used.
1a, the P-type diffusion layer constituting the region including
It has a shallow depth of about 0.2 μm. With this configuration, the P-type diffusion layers 11a and 11b can be formed in one step.

The collector region of the bipolar transistor and the channel region of the J-FET are formed in one step (N-type epitaxial layer 4). To improve the high frequency characteristics (hereinafter abbreviated as fT) of the bipolar transistor, the thickness of the collector region (epitaxial layer) 4 is set to about 1 μm.
When the thickness is reduced to about m, the channel region 4 formed in the same step becomes thinner, but the channel region below the extension gate region 11b is effectively sufficiently thicker than the channel region below the upper gate region 10b. Further, the P-type diffusion layer 11
A depletion layer spreads from b to the N− type epitaxial layer 4 (channel region) (an outline of the depletion layer is shown in FIG. 1). Then, due to the electric field effect of the depletion layer, N +
Even if a high voltage is applied to the diffusion layer 14c, the pinch-off voltage is low. Therefore, while maintaining a high drain withstand voltage, J
-The on-resistance of the FET can be reduced to improve its transconductance (hereinafter abbreviated as gm).

Unlike the conventional example, the P + type diffusion layer 10a in the external base region of the bipolar transistor is surrounded by a thick isolation region (SiO2 film 5 as an insulating film) (walled base structure). Thereby, the lateral capacitance of the base-collector junction can be reduced. Further, since the base extraction electrode 7a is provided on the thick isolation region (SiO2 film 5) and not on the thin insulating film on the collector region unlike the conventional example, the parasitic MIS capacitance between the base and the collector is also reduced. it can. Therefore, the fT of the bipolar transistor can be improved.

[Method of Manufacturing Semiconductor Device of First Embodiment (FIGS. 2 to 4)] Next, a semiconductor device having a lateral J-FET and a bipolar transistor according to a first embodiment of the present invention. Will be described with reference to FIGS. 2 to 4 are cross-sectional views of the semiconductor device after each step showing the method of manufacturing the IC shown in FIG. [Description of Steps Up to FIG. 2 (FIG. 2)] An N + type collector buried layer 2 and a P-type
A positive channel stopper layer 3 is formed sequentially. next,
An N-type epitaxial layer 4 is grown on the Si substrate (for example, the specific resistance is about 0.8 Ω-cm and the thickness of the epitaxial layer is about 1 μm). Next, a predetermined isolation region is selectively oxidized by a recess LOCOS method to form an SiO2 film 5. Next, an N + type diffusion layer 6 of a collector wall is formed in a collector extraction region of the bipolar transistor.

Next, after exposing the surface of the N-type epitaxial layer 4, a poly-Si film (finally 7a or the like) is deposited on the Si substrate 1. Next, this poly Si
After boron (B) ions are implanted into the film, a CVD-SiO2 film 8 constituting an interlayer insulating film is deposited. Next, a P + -type poly-Si film 7a constituting the base electrode of the bipolar transistor and a P + -type poly-Si film 7b constituting the upper gate electrode of the J-FET are selectively formed by using the photoetching technique. CVD- for parts other than the base electrode, etc.
The SiO2 film 8 and the poly-Si film are removed. At this time, the opening A constituting the active region of the bipolar transistor
Is formed. FIG. 2 is a sectional view of the semiconductor device in a state where the above steps have been completed.

[Description of Steps Up to FIG. 3 (FIG. 3)]
The Si substrate 1 is thermally oxidized at, for example, 900 to 1000 [deg.] C. to form an SiO2 film 9 constituting a surface protection film in the opening A, the collector extraction region, and the J-FET formation region B. At this time, boron doped in the P + type poly-Si films (7a and 7b) diffuses into the Si substrate 1, and the P + type diffusion layer 1 forming the external base region of the bipolar transistor is formed.
Oa and a P + type diffusion layer 10b constituting the upper gate region of the J-FET are formed. In the present invention, the external base region 10a and the upper gate region 10b are generated in a self-aligned manner based on the shapes of the base electrode 7a (and the isolation region 5) and the upper gate electrode 7b. In the conventional example, the external base region 72g and the upper gate region 74 are
It was formed in a region formed by photo-etching the insulating film 69 (the base electrode 77b and the upper gate electrode 77).
g cannot be generated unless after the photo-etching of the insulating film because of the shape. ). Therefore, it should be noted that the IC manufacturing method of the present invention has one less photoetching step than before.

Next, boron is selectively ion-implanted into the opening A of the formation region of the bipolar transistor and the drain region of the formation region B of the J-FET including at least a part of the upper gate electrode. For example, 10-30 ke
V is about 1 to 5 × (10 13) / square cm). Next, the Si substrate 1 is heat-treated at, for example, 900 ° C. In this case, the P + type poly-Si film 7a plays the role of a mask, and the P-type diffusion layer 11a constituting the active base region in the N-type epitaxial layer 4 immediately below the opening A of the bipolar transistor forming region is reduced to about 0. Formed at a depth of about 0.1 to 0.2 .mu.m in a self-alignment manner, and at the same time, connected to the P + type diffusion layer 10b of the upper gate in the N- type epitaxial layer 4 in the formation region B of the J-FET. P-type diffusion layer 11b forming an extended gate region extending to the region is selectively formed.

Next, a Si 3 N 4 film 12 is formed on the Si substrate 1.
And a poly-Si film 13 are sequentially deposited. Here, this Si3
The N4 film 12 is a surface protective film formed to improve the moisture resistance of the bipolar transistor. Next, this poly Si
The film 13 is etched back to form a self-aligned side wall film 13 of poly-Si constituting a spacer of the ultrahigh frequency bipolar transistor on the side wall of the P + type poly-Si film 7a in the opening A. At this time, the J-FET formation region B
Then, the poly-Si film 13 other than the upper gate electrode side wall is removed. FIG. 3 is a cross-sectional view of the semiconductor device in a state where the above steps have been completed.

[Description of Steps After FIG. 3 (FIGS. 4 and 1)] Next, the Si 3 N 4 film 12 is removed by using a photoetching technique, and an emitter forming window is formed in the opening A of the bipolar transistor forming region. C and a collector forming window D are selectively opened in the collector take-out region, and at the same time, J-FE
The source and drain formation windows E in the T formation region B are selectively opened. Next, the SiO in each of the forming windows CE is formed.
2 The film 9 is removed to expose the surface of the N− type epitaxial layer 4. Next, a poly-Si film (finally 14a or the like) is deposited on the Si substrate 1, for example, to a thickness of about 200 to 300 nm. Next, the poly-Si films 14a to 14c constituting the emitter electrode, the collector electrode, the source electrode and the drain electrode are formed on the respective forming windows CE by photoetching.
14c is selectively formed.

Next, arsenic (As) is selectively ion-implanted into the poly-Si films 14a to 14c (for example, 40 to 8).
At 0 keV, about 5 to 10 × (10 to the 15th power) / square cm). Next, by heat-treating the Si substrate 1 at, for example, 900 ° C., the arsenic doped in the poly-Si films 14a to 14c diffuses into the Si substrate 1, and the N + type diffusion forming the emitter region from the emitter forming window C. A layer 15a, an N + type diffusion layer 15b forming a collector contact from the collector formation window D, and an N + type diffusion layer 15c forming a source region and a drain region from the source and drain formation window E
Is formed. FIG. 4 is a sectional view of the semiconductor device in a state where the above steps have been completed.

The following steps will be described with reference to FIG. Next, using a well-known technique, a CVD-SiO2 film 16 constituting an interlayer insulating film is deposited on the Si substrate 1 and a contact window is opened. Next, an aluminum alloy wiring (Al-Si-Cu) 17 constituting a metal wiring is formed. According to the above manufacturing method, the horizontal J-type of the present embodiment shown in FIG.
A semiconductor device having an FET and a bipolar transistor is manufactured.

According to the manufacturing method of the first embodiment having the above-described structure, it is possible (at the same time, no additional step is required) to be formed on the semiconductor substrate in the manufacturing process of the conventional ultrahigh-frequency bipolar transistor. A horizontal J-FET can be formed at the same time. That is, in the step of forming the P + type diffusion layer 10a in the external base region of the bipolar transistor, the P + type diffusion layer 10b in the upper gate region of the J-FET can be formed at the same time. Further, a photo-etching step for forming an external base region or the like is not required. Similarly, in the step of forming the active base P-type diffusion layer 11a of the bipolar transistor, the P-type diffusion layer 11b of the extended gate region of the J-FET can be formed at the same time.

Even if the thickness of the epitaxial layer is reduced to about 1 μm to improve the fT of the bipolar transistor, the channel region under the extended gate region (N− type epitaxial layer 4) is smaller than the channel region below the upper gate region. Thick enough. Further, a depletion layer spreads from the extension gate region 11b to the channel region (an outline of the depletion layer is shown in FIG. 1). Even if a high voltage is applied to the N + diffusion layer 14c in the drain region, the pinch-off voltage is reduced by the electric field effect of the depletion layer. As described above, a J-FET having a high drain withstand voltage, a low on-resistance, and a large gm can be formed on a semiconductor device.

Unlike the conventional example, the P + type diffusion layer 10a in the external base region of the bipolar transistor is surrounded by a thick SiO2 film 5 having an isolation region (walled base structure), so that its base-collector junction is formed. Side capacity is small. In addition, the base extraction electrode is also made of thick SiO.
Since it is provided on the two films 5 and is not on the thin SiO2 film on the collector region unlike the conventional example, the parasitic MIS capacitance between the base and the collector is small. Therefore, the fT of the bipolar transistor is high. The N-type epitaxial layer 4 in the collector region of the bipolar transistor
Has the same area as the base region, and it is not necessary to form the collector region adjacent to the side surface of the base region. Therefore, the element area of the bipolar transistor is smaller than that of the conventional example.
In other words, by integrating the lateral J-FET having a high gm and the bipolar transistor having a high fT on the same semiconductor substrate by using the same manufacturing process as that of the ultra-high frequency bipolar transistor and using a normal manufacturing technique. Can be.

Embodiment 2 Next, a second embodiment of the present invention will be described with reference to FIGS. [Explanation of Semiconductor Device of Second Embodiment (FIG. 5)] FIG. 5 is a sectional structural view of a semiconductor device having a lateral J-FET and a bipolar transistor according to a second embodiment of the present invention. is there. In FIG. 5, FIG.
And the common elements use the same numbers, and 1 is a P-type Si
The substrate, 2 is an N + type collector buried layer of a bipolar transistor, 3 is a P + channel stopper layer, 4 is a collector region of the bipolar transistor and J-FE.
An N- type epitaxial layer constituting a T channel region; 5, an SiO2 film as an isolation region; 6, an N + type diffusion layer constituting a collector wall of a bipolar transistor;
Reference numerals 7a and 7b denote P + constituting a base extraction electrode of a bipolar transistor and a gate electrode of a J-FET, respectively.
Poly-Si film, 8 is CVD-Si constituting an interlayer insulating film
O2 film.

Reference numeral 9 denotes a SiO2 film constituting a surface protection film. Reference numerals 10a and 10b denote P + type diffusion layers which constitute the external base region of the bipolar transistor and the upper gate region of the J-FET, respectively. The external base region 10a and the upper gate region 10b have substantially the same concentration and substantially the same depth by being formed in one process. 11
a is a P-type diffusion layer constituting an active base region of a bipolar transistor, 12 is a Si3N4 film constituting a surface protective film for improving moisture resistance, and 13 is a self-aligned ultrahigh frequency bipolar transistor. Is a poly-Si film of a side wall constituting the spacer of FIG. 14
a, 14b, 14c and 14d denote the emitter electrode, collector electrode and J-FET of a bipolar transistor, respectively.
Is a poly-Si film constituting the source and drain electrodes and the insulated gate electrode (pseudo gate electrode). These electrodes have substantially the same composition and substantially the same thickness by being formed in one step. Reference numerals 15a, 15b and 15c denote N + type diffusion layers which constitute the emitter region and collector contact of the bipolar transistor, and the source and drain regions of the J-FET, respectively.
Reference numeral 16 denotes a CVD-SiO2 film constituting an interlayer insulating film. Reference numeral 17 denotes an aluminum alloy wiring (Al-
(Si-Cu) (only the wiring is shown for the electrode connection part).

The present embodiment having the above-described structure is the same as that of J-
An N + type poly-Si film 14d constituting an insulated gate electrode is provided on the drain region side adjacent to the P + type poly-Si film 7b of the upper gate electrode of the FET. The insulated gate electrode, the drain region, the source region and the like constitute a MIS type FET. The insulated gate electrode includes a channel region, SiO 2
It is insulated by the two films 9. Epitaxial layer thickness of about 1 μm to improve fT of bipolar transistor
When the thickness is made as small as possible, the channel region of the J-FET formed in the same step also has the same thickness. Nevertheless, the channel region (N-type epitaxial layer 4) below the insulated gate electrode is effectively sufficiently thicker than the channel region below the upper gate region. Even if a high voltage is applied to the N + diffusion layer 14c in the drain region, if the metal wiring 17 connected to the insulated gate electrode is grounded to, for example, the emitter potential of a bipolar transistor, the channel region (N− The depletion layer of the MIS type FET spreads in the epitaxial layer 4) (the depletion layer is schematically shown in FIG. 5). The pinch-off voltage is reduced by the electric field effect of the depletion layer. As in the first embodiment, the semiconductor device of the second embodiment can have a J-FET having a high drain breakdown voltage, a low on-resistance, and a large gm.

The P + type diffusion layer 10a in the external base region of the bipolar transistor according to the second embodiment is different from the conventional example in that the periphery thereof is surrounded by the thick SiO2 film 5 in the isolation region (walled base structure). Therefore, the lateral capacitance of the base-collector junction of the bipolar transistor is small. Further, since the base extraction electrode is provided on the thick SiO2 film 5 and not on the thin insulating film on the collector region as in the conventional example, a parasitic MI between the base and the collector is provided.
The S capacity is also small. Therefore, as in the first embodiment, the second
The semiconductor device of the embodiment can include a bipolar transistor having a high fT.

[Method of Manufacturing Semiconductor Device of Second Embodiment (FIGS. 6 to 8)] Next, a semiconductor device having a lateral J-FET and a bipolar transistor according to a second embodiment of the present invention will be described. The manufacturing method will be described with reference to FIGS. 6 to 8 are cross-sectional views of the semiconductor device after each step showing the method of manufacturing the IC shown in FIG. [Description of Steps Up to FIG. 6 (FIG. 6)] An N + type collector buried layer 2 and a P + type
A positive channel stopper layer 3 is formed sequentially. next,
An N-type epitaxial layer 4 is grown on the Si substrate (for example, the specific resistance is about 0.8 Ω-cm and the thickness of the epitaxial layer is about 1 μm). Next, a predetermined isolation region is selectively oxidized by a recess LOCOS method to form an SiO2 film 5. Next, an N + type diffusion layer 6 of a collector wall is formed in a collector extraction region of the bipolar transistor.

Next, after exposing the surface of the N- type epitaxial layer 4, a poly-Si film (finally 7a or the like) is deposited on the Si substrate 1. Next, this poly Si
After boron (B) ions are implanted into the film, a CVD-SiO2 film 8 constituting an interlayer insulating film is deposited. Next, a P + -type poly-Si film 7a constituting the base electrode of the bipolar transistor and a P + -type poly-Si film 7b constituting the upper gate electrode of the J-FET are selectively formed by using the photoetching technique. CVD- for parts other than the base electrode, etc.
The SiO2 film 8 and the poly-Si film are removed. At this time, the opening A constituting the active region of the bipolar transistor
Is formed. FIG. 6 is a cross-sectional view of the semiconductor device in a state where the above steps have been completed.

[Description of Steps Up to FIG. 7 (FIG. 7)]
The Si substrate 1 is thermally oxidized at, for example, 900 to 1000 [deg.] C. to form an SiO2 film 9 constituting a surface protection film in the opening A, the collector extraction region, and the J-FET formation region B. At this time, boron doped in the P + type poly-Si films (7a and 7b) diffuses into the Si substrate 1, and the P + type diffusion layer 1 forming the external base region of the bipolar transistor is formed.
Oa and a P + type diffusion layer 10b constituting the upper gate region of the J-FET are formed. In the present invention, the external base region 10a and the upper gate region 10b are generated in a self-aligned manner based on the shapes of the base electrode 7a (and the isolation region 5) and the upper gate electrode 7b. In the conventional example, the external base region 72g and the upper gate region 74 are
It was formed in a region formed by photo-etching the insulating film 69 (the base electrode 77b and the upper gate electrode 77).
Since g has a shape spreading on the insulating film, g can be generated only after the photo-etching of the insulating film. ). Therefore, it should be noted that the IC manufacturing method of the present invention has one less photoetching step than before.

Next, boron is selectively ion-implanted into the opening A in the formation region of the bipolar transistor (for example, about 1 to 5 × (10 13) / square cm at 10 to 30 keV). Next, this Si substrate 1 is, for example, 900 ° C.
Heat treatment. In this case, the P + type poly-Si film 7a plays the role of a mask, and the P-type diffusion layer 11a constituting the active base region in the N-type epitaxial layer 4 immediately below the opening A of the bipolar transistor forming region is reduced to about 0. .1 to
It is formed at a depth of about 0.2 μm in a self-aligned manner.

Next, an Si 3 N 4 film 12 is formed on the Si substrate 1.
And a poly-Si film 13 are sequentially deposited. Here, this Si3
The N4 film 12 is a surface protective film formed to improve the moisture resistance of the bipolar transistor. Next, this poly Si
The film 13 is etched back to form a self-aligned side wall film 13 of poly-Si constituting a spacer of the ultrahigh frequency bipolar transistor on the side wall of the P + type poly-Si film 7a in the opening A. At this time, the J-FET formation region B
Then, the poly-Si film 13 other than the upper gate electrode side wall is removed. FIG. 7 is a cross-sectional view of the semiconductor device in a state where the above steps have been completed.

[Description of Steps After FIG. 7 (FIGS. 7 and 8)] Next, the Si 3 N 4 film 12 is removed by using a photoetching technique, and an emitter forming window is formed in the opening A of the bipolar transistor forming region. C and a collector forming window D are selectively opened in the collector take-out region, and at the same time, J-FE
The source and drain formation windows E in the T formation region B are selectively opened. Next, the SiO in each of the forming windows CE is formed.
2 The film 9 is removed to expose the surface of the N− type epitaxial layer 4. Next, a poly-Si film (finally 14a or the like) is deposited on the Si substrate 1, for example, to a thickness of about 200 to 300 nm. Next, the Si3N4 film 12 on each of the formation windows CE and the channel region is formed by using the photoetching technique.
On top, poly-Si constituting an emitter electrode, a collector electrode, a source electrode and a drain electrode, and an insulated gate electrode
The films 14a to 14d are selectively formed.

Next, arsenic (As) is selectively ion-implanted into the poly-Si films 14a to 14c (for example, 40 to 8).
At 0 keV, about 5 to 10 × (10 to the 15th power) / square cm). Next, by heat-treating the Si substrate 1 at, for example, 900 ° C., arsenic doped in the poly-Si films 14 a to 14 c diffuses into the Si substrate 1. Thereby, the N + type diffusion layer 15 constituting the emitter region is formed in the emitter forming window C.
a, an N + type diffusion layer 15b forming a collector contact in a collector forming window D, and an N + type diffusion layer 15c forming a source region and a drain region in a source and drain forming window E are formed. FIG. 8 is a sectional view of the semiconductor device in a state where the above steps have been completed.

The following steps will be described with reference to FIG. Next, using a well-known technique, a CVD-SiO2 film 16 constituting an interlayer insulating film is deposited on the Si substrate 1 and a contact window is opened. Next, an aluminum alloy wiring (Al-Si-Cu) 17 constituting a metal wiring is formed. According to the above manufacturing method, the horizontal J-type of this embodiment shown in FIG.
A semiconductor device having an FET and a bipolar transistor is manufactured.

According to the manufacturing method of the second embodiment configured as described above, the semiconductor device is formed on the semiconductor substrate simultaneously with the conventional manufacturing process of the ultrahigh-frequency bipolar transistor (no additional process is required). A horizontal J-FET can be formed at the same time. That is, in the step of forming the P + type diffusion layer 10a in the external base region of the bipolar transistor, the P + type diffusion layer 10b in the upper gate region of the J-FET can be formed at the same time. Further, a photo-etching step for forming an external base region or the like is not required. Similarly, an active base emitter electrode 14a of a bipolar transistor
Can be formed simultaneously with the insulated gate electrode 14d of the J-FET.

Even if the thickness of the epitaxial layer is reduced to about 1 μm to improve the fT of the bipolar transistor, the channel region (N− type epitaxial layer 4) under the insulated gate electrode 14d remains in the channel region under the upper gate region. It is much thicker than that. Also, the N of the drain region
Even if a high voltage is applied to + diffusion layer 14c, if metal wiring 17 connected to the insulated gate electrode is grounded to, for example, the emitter potential of a bipolar transistor, the channel region under the insulated gate electrode (N− type epitaxial layer 4) The depletion layer of the MIS FET expands (see FIG.
Shown). The pinch-off voltage is reduced by the electric field effect of the depletion layer. The semiconductor device of the second embodiment is
A J-FET having a high drain withstand voltage, a low on-resistance, and a large gm can be provided.

Since the P + type diffusion layer 10a in the external base region of the bipolar transistor is surrounded by a thick SiO2 film 5 having an isolation region (walled base structure), unlike the conventional example, the base-collector junction is formed. Side capacity is small. In addition, the base extraction electrode is also made of thick SiO.
Since it is provided on the two films 5 and is not on the thin SiO2 film on the collector region unlike the conventional example, the parasitic MIS capacitance between the base and the collector is small. Therefore, the fT of the bipolar transistor is high. The N-type epitaxial layer 4 in the collector region of the bipolar transistor
Has the same area as the base region, so that the element area of the bipolar transistor is smaller than that of the conventional example. In other words, a horizontal J with a high gm is manufactured in the same manufacturing process as that of the ultra-high-frequency bipolar transistor and using a normal manufacturing technique.
-The FET and the bipolar transistor having a high fT can be integrated on the same semiconductor substrate.

In the above embodiment, the present invention is applied to a bipolar IC. However, the present invention is not limited to this. For example, the present invention may be applied to a mixed analog / digital bipolar CMOS IC. It can also be applied to Further, the semiconductor device of the embodiment has an isolation region made of a SiO2 film formed by the recess LOCOS method, but is not limited thereto.
The isolation region can be formed by the OCOS method. Further, in the embodiment, the P + type diffusion layer constituting the upper gate region is formed by impurity diffusion from the doped poly-Si film. However, the present invention is not limited to this. For example, the P + type diffusion layer is formed by ion implantation. Can also be formed.

[0060]

As described above, according to the present invention, the horizontal J-
In a semiconductor device in which an FET and a bipolar transistor are integrated, a J-type transistor having a high transconductance is provided.
An advantageous effect is obtained that it is possible to achieve both a FET and a bipolar transistor having a high cutoff frequency. In addition, the above-described semiconductor device can be manufactured by using a normal manufacturing technique without adding any process in the same manufacturing process as the bipolar transistor. Also, a photo-etching step for forming the upper gate region and the like is unnecessary. Therefore,
According to the present invention, there is obtained an advantageous effect that an excellent semiconductor device capable of improving performance and reducing cost with a simple configuration and a method of manufacturing the same can be realized.

The extended gate region or the insulated gate electrode of the present invention reduces the pinch-off voltage of the J-FET due to the electric field effect of the depletion layer extending in the channel region (semiconductor layer) under the extended gate region or the insulated gate electrode. A J-FET with low on-resistance and high transconductance is realized. According to the present invention, there is obtained an advantageous effect that a semiconductor device having a J-FET having a low pinch-off voltage, a low on-resistance and a high transconductance can be realized.

The upper gate region of the semiconductor device of the present invention can be manufactured in the same process as the external base region of the bipolar transistor. Further, the external base region and the upper gate region can be generated in a self-aligned manner based on the shapes of the base electrode (the base electrode and the isolation region in the invention of claim 3) and the upper gate electrode (external base region). No photo-etching is required to form such a pattern.) Therefore, the IC of the present invention can be manufactured by a manufacturing method having one less photoetching step than before. The extended gate region of the semiconductor device of the present invention can be manufactured in the same process as the active base region of the bipolar transistor, or the insulated gate electrode of the semiconductor device of the present invention can be manufactured in the same process as the emitter electrode of the bipolar transistor. Manufacturing is possible. Therefore, the present invention has an effect that a semiconductor device which is easy to manufacture and has high productivity can be realized.

The external base region of the semiconductor device of the present invention
Since the outer peripheral portion has a walled base structure surrounded by an insulating film, the side surface capacitance of the base-collector junction surface is small,
In addition, since there is a distance between the base electrode and the collector electrode, the base-collector capacitance (Ccb) is small. According to the present invention, there is further obtained an advantageous effect that a semiconductor device including a bipolar transistor having a high cutoff frequency (fT) can be realized.

In the bipolar transistor of the semiconductor device according to the present invention, it is not necessary to form a collector region adjacent to the external base region. No need to form. Therefore, the present invention has an advantageous effect that a semiconductor device having a small element area can be realized.

The method of manufacturing a semiconductor device according to the present invention uses a horizontal J-FET having a high transconductance and a bipolar transistor having a high cutoff frequency in the same manufacturing process as that of an ultra-high-frequency bipolar transistor and using a normal manufacturing technique. An advantageous effect of realizing a manufacturing method capable of manufacturing a semiconductor device having integrated type transistors is obtained. A semiconductor device manufactured by the method for manufacturing a semiconductor device of the present invention has an extended gate region or an insulated gate electrode of a J-FET, and the extended gate region or the insulated gate electrode is a J-FET.
-Reduce the pinch-off voltage of the FET to realize a J-FET with low on-resistance and high transconductance. Therefore, the present invention has an advantageous effect that a method of manufacturing a semiconductor device having a J-FET having a low pinch-off voltage, a low on-resistance, and a high transconductance can be realized.

The upper gate region of the semiconductor device according to the present invention is manufactured in the same process as the external base region of the bipolar transistor. Further, the external base region and the upper gate region are generated in a self-aligned manner based on the shapes of the base electrode (the base electrode and the isolation region in the invention of claim 7) and the upper gate electrode (the external base region and the like are formed). Photo-etching for forming is not necessary.) Therefore, the IC manufacturing method of the present invention has one less photoetching step than the conventional method. In the method for manufacturing a semiconductor device of the present invention, the extended gate region is manufactured in the same step as the active base region of the bipolar transistor, or the insulated gate electrode of the semiconductor device of the present invention is the same as the emitter electrode of the bipolar transistor. Manufactured in process. Therefore, according to the present invention, there is obtained an advantageous effect that a method of manufacturing a semiconductor device which is easy to manufacture and has high productivity can be realized.

Preferably, in the method of manufacturing a semiconductor device according to the present invention, the outer peripheral portion of the external base region of the bipolar transistor is surrounded by an insulating film (walled base structure). According to the present invention, there is obtained an advantageous effect that a semiconductor device manufacturing method capable of manufacturing a semiconductor device including a bipolar transistor having a high cutoff frequency (fT) can be realized.

Further, since there is no need to form a collector region adjacent to the outer base region, it is not necessary to form a collector region with a margin for mask alignment unlike the conventional example. Therefore, according to the present invention, there is obtained an advantageous effect that a semiconductor device manufacturing method capable of manufacturing a semiconductor device having a small element area can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, showing a method of manufacturing the semiconductor device after an intermediate step;

FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, showing a method of manufacturing the semiconductor device after an intermediate step;

FIG. 4 is a cross-sectional view of the semiconductor device after an intermediate step, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional structural view of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention, showing a method of manufacturing the semiconductor device after an intermediate step;

FIG. 7 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention, showing a method of manufacturing the semiconductor device after an intermediate step;

FIG. 8 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention, showing a method of manufacturing the semiconductor device after an intermediate step;

FIG. 9 is a cross-sectional structural view of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 P- type semiconductor substrate 2 N + type buried diffusion layer 3 P + type buried diffusion layer 4 N- type semiconductor layer 5 silicon oxide film 6 N + type diffusion layer 7 a, 7 b P + type polycrystalline silicon film 8 silicon oxide film 9 silicon oxide film 10a, 10b First P + type diffusion layer 11a, 11b Second P type diffusion layer 12 Silicon nitride film 13 Polycrystalline silicon film 14a, 14b, 14c, 14d N + type polycrystalline silicon film 15a, 15b, 15c Third N + type diffusion layer 16 Silicon oxide film 17 Metal wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/808 F term (Reference) 5F003 BA13 BA96 BB01 BB02 BC01 BC07 BC08 BJ16 BM01 BP04 BP11 BP21 BP41 BS06 BS08 5F082 AA06 AA08 AA25 BA03 BC01 BC08 DA10 EA04 EA27 EA33 EA45 5F102 FA03 GA12 GB01 GC01 GD04 GJ03 GT08 GV06 GV07 GV08

Claims (7)

[Claims] 1. A semiconductor device having a lateral junction field-effect transistor and a bipolar transistor on a semiconductor substrate of a second conductivity type, wherein the junction field-effect transistor is disposed on one main surface of the substrate. A channel region provided with a semiconductor layer of a first conductivity type, an upper gate region provided in a predetermined region of the substrate and made of a first diffusion layer of a second conductivity type and a high concentration; A source electrode and a drain electrode respectively provided on both sides, and an extended gate region provided on the drain electrode side of the upper gate region and formed of a second diffusion layer of a second conductivity type and low concentration. The bipolar transistor includes: an external base region including a second conductivity type diffusion layer having substantially the same concentration and substantially the same depth as the first diffusion layer; An active base region comprising a diffusion layer of the second conductivity type having substantially the same concentration and substantially the same depth as the second diffusion layer. 2. A semiconductor device having a lateral junction field-effect transistor and a bipolar transistor on a semiconductor substrate of a second conductivity type, wherein the junction field-effect transistor is disposed on one main surface of the substrate. A channel region provided with a semiconductor layer of a first conductivity type, an upper gate region provided in a predetermined region of the substrate and formed of a first diffusion layer of a second conductivity type, provided on the upper gate region; A junction type upper gate electrode, a source electrode and a drain electrode respectively provided on both sides of the upper gate region, and a first conductivity type provided on the channel region on the drain electrode side of the upper gate region. An insulating gate electrode made of a semiconductor film, wherein the bipolar transistor has substantially the same concentration and substantially the same depth as the first diffusion layer. An external base region comprising a diffusion layer of the second conductivity type, and an emitter electrode comprising a semiconductor film of the first conductivity type having substantially the same composition and thickness as the semiconductor film. A semiconductor device characterized by the above-mentioned. 3. The semiconductor device according to claim 1, wherein an outer peripheral portion of said external base region is surrounded by an insulating film. 4. A method of manufacturing a semiconductor device having a lateral junction field-effect transistor and a bipolar transistor on a semiconductor substrate of a second conductivity type, wherein said junction field-effect transistor is provided on one main surface of said substrate. Forming a first conductivity type semiconductor layer forming a region including a channel region of the transistor and a collector region of the bipolar transistor; and forming an upper gate region of the junction field effect transistor in a predetermined region of the substrate. Forming a high-concentration first diffusion layer of a second conductivity type forming a region including an external base region of the bipolar transistor; and providing a high concentration first diffusion layer on the drain region side of the upper gate region. A region including an extended gate region of the junction field effect transistor and an active base region of the bipolar transistor is formed. Forming a low-concentration second diffusion layer with a second conductivity type to be formed; and forming a region including a source region and a drain region of the junction field-effect transistor on both sides of the upper gate region. Forming a third diffusion layer of a conductivity type. A method for manufacturing a semiconductor device, comprising: 5. A method of manufacturing a semiconductor device having a lateral junction field-effect transistor and a bipolar transistor on a semiconductor substrate of a second conductivity type, wherein the junction field-effect transistor is provided on one main surface of the substrate. Forming a first conductivity type semiconductor layer forming a region including a channel region of the transistor and a collector region of the bipolar transistor; and forming a junction type upper gate electrode of the junction field effect transistor and the bipolar transistor. Forming a second conductivity type semiconductor film forming a portion including a base electrode; including, in predetermined regions of the substrate, an upper gate region of the junction field effect transistor and an external base region of the bipolar transistor, respectively. Forming a first diffusion layer of a second conductivity type forming a region; Forming a first conductivity type semiconductor film constituting a portion including the insulated gate electrode of the junction field effect transistor and the emitter electrode of the bipolar transistor provided on the channel region on the drain region side of the region And forming a second diffusion layer of a first conductivity type on both sides of the first diffusion layer to form a region including a source region and a drain region of the junction field effect transistor. A method for manufacturing a semiconductor device. 6. The external base region is formed by diffusing a second conductivity type impurity from a first polycrystalline silicon film forming the base electrode of the bipolar transistor, and the emitter electrode is formed of a second polycrystalline silicon film. The method of manufacturing a semiconductor device according to claim 4, wherein an impurity of the first conductivity type is formed by diffusing the impurity into the polycrystalline silicon film. 7. The method for manufacturing a semiconductor device according to claim 4, further comprising a step of forming an insulating film surrounding an outer peripheral portion of said external base region. .