JP2001306158A - Power source voltage monitoring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power source voltage monitoring circuit which dispenses with a fixed voltage circuit as a reference value and is able to monitor power source voltage down to low voltage. SOLUTION: This invention is provided with divided voltage means D1, R1, R2, a comparator CMP which inputs divided voltage VCX and zero voltage GND compares both voltages, and output transistor means Q1, Q2, Q3 which output monitoring signals at an output terminal through the comparator's output. The comparator compares offset voltage VOS which is acquired from the area ratio with the divided voltage VCX. The comparator's power source voltage can be lowered down to around 1 V and the voltage area can be monitored by setting up the threshold voltage which monitor power source voltage as around 1 V. By setting up values for divided voltage resistors R1, R2 equalized to the partial differential of temperature between the forward voltage of diode D1 and the offset voltage of the comparator CMP, the temperature characteristic of the threshold voltage VTH can be set off and the stable monitoring of power source voltage regardless of the changes in temperature is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for monitoring a power supply voltage, and more particularly to a power supply voltage monitoring circuit capable of detecting a decrease in the power supply voltage with high accuracy.

[0002]

2. Description of the Related Art In various electronic circuits, when the power supply voltage decreases, the operation of each circuit element becomes unstable, and normal operation may not be guaranteed. Therefore, a power supply voltage monitoring circuit that monitors a power supply voltage and outputs a predetermined signal when the power supply voltage falls below a predetermined voltage is provided.
FIG. 5 is a circuit diagram of an example of a conventional power supply voltage monitoring circuit.
In the figure, the power supply voltage VCC is divided by resistors R1 and R2
Then, the divided voltage V1 is input to the negative input of the comparator CMP. The positive input of the comparator CMP has a reference voltage V0 output from the constant voltage circuit VGEN.
Is entered. Here, the reference voltage V0 is set to a limit voltage at which the power supply voltage VCC is reduced, that is, a voltage related to a voltage reduction operation limit voltage. The output of the comparator CMP has an emitter grounded and a collector connected to the power supply voltage V via four diodes and a resistor R3.
The base of the first NPN transistor Q1 connected to the CC is connected, the emitter of the first NPN transistor Q1 is grounded to the collector, and the collector of the first NPN transistor Q1 is connected to the power supply voltage VCC via the resistor R4. The base of Q2 is connected, and the collector of the second NPN transistor Q2 is connected to the base of a third NPN transistor Q3 whose emitter is grounded and whose collector is connected to the output terminal.

In this conventional power supply voltage monitoring circuit, when the power supply voltage VCC is higher than a predetermined threshold voltage, that is, the divided voltage V1 of the voltage dividing resistors R1 and R2 corresponds to the threshold voltage. When the reference voltage V0 is higher than the reference voltage V0, the output of the comparator CMP is “0”,
The transistor Q1 is off, the second transistor Q2 is on, the third transistor Q3 is off, and the output terminal OUT
Is "1" level. On the other hand, the power supply voltage VCC becomes equal to or lower than the threshold voltage, and the divided voltage V1 of the voltage dividing resistors R1 and R2 is reduced.
When 1 becomes equal to or lower than the reference voltage V0, the output of the comparator CMP becomes “1”, the first transistor Q1 turns on,
The second transistor Q2 is turned off, the third transistor Q3 is turned on, and the output terminal OUT becomes "0" level. As a result, it is detected that the power supply voltage has dropped below the voltage reduction operating limit voltage.

[0004]

In such a power supply voltage monitoring circuit, a constant voltage circuit VGE for outputting a reference voltage V0 is provided.
N is also operated by the power supply voltage VCC. for that reason,
When the power supply voltage VCC falls below a voltage at which the constant voltage circuit VGEN operates normally, the reference voltage V0 output from the constant voltage circuit VGEN becomes unstable, and as a result, an appropriate voltage comparison in the comparator CMP is not performed, and The output of the CMP becomes unstable. Therefore, the level of the output terminal OUT indicating the monitoring result output by the first to third transistors Q1 to Q3 becomes unstable, and an erroneous output may occur.

To cope with such a problem, in the conventional power supply voltage monitoring circuit described above, the base of the second transistor Q2 is connected to the power supply voltage VCC via four diodes Dx and a resistor R3. Therefore, four diodes D
x, a voltage approximately 3 V lower than the power supply voltage VCC due to the forward voltage VF of x and the voltage drop of the resistor R3.
Will be added to the base. Therefore, before the power supply voltage VCC falls below a voltage at which the constant voltage circuit VGEN does not operate normally (about 2 V in a normal constant voltage circuit), the base potential of the second transistor Q2 decreases and the second transistor Q2 decreases. Q2 turns off, thereby turning on the third transistor Q3, and "0" is output to the output terminal OUT. For this reason, when the power supply voltage VCC becomes lower than the reduced voltage operation limit voltage, the output of the output terminal OUT of the monitoring circuit is fixed, and the output is stabilized.

However, this circuit is a symptomatic method in which the output logic is switched to the normal logic in a power supply voltage region that is so low that the constant voltage circuit VGEN cannot operate normally, and the setting range of the threshold voltage for power supply monitoring is There is a trade-off that the constant voltage circuit is limited to a high power supply voltage range that can normally operate. That is, in order for the power supply voltage monitoring circuit to operate as intended, the threshold voltage must be
The condition is that the GEN is set to a power supply voltage region where normal operation is possible. When a general band gap circuit is used as the constant voltage circuit VGEN, the lower limit of the power supply voltage that can function normally is about 2 V as described above, and therefore, the threshold voltage must be set to 2 V or more.

Therefore, to realize a power supply voltage monitoring circuit that requires a lower threshold voltage, a constant voltage circuit operable down to a lower power supply voltage is required. In general, the type of constant voltage circuit has a low output voltage accuracy, which causes a deterioration in power supply voltage detection accuracy in the power supply voltage monitoring circuit. As an example, when the forward voltage VF of the diode is used as a constant voltage circuit,
Variation in absolute value of VF ± 50 mV, temperature fluctuation 200 m
Depending on V (−20 to 80 ° C.), for example, when aiming at 1 V, the detection voltage accuracy has a variation width of about 0.8 to 1.2 V.

An object of the present invention is to provide a power supply voltage monitoring circuit capable of monitoring a power supply voltage to a low voltage by eliminating the need for a constant voltage circuit.

[0009]

A power supply voltage monitoring circuit according to the present invention comprises: a voltage dividing means for dividing a power supply voltage; a divided voltage and a zero voltage which are inputted; A comparator for outputting a comparison result; and an output transistor means for outputting a monitoring signal based on an output of the comparator. The comparator provides an area ratio to a pair of transistors constituting an input-stage differential amplifier. And the offset voltage obtained from the above is compared with the divided voltage.

Here, the voltage dividing means includes a diode,
Preferably, a voltage dividing resistor group is provided, and a voltage obtained by stepping down the power supply voltage by the diode is divided by the voltage dividing resistor group, and the divided voltage is set as a divided voltage to be input to the comparator. Alternatively, the voltage dividing means includes a diode and a voltage dividing resistor group, divides the voltage between both ends of the diode by a first voltage dividing resistor group, and reduces the power supply voltage reduced by voltage division to a second voltage dividing voltage. It is preferable that the voltage be divided by a resistor group to be a divided voltage input to the comparator. In this case, it is preferable that the value of the voltage dividing resistor group is set such that values obtained by partially differentiating the voltage after dividing the resistance and the offset voltage of the comparator with respect to temperature are equal.

In the present invention, when the power supply voltage becomes lower than a voltage at which the comparator operates normally, the output transistor means operates independently of the output of the comparator. The circuit is configured as a circuit for fixing the monitoring signal output from. In this case, the circuit that fixes the monitoring signal includes a diode that steps down the power supply voltage and inputs the power supply voltage to the output transistor means, and the power supply voltage stepped down by the diode is higher than a voltage at which the comparator operates normally. The output of the output transistor means is fixed when the voltage of the output transistor also becomes low.

According to the present invention, the comparator has a configuration in which the transistor pair forming the differential amplifier at the input stage is provided with an offset voltage by giving an area ratio, thereby inputting a zero voltage to one of the inputs, A divided voltage obtained by dividing the power supply voltage is input to the other, and the input can be compared to monitor a decrease in the power supply voltage. As a result, the power supply voltage for normal operation of the comparator can be reduced to about 1 V, and the threshold voltage for monitoring the power supply voltage is reduced to 1 V.
By setting the voltage to a low level, the power supply voltage can be monitored up to the low voltage range.

Further, the voltage dividing resistor group is set so that the voltage-differentiated voltage by the means for outputting the divided voltage and the partial differentiation of the offset voltage of the comparator with the temperature are equalized, so that the power supply voltage is set. Offsets the temperature characteristics of the threshold voltage for monitoring the power supply voltage, and enables stable monitoring of the power supply voltage regardless of the temperature change.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a specific circuit configuration. In these figures, a first diode D1 and a voltage dividing resistor R are provided between a power supply voltage VCC and a ground GND.
1 and R2 are cascaded to divide the power supply voltage VCC, and the voltage VCX output from the connection point between the voltage dividing resistors R1 and R2 is input to the negative input of the comparator CMP. The positive input of the comparator CMP is connected to the GND, but since the comparator CMP has an offset voltage VOS as described later, the offset voltage VO is substantially applied to the positive input.
This is equivalent to inputting S.

The output of the comparator CMP has an emitter grounded and a collector connected to the second diode D2.
And the first N connected to the power supply voltage VCC via the resistor R3.
The base of the PN transistor Q1 is connected, the emitter of the first NPN transistor Q1 is grounded, and the base of the second NPN transistor Q2 whose collector is connected to the power supply voltage VCC via the resistor R4 is connected. The base of the third NPN transistor Q3 whose emitter is grounded and whose collector is connected to the output terminal OUT is connected to the collector of the second NPN transistor Q2.

As shown in FIG. 2, the comparator CMP comprises a differential amplifier circuit, and a pair of PNP transistors Q1 constituting an input differential amplifier.
1, Q12 is formed such that the size (area) of each emitter is 1: n. Here, the area of one PNP transistor Q11 serving as a positive input is formed to be 1 / n of the area of the other PNP transistor Q12 serving as a negative input. Therefore, both PNP transistors Q11, Q1
2 causes a difference in drive current between the two PNP transistors Q1
1, the offset voltage VOS is provided between Q12. This offset voltage VOS is determined by the following equation: VOS = (kT / q) × (log) n (1) Here, k is Boltzmann's constant, q is the charge amount of electrons, T, and absolute temperature. Therefore, the PNP transistor Q11 on the side having a small emitter area on the positive input side
Is connected to the ground GND (zero potential), the circuit becomes equivalent to a circuit in which the offset voltage VOS is input relatively to the pair of the negative input side PNP transistor Q12.

A voltage VCX divided by the first diode D1 and the voltage dividing resistors R1 and R2 is inputted to a negative input of the comparator CMP.
CX is VCX = (VCC−VF) × R1 / (R1 + R2) (2) Here, VF is a forward voltage drop of the first diode D1, that is, an emitter-base voltage VBE.

According to the above configuration, the comparator CMP
, A divided voltage VCX obtained by dividing the power supply voltage VCC
And the offset voltage VOS, and the level of the output terminal is changed based on the comparison result to monitor the power supply voltage. That is, the divided voltage VCX is equal to the offset voltage VOS.
If it is higher, the output of the comparator CMP becomes “0”, the first NPN transistor Q1 is turned off,
The second NPN transistor Q2 is turned on, the third NPN transistor Q3 is turned off, and the output terminal OUT becomes "1" level. Also, the divided voltage VCX is equal to the offset voltage V
When the value becomes OS or less, the output of the comparator CMP becomes “1”.
Thus, the first NPN transistor Q1 is turned on, the second NPN transistor Q2 is turned off, the third NPN transistor Q3 is turned on, and the output terminal OUT is at the “0” level.

Here, when the power supply voltage VCC ′ when the divided voltage VCX is equal to the offset voltage VOS is calculated, VCC ′ = VOS × (R1 + R2) / R1 + VF = (kT / q) × (log) n × (R1 + R2) ) / R1 + VF (3) Therefore, the power supply voltage VCC 'is set to the threshold voltage VTH of the power supply voltage VCC (VCC' =
VTH) A divided voltage VC by the dividing resistors R1 and R2.
By setting X, the power supply voltage VCC becomes the threshold voltage V
When the voltage falls below TH, “0” is output to the output terminal OUT, and the power supply voltage can be monitored.

Since the comparator CMP has the offset voltage VOS and is configured to be able to input a zero potential to the positive input, the power supply voltage for normal operation may be about 1 V. Therefore, the threshold voltage VTH can be set to a low voltage of about 1 V, and the power supply voltage VCC for the low voltage can be monitored. Further, the power supply voltage VCC becomes 1 when the comparator CMP becomes inoperable.
Even if the voltage becomes lower than about V and the output of the comparator CMP becomes unstable, the second diode D2 connected to the base of the second NPN transistor Q2
The second NPN transistor Q2 is turned off by the voltage drop between the third NPN transistor Q3 and the resistor R3.
Is kept on.

As a result, in the conventional circuit shown in FIG. 5, the number of diodes Dx connected in series between the power supply voltage VCC and the base for forcibly turning off the second NPN transistor Q2 is a constant voltage. The power supply voltage region (voltage region of 2 V or more) in which the circuit VGEN does not operate normally must be determined so as to be masked. For this purpose, three or more (four) diodes Dx are required. Circuit does not have a constant voltage circuit and the comparator CM
The power supply voltage region (voltage region of about 1 V) where P does not operate normally may be determined so as to be masked. The second diode D2 may be one stage, and the lower limit of the power supply voltage detection set value can be expanded. Therefore, the trade-off seen in the conventional example does not occur with the expansion of the voltage reduction operation limit.

FIG. 3 shows a power supply voltage VCC, a divided voltage VCX, a threshold voltage VTH with respect to the power supply voltage VCC,
A voltage for forcibly turning off the second NPN transistor Q2, an operation limit voltage of the comparator CMP, a third NPN
FIG. 9 is a diagram illustrating a limit voltage at which the transistor Q3 can be kept on, and a level of an output terminal OUT as an output of the power supply voltage monitoring circuit. From the figure, it can be seen that the power supply voltage VCC is
It can be seen that the output of the power supply voltage monitoring circuit goes to the “0” level when the voltage falls below TH. When the voltage drops below the limit voltage at which the third NPN transistor Q3 can be kept on, a voltage dependent on the power supply voltage VCC is output to the output terminal. It does not substantially affect the output of the monitoring circuit.

Further, in this embodiment, since the first diode D1 is provided in the circuit for obtaining the divided voltage VCX of the power supply voltage VCC, the divided voltage may fluctuate due to the temperature characteristics of the first diode D1. Is such that a value obtained by partially differentiating VOS and VF with respect to each absolute temperature on the right side of the equation (3) indicating the threshold voltage VCC ′ holds, that is, d [VOS × (R1 + R2) / R1] / dT = D [−VF] / dT (4) When this is rewritten for VOS, d [(kT / q) × (log) n × (R1 + R2) / R1] / dT = d [−VF] / dT .. (5) By setting each resistance value of the voltage dividing resistors R1 and R2 so that the following equation is obtained, the temperature coefficient of the threshold voltage VTH is made zero, and stable power supply voltage monitoring can be performed regardless of a temperature change. Become.

Here, as shown in FIG. 4, the divided voltage VC
As a circuit for obtaining X, a first diode D1 and a constant current source I1 are connected between a power supply voltage VCC and a ground GND, and a voltage dividing resistor R is connected in parallel with the first diode D1.
a, Rb are connected to each other, and the voltage VFZ divided by these voltage dividing resistors Ra, Rb is applied to the voltage dividing resistor R as in the above-described embodiment.
The pressure may be divided by 1, R2. Here, the divided voltage VF
Z is VFZ = VF × Ra / (Ra + Rb). When VFZ is substituted for VF in the equation (2), the divided voltage VCX ′ is VCX ′ = (VCC−VF × Ra / (Ra + Rb)) × R1 / (R1 + R2) (2 ′) As described above, by dividing the VF of the first diode D1 by resistance, the values of the voltage dividing resistors R1 and R2 and the values of the voltage dividing resistors Ra and Rb are arbitrarily set, so that the positive input of the comparator CMP is input. Divided voltage VC
X ′, in other words, the threshold voltage for monitoring the power supply voltage VCC can be arbitrarily and finely set. Furthermore, it is also possible to change the number of stages of the first diode to realize different threshold values.

[0025]

As described above, the present invention relates to a configuration in which a comparator for comparing a power supply voltage with a reference value is provided with an offset voltage by giving an area ratio to a pair of transistors constituting a differential amplifier in an input stage. By doing so, it becomes possible to input a zero voltage to one of the inputs, input a divided voltage obtained by dividing the power supply voltage to the other input, and compare these inputs to monitor a drop in the power supply voltage. As a result, the power supply voltage for normal operation of the comparator can be reduced to about 1 V, the threshold voltage for monitoring the power supply voltage is set to a low voltage of about 1 V, and the power supply voltage is monitored up to the low voltage region. Can be performed. Also, the power supply voltage is monitored by setting a voltage dividing resistor group so that the partial differential of the diode provided in the means for outputting the divided voltage and the offset voltage of the comparator with the temperature is equalized. The temperature characteristics of the threshold voltage are offset, and stable power supply voltage monitoring can be performed regardless of temperature changes.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a power supply voltage monitoring circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a specific example of the circuit of FIG.

FIG. 3 is a timing chart of the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

FIG. 5 is a circuit diagram of an example of a conventional power supply voltage monitoring circuit.

[Explanation of symbols]

 CMP Comparator R1, R2, Ra, Rb Voltage dividing resistor D1 First diode D2 Second diode Q1 First output transistor Q2 Second output transistor Q3 Third output transistor VCC Power supply voltage VTH (= VCC ') Threshold value Voltage VCX, VCX 'Divided voltage VF Diode forward voltage VOS offset voltage VFX Diode divided voltage

Continuation of the front page F term (reference) 2G035 AA03 AA21 AA26 AB02 AC15 AD02 AD04 AD11 AD23 AD56 5H410 BB04 CC02 DD02 EA10 EA12 EB01 EB37 FF03 FF22 LL04 5H420 BB03 BB12 CC02 DD02 EA11 EA18 EA23 EB15 NA23 EB23 NB12 NC02 NC03 NC23 NC26 NE13

Claims (6)

[Claims] 1. A voltage dividing means for dividing a power supply voltage, a comparator for inputting the divided voltage and zero voltage, comparing the two voltages and outputting a comparison result, and an output of the comparator. Output transistor means for outputting a monitoring signal, wherein the comparator has a transistor pair constituting an input stage differential amplifier having an area ratio, and compares an offset voltage obtained from the area ratio with the divided voltage. A power supply voltage monitoring circuit, characterized in that: 2. The voltage dividing means includes a diode and a voltage dividing resistor group, divides a voltage obtained by stepping down the power supply voltage by the diode with the voltage dividing resistor group, and supplies the divided voltage to the comparator. The power supply voltage monitoring circuit according to claim 1, wherein the divided voltage is an input divided voltage. 3. The voltage dividing means includes a diode and a voltage dividing resistor group, divides a voltage across the diode by a first voltage dividing resistor group, and reduces the power supply voltage reduced by the voltage division to a second voltage. 2. The power supply voltage monitoring circuit according to claim 1, wherein the divided voltage is divided by two voltage-dividing resistor groups to obtain a divided voltage to be input to the comparator. 3. 4. The value of the voltage dividing resistor group is set such that values obtained by partially differentiating the voltage after dividing the resistance and the offset voltage of the comparator with respect to temperature are equal. The power supply voltage monitoring circuit according to any one of claims 1 to 3. 5. The output transistor means output from the output transistor means when the power supply voltage becomes lower than a voltage at which the comparator operates normally, regardless of the output of the comparator. 5. The power supply voltage monitoring circuit according to claim 1, wherein the power supply voltage monitoring circuit is configured as a circuit for fixing a monitoring signal. 6. The circuit for fixing the monitoring signal includes a diode for stepping down the power supply voltage and inputting it to the output transistor means, and the power supply voltage stepped down by the diode causes the comparator to operate normally. The power supply voltage monitoring circuit according to claim 5, wherein the output of the output transistor means is fixed when the voltage becomes lower than the voltage.