JPH1079652A - Hysteresis comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the genereation of abnormal output oscillation by preparing plural reference voltage levels, switching reference voltage to be used for comparison and generating hysteresis before an input signal reaches the reference voltage due to its rise or drop and a compared result is inverted. SOLUTION: In the OFF state of all transistors(TRs) Q9 , Q12 , Q15 , 1st reference voltage VREF0 obtained by dividing power supply voltage VCC by resistors R1 , R2 , is applied to a TR Q2 . When the TR Q15 is turend on, a resistor R10 is connected in parallel with the resistor R2 and the reference voltage VREF0 is dropped to 2nd reference voltage VREF1 (VREF1 <VREF0 ) and hysteresis is generated. Thereby voltage V1 is quickly dropped, the TR Qq , is turned on and an output signal VOUT is inverted from a low level to a high level. Finally the TR Q12 is turned on, resistors R10 , R3 are connected in parallel with the resistor R2 and the reference voltage VREF1 is dropped to 3rd reference voltage VREF2 (VREF2 < VREF1 ).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hysteresis comparator, and more particularly, to a comparator having hysteresis characteristics.

[0002]

2. Description of the Related Art Conventionally, a comparator having a hysteresis characteristic has been used to prevent chattering. For example, Japanese Patent Application Laid-Open No. Hei 5-291899 discloses that a differential circuit is used when a capacitor is used as a feedback element between an output terminal and a non-inverting input terminal. To eliminate the extension of the pulse width due to hysteresis.

If there is no hysteresis characteristic, if the input signal contains noise, the output signal vibrates unnecessarily due to the noise, so-called chattering occurs. Also, even if the input signal does not contain noise, if the voltage change of the input signal is gentle, the power supply voltage and the reference voltage of the comparator fluctuate by switching the low level / high level of the comparator output, An abnormal output vibration such as a reversal of the comparator output occurs.

FIG. 15 is a circuit diagram showing an example of a conventional hysteresis comparator. In the figure, an input signal is supplied from the terminal 10 VIN + is applied to the base of the transistor Q _1. The reference voltage V _REF to the base of the transistor Q ₂ is
As a result, the voltage VIN− is applied to the transistors Q ₃ and Q ₄
Is differentially amplified. Here, for example, the input signal VIN + is changes from the low level to the high level, the collector of the transistor Q ₇ is changed from the high level to the low level. Thus, first transistor Q ₁₁ is turned off, the transistor Q ₁₂ is turned on, the previous power supply voltage V _CC resistors R _1, voltage at R ₂ divide obtain a reference voltage V _REF V
While was a IN-, the resistor R ₂ in parallel with the resistor R ₃
Is connected, the reference voltage V _REF decreases as shown in FIG. After the transistor Q ₁₁ is turned off, the transistor Q ₈ is turned off, the transistor Q ₉ is turned on, the signal VOUT which transistor Q ₁₀ is outputted from the terminal 10 is turned off is at the high level as shown in FIG. 16.

[0005]

The circuit shown in FIG.
When the signal VIN + changes from high level to low level,
Transistor Q₇Collectors are low to high
Changes to At this time, first, the transistor Q₈Is on
And transistor Q₉Turns off and the transistor Q _TenBut
And the output signal VOUT becomes low level. After this,
Transistor Q₁₁Turns on and the transistor Q₁₂Turns off
Reference voltage V_REFRises.

In this case, after the level of the output signal VOUT is inverted, the reference voltage V _REF changes and hysteresis is applied. As described above, the level of the output signal is inverted before the hysteresis is applied, so that there is a problem that abnormal output vibration may occur.

[0007] The present invention has been made in view of the above points,
An object of the present invention is to provide a hysteresis comparator that generates hysteresis at different levels of an input signal and applies hysteresis stepwise to apply hysteresis before the comparison result is inverted to prevent abnormal output oscillation.

[0008]

According to a first aspect of the present invention, there is provided a comparing means for comparing an input signal with a reference voltage and outputting the comparison result, and a first reference voltage when the input signal rises. Before the comparison result is inverted, the reference voltage supplied to the comparison means is switched to a second reference voltage lower than the first reference voltage, and after the comparison result is inverted, the reference voltage is changed to the second reference voltage. Switching to a third reference voltage lower than the second reference voltage, and, when the input signal decreases to the third reference voltage, before the comparison result is inverted, the reference voltage is changed to the second voltage. And a reference voltage switching means for switching the reference voltage to a first reference voltage after the comparison result is inverted.

As described above, when the input signal rises, the reference voltage used for comparison is switched from the first reference voltage to the second reference voltage before the comparison result is inverted. By switching the reference voltage used for comparison from the third reference voltage to the second reference voltage before inversion, hysteresis can be applied before the input signal becomes the reference voltage and the comparison result is inverted, This can prevent occurrence of abnormal output vibration.

[0010]

FIG. 1 is a circuit diagram of an embodiment of the circuit of the present invention.
A road map is shown. In the figure, the same parts as those in FIG.
Attach. In FIG. 1, an input signal supplied from a terminal 10
VIN + is a PNP transistor Q₁Applied to the base of
And the transistor Q₁The voltage is shifted by PNP
Transistor Q_ThreeApplied to the base. Also, PNP type
Transistor Q_TwoReference voltage V_REFAs voltage
VIN- is applied and the transistor Q_TwoWith voltage shifted
PNP transistor Q_FourApplied to the base.
Transistor Q_Three, Q_FourIs a differential circuit as a means of comparison.
And an NPN transistor Q having a current mirror configuration.
_Five, Q₆Is the transistor Q of the above differential circuit._Three, Q _FourNoh
Forming a dynamic load. Transistor Q_Three, Q_FourEmi of
Are connected in common and connected to a constant current source 12.

The transistor Q_FourCollector is NPN type
Transistor Q₇Connected to the base. Transis
TA Q₇Is a grounded emitter and a collector is a constant current source 14.
And a resistor R_Four, R_Five, R₁₁At one end of each
It is connected. Resistance R_Four, R_Five, R₁₁The other end of each is N
PN type transistor Q₈, Q₁₁, Q₁₄Connect to each base
Has been continued. Transistor Q₈Grounded emitter
The collector is a constant current source 16 and an NPN transistor
Q₉Connected to the base. Transistor Q ₁₁Is d
The emitter is grounded and the collector is connected to the constant current source 18 and transformer.
Jista Q₁₂Connected to the base. Transistor Q
₁₄Has an emitter grounded and a collector connected to the constant current source 20 and
NPN transistor Q_FifteenConnected to the base.

[0012] NPN type transistor Q ₉ is grounded emitter and a collector connected to the base of an NPN transistor Q ₁₀ of the constant-current source 22 and the output. Transistor Q ₁₀ is grounded emitter and a collector connected to the output terminal 24 is connected to the power supply V _CC through a resistor R _6. Between the power supply V _CC and the ground are connected resistance R _1, R ₂ connected in series, the connection point of the resistors R _1, R ₂ are connected to the base of the transistor Q _2. Also,
NPN type transistor Q ₁₂ is grounded emitter, collector is connected through a resistor R ₃ to the connection point of the resistors R _1, R _2, an NPN transistor Q ₁₅ is grounded emitter, collector resistors R ₁₀ Is connected to the connection point of the resistors R ₁ and R ₂ .

The above resistor R_Four, R_Five, R₁₁Are almost identical
The resistance value, the current value I flowing through each of the constant current sources 16, 18, 20
₀, I₁, I_TwoIs I₁<I₀<I_TwoRelationship and the tiger
Transistor Q₈, Q₁₁, Q₁₄Have substantially the same characteristics.
Therefore, the transistor Q₇Collector voltage V₁To 0
When increasing from V, the transistor Q₈, Q₁₁, Q₁₄Is
It turns on at substantially the same timing,₁<I₀<I_TwoIn
Transistor Q ₁₁First saturated transistor
Q₁₂Base potential of transistor Q₁₂Turns off
You. Next, the transistor Q₈Saturates and the transistor Q₉
Base potential of transistor Q₉Turns off. This
After the transistor Q₁₄Saturates and the transistor Q_Fifteenof
Base potential drops, transistor Q_FifteenTurns off. this
Voltage V from state₁Down, the reverse of the above
Jista Q_FifteenTurns on, and then the transistor Q₉Turns on,
Finally, the transistor Q₁₂Turns on. Perform the above operation
The circuit is set as follows.

The operation of the entire circuit of FIG. 1 will be described.
Changes the input signal VIN + from low level to high level.
Transistor Q₇Is turned on for that collector
Voltage V ₁Becomes approximately 0V. This allows the transistor
Q₈, Q₁₁, Q₁₄Are turned off at substantially the same timing,
₁<I₀<I_TwoTherefore, first, as described above,
Star Q_FifteenTurns on, and then the transistor Q₉Turns on and
Later the transistor Q₁₂Turns on.

The above transistor Q₉, Q₁₂, Q_FifteenIs all
Power supply voltage V in the off state_CCIs the resistance R₁, R_TwoWith partial pressure
First reference voltage V_REF0Is the voltage VIN-
Jista Q_TwoApplied to the base of the
Jista Q_FifteenTurns on the resistor R_TwoAnd the resistor R in parallel_TenContact
As shown in FIG. 2, the reference voltage is the second reference voltage V
_REF1(V_REF1<V_REF0) To reduce hysteresis
You. As a result, the voltage V ₁Drops rapidly and the next
Jista Q₉As shown in FIG.
Transistor Q₉Collector voltage V_TwoIs high to low
And the output signal VOUT of the output terminal 24 is low.
-Level to high level. At this time,
Abnormal output vibration may occur due to the
And not. Finally, the transistor Q₁₂Is turned on
Resistance R_TwoAnd the resistor R in parallel_TenAnd R _ThreeIs connected to
As shown, the reference voltage is the third reference voltage V_REF2(V_REF2<
V_{RE F1}).

Next, when the input signal VIN + changes from the high level.
When it changes to low level, transistor Q₇Is off,
Voltage V₁Rises from approximately 0V. This allows Transis
TA Q ₈, Q₁₁, Q₁₄Turns on at almost the same timing,
I₁<I₀<I_TwoTherefore, first, as described above,
Jista Q₁₂Turns off, and then the transistor Q₉Turns off,
Finally, the transistor Q_FifteenTurns off.

The above transistor Q₉, Q₁₂, Q_FifteenIs all
The reference voltage V_REF2Is the voltage VIN-
Transistor Q_TwoIs applied to the base of the
Transistor Q₁₂Turns on the resistor R_ThreeConnection is cut off
Resistor R_TwoAnd the resistor R in parallel_TenOnly connected and shown in Figure 2
Thus, the reference voltage is the third reference voltage V_REF2From the second standard
Voltage V_REF1(V_REF2<V_REF1) Rise to hysteresis
It takes. As a result, the voltage V₁Rises rapidly and the next
Transistor Q₉Is turned off, as shown in FIG.
Transistor Q₉Collector voltage V_TwoIs low level
From the output terminal 24 to the high level.
T is inverted from high level to low level. At this time
Abnormal output vibration occurs because hysteresis has already been applied.
I won't be afraid. Finally, the transistor Q_FifteenCan be turned off
And the resistance R_TwoFrom resistance R_TenConnection is cut off and
As shown, the reference voltage is the first reference voltage V_REF0(V_REF1<
V _REF0) To rise.

The resistors R _{1 to} R ₁₁ and the transistor Q
₈ , Q ₉ , Q _{11 to} Q ₁₅ and constant current sources 16 to 20 constitute a reference voltage switching means. Thereby, the input signal V
When IN + rises from low level to high level, FIG.
When the input signal VIN + exceeds the reference voltage _VREF0 , the output signal VOUT is inverted to a high level, and when the input signal VIN + falls from a high level to a low level as shown in FIG.
+ Is less than the reference voltage V _REF2 and the output signal VOU
T is inverted to a low level to obtain a hysteresis characteristic. In addition, when the input signal VIN + rises or falls, the output signal is inverted after the reference voltage is switched and the hysteresis is applied. Therefore, an abnormal output is always generated when the input signal VIN + rises or falls. Vibration can be prevented.

By the way, the reference voltage V_REFFig. 1
Resistance R_TwoAnd the resistor R in parallel_Three, R_TenConnect each one
Is not limited to the configuration for shutting off, for example, the configuration shown in FIGS.
It is good. In FIG. 4, the power supply V_CCIn series between
Connected resistor R₁₂, R₁₃, R₁₄, R_FifteenConnect. G
Transistor Q₁₂The collector of the resistor R₁₃, R₁₄At the connection point
Connected, the emitter grounded, and the transistor Q_FifteenNo
The resistor R₁₄, R _FifteenTo the connection point of the
And the resistor R₁₂, R₁₃From the connection point of
Reference voltage V_REFWith transistor Q_TwoApplied to the base of
I do. In this case, the transistor Q₁₂, Q_FifteenAre both off
Transistor Q from state_FifteenBy turning on the reference
Voltage V_REFDecreases, and the transistor Q₁₂Turn on
The reference voltage V_REFIs lower.

In FIG. 5, resistors R ₁₆ , R ₁₇ and R ₁₈ connected in series are connected between the power supply V _CC and the ground. The collector of the transistor Q ₁₂ via the resistor R ₁₉ is connected to the connection point of the resistors R _16, R _17, and ground the emitter is connected to the collector of the transistor Q ₁₅ to the connection point of the resistors R _17, R _18, its emitter is grounded, applying a reference voltage V _REF taken out from the connection point of the resistors R _16, R ₁₇ to the base of the transistor Q _2. In this case, decrease the reference voltage V _REF by transistors Q _12, Q ₁₅ turns on the transistor Q ₁₅ from both off state, the reference voltage V _REF by further turning on the transistors Q ₁₂ and Q ₁₅ is reduced more I do.

In addition, instead of using the transistors Q _{8 to} Q ₁₀ and the constant current sources 16 and 22, the output signal is taken out,
An inverter 26 and NOR circuits 28 and 3 as shown in FIG.
The output signal VOUT may be extracted from the terminal 34 by configuring the RS flip-flop 32 with 0. In Figure 6, Noah when the voltage V ₁ of the collector of the transistor Q ₇ is when changing from the high level to the low level, the transistors Q ₁₅ and Q ₁₂ is the reference voltage and ON becomes V _REF2 shown in FIG. 2 The input of the circuit 30 becomes high level, the RS flip-flop 32 is set, and a high-level signal VOUT is output from the terminal 34. Conversely, the voltage V ₁
There when changing from a low level to a high level, V reference voltage transistors Q ₁₂ and Q ₁₅ is turned off and is shown in FIG. 2
_{When REF0} is reached, the input of the inverter 26 goes low, that is, the input of the NOR circuit 28 goes high, and RS
The flip-flop 32 is reset, and a low-level signal VOUT is output from the terminal 34.

Next, a modified example of the circuit of FIG. 1 will be described. When the gain of the entire circuit is high in the circuit of FIG. 1, the difference between each of the reference voltages V _REF0 , V _REF1 , and V _REF2 may be 1 mV or less, and the hysteresis may not be sufficiently fast. . In such a case, the circuit configuration is modified as shown in FIGS. 7, 8, and 9, respectively.

In the circuit shown in FIG. 7, the transistor Q ₇ and the constant current source 14 in FIG. 1 are eliminated to lower the gain of the circuit. In this case, since the inverted signal by the transistor Q ₇ is not, by connecting the collector of the transistor Q ₇ to signal to the collector of the transistor Q ₆ is inverted to the resistor R _4, R _5, R ₁₁ each on one end I have.

In the circuit shown in FIG. 8, transistors Q ₅ and Q
₆ instead of the current mirror arrangement and a current mirror circuit with transistors Q _6, Q _7. This is the same as the collector current of the transistor Q ₆ the collector current of the transistor Q _7, are lowered gain without performing amplification by transistor Q ₇ as shown in FIG.

[0025] In the circuit shown in FIG. 9 constitute a current mirror circuit with transistors Q _6, Q ₇ similarly to the circuit shown in FIG. 8, the NPN type transistor Q ₁₆ is further connected in common people transistor Q ₇ and the emitter and collector respectively provided, by connecting a resistor R ₁₆ between the base and the collector of the transistor Q ₁₆ is lower than the collector current of the transistor Q ₇ to the circuit of FIG. 8, which further lowers the gain.

[0026] Incidentally, FIG. 8, the transistor Q ₅ which is diode connected in FIG. 9 is present to balance the transistor Q _6, this transistor Q
₅ may be deleted. With the circuit configuration shown in FIGS. 7, 8, and 9, the difference between the reference voltages V _REF0 and V _REF1 and the difference between the reference voltages V _REF1 and V _REF2 are each several mV.
To several tens mV or more, and hysteresis can be applied sufficiently quickly.

FIG. 10 is a circuit diagram showing another embodiment of the circuit of the present invention. In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals.
In FIG. 10, an input signal VI supplied from a terminal 10 is shown.
N + is applied to the base of a PNP transistor Q _1,
Is the voltage shift in the transistor Q ₁ is applied to the base of a PNP transistor Q _3. The voltage VI as a reference voltage V _REF to the base of a PNP transistor Q ₂
N- is applied, it is applied to the voltage shift in the transistor Q ₂ to the base of a PNP transistor Q _4. The transistors Q ₃ and Q ₄ constitute a differential circuit as comparison means, and the NPN transistors Q ₅ ,
Q ₆ forms an active load of transistors Q _3, Q ₄ of the differential circuit. The emitters of the transistors Q ₃ and Q ₄ are commonly connected and connected to a constant current source 12. Between the collector and the emitter of the transistor Q ₅ resistor R ₃₀ is connected, thereby improving the symmetry of clogging balance of the differential circuit. This is to prevent the occurrence of an offset due to the deterioration of the balance due to the addition of resistors R ₃₁ and R ₃₂ , which will be described later. However, this is unnecessary if there is no concern about the deterioration of the balance. Or a combination of resistors may be added.

One end of each of the resistors R ₄ , R ₅ and R ₁₁ is connected to the collector of the transistor Q ₄ . Resistance R
_4, R _5, R ₁₁ and the other end of each is connected to the base of an NPN transistor Q _8, Q _11, Q ₁₄ respectively. Transistor Q ₈ is grounded emitter is connected to the collector to the base of the constant current source 16 and NPN type transistor Q _10, the base-emitter resistor R ₃₁ is connected. Transistor Q ₁₁ is grounded emitter, is connected to the collector to one end of a resistor R _33. Transistor Q ₁₄ is grounded emitter is connected to the collector to one end of the resistor R _34, the base-emitter resistor R ₃₂ is connected.

Transistor Q_TenIs grounded emitter,
Collector is resistor R₆Power through V _CCWhen connected to
Is connected to the output terminal 36. Power supply V_CCAnd earth
Are connected in series with a resistor R₁, R_TwoIs connected and
Anti-R₁, R_TwoConnection point of transistor Q_TwoContact the base of
Has been continued. The resistance R₃₃, R₃₄The other end of each is a resistor
R₁, R_TwoConnected to the connection point.

[0030] In this case, I think about the on-state characteristics of the transistor Q _8. The collector voltage of the transistor Q ₆ V ₁₀
When this voltage V ₁₀ is the resistance R _4, is divided by the R ₃₁ minutes is applied to the base of the transistor Q _8, the transistor Q ₈ is turned on when satisfying the following equation, the output terminal 24 becomes a low level .

[0031]

(Equation 1)

Where I_TenIs the transistor Q when it is on₈of
Collector current, I_sIs the transistor Q ₈Reverse saturation current
Flow, V_TIs the thermal voltage kT / q and the base current is
Let it be small. Therefore,

[0033]

(Equation 2)

[0034] The above-mentioned V _TH10 is a threshold voltage of the transistor Q _8. Voltage V ₁₀ is the resistance R ₁₁ also transistor Q _14, and is divided by the R ₃₂ minutes is applied to the base, even the base-emitter is open for the transistor Q ₁₁ (infinite resistance) is the voltage V ₁₀ and the resistor R ₅ because it is applied to the base through the infinite resistance, it is similar to that of the transistor Q _8.

For this reason, the transistors Q ₈ , Q ₁₁ , Q ₁₄
Each are the same characteristics, when I _s, V _T is the same,
By setting R ₄ = R ₅ = R ₁₁ , R ₃₂ > R ₃₁ and I ₁₁ ≦ I ₁₀ ≦ I ₁₂ , V _TH11 <V _TH10 <
The relationship of V _TH12 can be obtained. It should be noted that I ₁₁ and I ₁₂ are the collector currents when the transistors Q ₁₁ and Q ₁₄ are on,
V _TH11, V _TH12 is a transistor Q _11, Q ₁₄ each threshold voltage of the.

To explain the operation of FIG. 10, the main part is shown in FIG. However, it connects the resistor R ₃₅ between the base and emitter shown in FIG. 11 (A) in the transistor Q _19, the same as FIG. 10 when the resistance value of the resistor R ₃₅ and infinity. When the input signal VIN + is changed from high level to low level, the collector voltage V ₁₀ of the transistor Q ₆ is changed from the high level to the low level. Transistor Q _11, Q _8, Q ₁₄ is V _TH11 <V _TH10 <V _TH12
Because of the relationship, first, transistor Q ₁₁ is turned off,
For resistor R ₃₃ is shut off parallel connection of the resistor R ₂ and R _34, the reference voltage as shown in FIG. 11 (B) rises from a third reference voltage V _REF2 to the second reference voltage V _REF1 Hysteresis occurs. Then the voltage V ₂₀ of the collector of the transistor Q ₈ transistor Q ₈ is turned off is changed to the high level from the low level as shown in FIG. 11 (B). Moreover transistor Q ₁₄ is turned off, to the resistor R ₃₄ is shut off parallel connection of the resistor R _2, the reference voltage rises from the second reference voltage V _REF1 to the first reference voltage V _REF0.

[0037] Then the input signal VIN + is changes from the low level to the high level, the collector voltage V ₁₀ of the transistor Q ₆ is changed from low level to high level. Since transistors Q _11, Q _8, Q ₁₄ are in a relation of _{V TH11 <V TH10 <V TH12} , first, the transistor Q ₁₄ is turned on, resistor R ₃₄ is connected in parallel with the resistor R _2, FIG. 11
As shown in (B), the reference voltage _decreases from the first reference voltage V _REF0 to the second reference voltage V _REF1 , and hysteresis is applied. Then the voltage V ₂₀ transistor Q ₈ is turned on Figure 11
The level changes from the high level to the low level as shown in FIG. Furthermore the transistor Q ₁₁ is turned on, resistor R ₃₃ is the resistance R
₂ and R ₃₄ , the reference voltage drops from the second reference voltage V _REF1 to the third reference voltage V _REF2 .

[0038] Thus, the input signal VIN + goes low voltage V ₂₀ is inverted when the voltage V ₁₀ exceeds the threshold voltage V _TH11 when standing rise from a low level to a high level, the input signal VIN + is high hysteresis characteristics can be obtained at a high level and the inverted voltage V ₂₀ when the voltage V ₁₀ becomes smaller than the threshold voltage V _TH12 when the low-level falls. Also, when the input signal VIN + rises or falls, the output signal is inverted after the reference voltage is first switched and hysteresis is applied, so that the input signal VI
Abnormal output vibration can be always prevented when N + rises or falls.

In FIG. 11A, the resistance R₃₅To
As mentioned above, you can delete it.
Resistance R₃₁, R₃₂, R₃₅Each can be replaced with a constant current source
No. FIG. 12 shows a modification of the circuit of FIG. FIG.
The transistor Q₁, Q_TwoRemove the differential circuit
Input is PNP transistor Q_Three, Q_FourEach as one stage
I have. This is, of course, a two-stage PNP type as in FIG.
Transistor Q₁~ Q_FourMay be configured, and for example,
Other types using NPN transistors may be used. Ma
The transistor Q_FiveNPN Transistor
TA Q₁₇And the transistor Q₁₇Emitter of
And the collector is connected to the constant current source 37.
Transistor Q_FiveThe collector output of transistor Q
₁₇Is inverted and amplified. This transistor Q₁₇Collection of
Voltage V_TenAs resistance R _Four, R_Five, R₁₁Applied to
It is.

FIGS. 13 and 14 are circuit diagrams of an embodiment using MOS transistors of the circuit of the present invention. 13, an input signal is supplied from the terminal 40 VIN + is applied to the gate of the P-channel MOS transistor Q _21. The voltage VIN- is applied as the reference voltage V _REF to the gate of the P-channel MOS transistor Q _22. The transistors Q ₂₁ and Q ₂₂ constitute a differential circuit, and the N-channel MOS transistors Q ₂₃ and Q ₂₄ having a current mirror configuration are current sources for the transistors Q ₂₁ and Q ₂₂ of the differential circuit. The sources of the transistors Q ₂₁ and Q ₂₂ are commonly connected and connected to the constant current source 42. The drain of the transistor Q ₂₂ is connected to the gate of N-channel MOS transistor Q _25. The transistor Q ₂₅ has a drain connected to the constant current source 44.
And the input terminals of the inverters 46, 48 and 50, and the source is grounded.

The threshold value V of each of the inverters 46, 48 and 50
TH0, VTH1, and VTH2 are VTH1 <VTH0 <V
TH2 is set. An output terminal of the inverter 46 is connected to the terminal 52, the output terminal of the inverter 48 is connected to the gate of N-channel MOS transistor Q _26, the output terminal of the inverter 50 is connected to the gate of the P-channel MOS transistor Q _27. The source of the transistor Q ₂₆ is grounded, and the drain transistor Q ₂₇
It is connected to the drain and one end of resistor R _22. The source of the transistor Q ₂₇ is connected to the power supply V _CC. Resistor R ₂₀ connected in series between the power supply V _CC and ground, R
₂₁ is connected, and the connection point of R ₂₀ and R ₂₁ is connected to the other end of the resistor R ₂₂ and to the gate of the transistor Q ₂₂ .

[0042] Here, if the input signal VIN + voltage V ₁ of the drain of the transistor Q ₂₅ changes from the low level to the high level drops from the high level to the low level, first the output of the inverter 50 is inverted from the low level to the high level I do. Thus the transistor Q ₂₇ is turned off from on, the reference voltage V _REF resistor R ₂₃ which is connected to the resistor R ₂₀ in parallel is blocked hysteresis according to decreases.
Next, the output VOUT of the inverter 46 is inverted from the low level to the high level. At this time, since the hysteresis has already been applied, abnormal output vibration does not occur. Finally reference voltage V _REF transistor Q ₂₆ output of the inverter 48 is inverted from the low level to the high level is turned on from off is further reduced.

Next, the input signal VIN + changes from high level to low level.
-Level changes to transistor Q _{twenty five}Drain voltage
V₁Rises from low level to high level,
The output of the inverter 48 is inverted from high level to low level
I do. Thereby, the transistor Q₂₆From on to off
The reference voltage V_REFRises with hysteresis.
Next, the output VOUT of the inverter 46 changes from high level to low level.
-Level. At this time, the hysteresis has already
Therefore, no abnormal output vibration occurs. last
The output of the inverter 50 changes from high level to low level
Invert transistor Q₂₇The reference voltage
V_REFRises further.

In FIG. 14, an input signal VIN + supplied from a terminal 40 is a P-channel MOS transistor Q _21.
Is applied to the gates. The voltage VI as a reference voltage V _REF to the gate of the P-channel MOS transistor Q ₂₂
N- is applied. Transistors Q _21, Q ₂₂ constitute a differential circuit, N-channel MOS transistors Q _23, Q ₂₄ of the current mirror arrangement forms an active load of transistors Q _21, Q ₂₂ of the differential circuit. Transistor Q
The sources of ₂₁ and Q ₂₂ are commonly connected and connected to a constant current source 42. The drain of the transistor Q ₂₂ is connected to the gate of the P-channel MOS transistor Q _25. Transistor Q ₂₅ is connected to drain to an input terminal of the constant current source 44 and the inverter 54 is grounded source.

The output terminal of the inverter 54 is an N-channel M
OS transistor Q₂₆Gate and P-channel MOS transistor
Transistor Q₂₇Connected to the gate. Transis
TA Q ₂₆Source is grounded and drain is connected in series
Resistance R_{twenty four}, R_{twenty three}Through the transistor Q₂₇On the drain of
It is connected. Transistor Q₂₇Source is power supply V _CC
It is connected to the. Power supply V_CCIs connected in series between
Continued resistance R₂₀, R _{twenty one}Are connected, and R₂₀, R_{twenty one}Connection
The point is the resistance R_{twenty three}, R_{twenty four}Connected to
Jista Q_{twenty two}Connected to the gate. Further inverter
An output terminal 54 is an output terminal via inverters 56 and 58.
Child 60.

Incidentally, the threshold value VTH0 of the inverter 56
Is an N-channel MOS transistor Q ₂₆Threshold VTHN,
P channel MOS transistor Q₂₇Of the threshold VTHP
Then the following relationship is set. VTHN <VTH0 <Vcc-VTHP Normally, when the inverter 56 is formed of a CMOS circuit,
The above relationship is obtained.

[0047] Now the input signal VIN + voltage V ₁ of the drain of the transistor Q ₂₅ changes from the low level to the high level rises from the high level to the low level, first the output of the inverter 54 is inverted from the low level to the high level I do. Thus the transistor Q ₂₆ is turned on from off, the resistor R ₂₄ is connected in parallel with the resistor R ₂₁ reference voltage V
_REF decreases and hysteresis is applied. Next, the output of the inverter 56 is inverted from the high level to the low level, and the output VOUT of the inverter 58 is inverted from the low level to the high level. At this time, since the hysteresis has already been applied, abnormal output vibration does not occur. Finally, the transistor Q ₂₇ is turned off from on, and the reference voltage V _REF is further reduced.

Next, the input signal VIN + changes from high level to low level.
-Level changes to transistor Q _{twenty five}Source voltage V
₁Rises from low level to high level,
The output of the inverter 54 is inverted from high level to low level.
You. Thereby, the transistor Q₂₇From off to on
The reference voltage V_REFRises with hysteresis.
Next, the output of the inverter 56 is changed from the low level to the high level.
And the output VOUT of the inverter 58 is at a high level.
From low to low level. At this time the hysteresis has already
Abnormal output vibration does not occur.
No. Finally, the transistor Q₂₆From off to on
Pressure V_REFRises further.

[0049]

As described above, the first aspect of the present invention provides
Comparing means for comparing the input signal with a reference voltage and outputting the comparison result; and supplying the comparison result to the comparison means before the comparison result is inverted when the input signal rises to the first reference voltage. A second reference voltage lower than the first reference voltage;
After the comparison result is inverted, the reference voltage is switched to a third reference voltage lower than the second reference voltage, and the input signal is reduced to become the third reference voltage. And a reference voltage switching means for switching the reference voltage to the second voltage before the comparison result is inverted, and for switching the reference voltage to the first reference voltage after the comparison result is inverted.

As described above, when the input signal increases, the reference voltage used for comparison is switched from the first reference voltage to the second reference voltage before the comparison result is inverted, and when the input signal decreases, the comparison result changes. By switching the reference voltage used for comparison from the third reference voltage to the second reference voltage before inversion, hysteresis can be applied before the input signal becomes the reference voltage and the comparison result is inverted, This can prevent occurrence of abnormal output vibration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of the present invention.

FIG. 2 is a characteristic diagram of the present invention.

FIG. 3 is a characteristic diagram of the present invention.

FIG. 4 is a circuit diagram of a partially modified example of the circuit of FIG. 1;

FIG. 5 is a circuit diagram of a partially modified example of the circuit of FIG. 1;

FIG. 6 is a circuit diagram of a partially modified example of the circuit of FIG. 1;

FIG. 7 is a circuit diagram of the present invention.

FIG. 8 is a circuit diagram of the present invention.

FIG. 9 is a circuit diagram of the present invention.

FIG. 10 is a circuit diagram of the present invention.

FIG. 11 is a circuit diagram and a characteristic diagram of a main part of the present invention.

FIG. 12 is a circuit diagram of the present invention.

FIG. 13 is a circuit diagram of the present invention.

FIG. 14 is a circuit diagram of the present invention.

FIG. 15 is a circuit diagram of a conventional circuit.

FIG. 16 is a characteristic diagram of the circuit of FIG.

[Explanation of symbols]

Q _{1 to} Q ₁₆ transistors Q _{21 to} Q ₂₇ MOS transistors R _{1 to} R ₂₄ Resistances 12 to 22, 42, 44 Constant current sources 46, 48, 50, 54 Inverters

Claims (1)

[Claims] 1. A comparing means for comparing an input signal with a reference voltage and outputting the comparison result, wherein the input signal rises to a first reference voltage before the comparison result is inverted before the comparison result is inverted. The reference voltage supplied to the comparing means is switched to a second reference voltage lower than the first reference voltage, and after the comparison result is inverted, the reference voltage is changed to a third reference voltage lower than the second reference voltage. Switching, and when the input signal decreases to the third reference voltage, the reference voltage is changed to the second reference voltage before the comparison result is inverted.
And a reference voltage switching means for switching the reference voltage to a first reference voltage after the comparison result is inverted.