JP2001298272A - Printed board - Google Patents

Printed board

Info

Publication number
JP2001298272A
JP2001298272A JP2000111637A JP2000111637A JP2001298272A JP 2001298272 A JP2001298272 A JP 2001298272A JP 2000111637 A JP2000111637 A JP 2000111637A JP 2000111637 A JP2000111637 A JP 2000111637A JP 2001298272 A JP2001298272 A JP 2001298272A
Authority
JP
Japan
Prior art keywords
circuit board
printed circuit
layer
stress relaxation
flip chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000111637A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamada
浩史 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2000111637A priority Critical patent/JP2001298272A/en
Publication of JP2001298272A publication Critical patent/JP2001298272A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve a problem of a conventional printed board where the exchange of electronic parts is remarkably difficult and that it takes much facility cost for reinforcing resin in a device where a gap between a printed board and a flip chip is filled with reinforcing resin for reducing stress to a solder bump by the thermal expansion coefficient difference of the printed board and the flip chip. SOLUTION: In the printed board, parts connection electrodes 6 connected with electronic parts by solder bumps are formed on a build-up layer 2 where an inner layer conductor pattern 3 is formed. The printed board is provided with a stress relief layer 4 for relieving stress which is formed on the build-up layer 2, and fine conductor poles 5 which are pulled out from the inner layer conductor pattern 3 through the stress relief layer 4 and are connected to the parts connection electrodes 6. When a temperature rises in a state where the electronic parts of the flip chip and the like are connected to the parts connection electrodes 6 by the solder bumps, the fine conductor poles 5 are deformed with the stress relief layer 4, and the expansion difference of the printed board and the electronic parts by the difference of the thermal expansion coefficients of the printed board and the electronic parts is absorbed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はプリント基板に係
り、特にフリップチップ等の微細電子部品を実装するプ
リント基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board, and more particularly to a printed circuit board on which fine electronic components such as flip chips are mounted.

【0002】[0002]

【従来の技術】近年、大規模半導体集積回路(LSI)
のパッドの微細化は急速に進んでおり、より高密度なフ
リップチップ実装が普及してきている。しかし、半導体
チップをパッケージに含まずに直接基板に搭載するフリ
ップチップ実装を行うにあたり、ダイレクトにプリント
基板のパッドとフリップチップをはんだバンプで接続す
るため、プリント基板とフリップチップの熱膨張係数差
により発生する歪みによる応力がはんだバンプに直接か
かるが、はんだバンプ間が微細化し、接続するはんだ量
が少なくなってきているため、上記の応力に耐え得るこ
とができず、接続寿命の低下を防ぐことが困難となって
きている。
2. Description of the Related Art In recent years, large-scale semiconductor integrated circuits (LSIs)
The miniaturization of pads has rapidly progressed, and higher-density flip-chip mounting has become widespread. However, when performing flip-chip mounting, in which the semiconductor chip is not directly included in the package but directly on the board, the pads on the printed board and the flip-chip are directly connected by solder bumps. Although the stress due to the generated strain is directly applied to the solder bumps, the distance between the solder bumps has become smaller and the amount of solder to be connected has been reduced, so that the above stress cannot be withstood and the life of the connection is not reduced. Is becoming more difficult.

【0003】例えば、図5(a)に示すように、コア層
1上に内層導体パターン3が形成されているビルドアッ
プ層2が設けられたプリント基板の部品接続電極6に、
はんだバンプ6でフリップチップ10を接続した状態で
温度上昇が発生すると、プリント基板の熱膨張係数(約
16〜20ppm/℃)が、フリップチップ10の熱膨
張係数(約3.5ppm/℃)に比べて大きいため、プ
リント基板はフリップチップ10より膨張する。
For example, as shown in FIG. 5A, a component connection electrode 6 of a printed circuit board provided with a build-up layer 2 in which an inner conductor pattern 3 is formed on a core layer 1 is provided.
When the temperature rise occurs while the flip chip 10 is connected with the solder bumps 6, the thermal expansion coefficient of the printed circuit board (about 16 to 20 ppm / ° C.) is reduced to the thermal expansion coefficient of the flip chip 10 (about 3.5 ppm / ° C.). Since the printed circuit board is larger than the flip chip 10, the printed circuit board expands.

【0004】そのときの膨張差は、プリント基板の熱膨
張係数を18ppm/℃、フリップチップ10の熱膨張
係数を3.5ppm/℃、発熱冷却時の温度上昇差を6
0℃とした場合、10mm□の範囲で10μm程度とな
る。この熱膨張係数差がプリント基板とフリップチップ
10を接続しているはんだバンプ9に図5(b)に示す
ように歪みを与え、応力が発生し、発熱冷却が繰り返さ
れることにより、はんだバンプ9の破壊を誘発する。
The expansion difference at that time is as follows: the thermal expansion coefficient of the printed circuit board is 18 ppm / ° C .; the thermal expansion coefficient of the flip chip 10 is 3.5 ppm / ° C .;
When the temperature is set to 0 ° C., the thickness is about 10 μm in a range of 10 mm □. This difference in thermal expansion coefficient causes the solder bump 9 connecting the printed circuit board and the flip chip 10 to be distorted as shown in FIG. 5 (b), stress is generated, and heat generation and cooling are repeated. Trigger the destruction of.

【0005】そこで、従来は、この熱膨張係数差による
はんだバンプへの応力を軽減するため、プリント基板と
フリップチップの間隙に補強樹脂を充填し、はんだバン
プ及びプリント基板とフリップチップの間隙を樹脂で固
め補強している。この補強樹脂の充填によりはんだ付け
部への応力が軽減され、接続寿命は上昇する。
Therefore, conventionally, in order to reduce the stress on the solder bump due to the difference in the thermal expansion coefficient, the gap between the printed board and the flip chip is filled with a reinforcing resin, and the gap between the solder bump and the printed board and the flip chip is filled with the resin. It is hardened and reinforced. The filling of the reinforcing resin reduces the stress on the soldered portion and increases the connection life.

【0006】[0006]

【発明が解決しようとする課題】しかるに、上記の従来
のプリント基板では、補強樹脂充填後における機能検査
等においてフリップチップの不具合が検出され、フリッ
プチップ及び補強樹脂を取り外し、フリップチップを交
換することになった場合、密着しているフリップチップ
を樹脂から取り外すこと、プリント基板側に残った樹脂
をきれいに除去し、再度フリップチップが搭載される状
況まで再生することは著しく困難である。また、補強樹
脂充填のために樹脂の購入及び充填設備や樹脂硬化設備
の購入等が必要であるため、費用的にも増大するという
問題がある。
However, in the above-mentioned conventional printed circuit board, a defect of the flip chip is detected in a function test or the like after filling the reinforcing resin, and the flip chip and the reinforcing resin are removed and the flip chip is replaced. In this case, it is extremely difficult to remove the adhered flip chip from the resin, clean the resin remaining on the printed circuit board side, and reproduce the flip chip again. In addition, since it is necessary to purchase a resin and purchase a filling facility and a resin curing facility for filling the reinforcing resin, there is a problem that the cost increases.

【0007】本発明は以上の点に鑑みなされたもので、
応力緩和層及び微細導体柱が熱膨張係数の差により発生
する膨張差を吸収し、はんだバンプに発生する応力を緩
和するため、補強樹脂を充填せずともプリント基板とフ
リップチップの接続寿命の低下を防ぐことができるプリ
ント基板を提供することを目的とする。
[0007] The present invention has been made in view of the above points,
The stress relief layer and the fine conductor pillar absorb the expansion difference caused by the difference in thermal expansion coefficient, and reduce the stress generated in the solder bumps, so the connection life of the printed circuit board and flip chip is reduced without filling with reinforcing resin It is an object of the present invention to provide a printed circuit board capable of preventing the occurrence of a printed circuit board.

【0008】また、本発明の他の目的は、補強樹脂充填
時の弊害であった部品交換もプリント基板の再生を容易
にし、さらに費用的な面では、補強樹脂充填のための樹
脂及び設備の購入を不要とし得る応力緩和構造を持つプ
リント基板を提供することにある。
Another object of the present invention is to facilitate the regeneration of a printed circuit board even when replacing parts, which was an adverse effect at the time of filling the reinforcing resin. Further, in terms of cost, the resin and equipment for filling the reinforcing resin are required. An object of the present invention is to provide a printed circuit board having a stress relaxation structure that can make purchase unnecessary.

【0009】[0009]

【課題を解決するための手段】本発明は上記の目的を達
成するため、内層導体パターンが形成されているビルド
アップ層上に、電子部品とはんだバンプで接続される部
品接続電極が形成されているプリント基板において、ビ
ルドアップ層上に形成された応力緩和のための応力緩和
層と、ビルドアップ層に形成された内層導体パターンよ
り応力緩和層を貫通して引き出されて部品接続電極と接
続する微細導体柱とを有する構成としたものである。
According to the present invention, in order to achieve the above object, a component connection electrode connected to an electronic component by a solder bump is formed on a build-up layer on which an inner conductor pattern is formed. In a printed circuit board, a stress relaxation layer formed on the build-up layer for stress relaxation and an inner conductor pattern formed on the build-up layer are drawn through the stress relaxation layer and connected to the component connection electrodes. This is a configuration having fine conductor columns.

【0010】この発明では、フリップチップ等の電子部
品を部品接続電極にはんだバンプで接続した状態で、温
度上昇があったときには、微細導体柱が応力緩和層と共
に変形してプリント基板と電子部品の熱膨張係数の差に
よるプリント基板と電子部品の膨張差を吸収することが
できる。
According to the present invention, when an electronic component such as a flip chip is connected to a component connecting electrode by a solder bump, when the temperature rises, the fine conductor pillars are deformed together with the stress relieving layer, and the printed circuit board and the electronic component are connected. The difference in expansion between the printed circuit board and the electronic component due to the difference in thermal expansion coefficient can be absorbed.

【0011】ここで、上記の応力緩和層は、共晶はんだ
のヤング率より小さく、電子部品の部品接続電極へのは
んだ付け時での耐熱性を有し、耐溶剤性で、絶縁性のあ
る耐熱低弾性絶縁物により構成されていることを特徴と
する。
Here, the stress relaxation layer is smaller than the Young's modulus of the eutectic solder, has heat resistance at the time of soldering the electronic component to the component connection electrode, has solvent resistance, and has insulating properties. It is characterized by being constituted by a heat-resistant low-elastic insulator.

【0012】また、上記の応力緩和層は、熱膨張係数の
差により発生するプリント基板と電子部品の膨張差に対
して追従する、所定の膜厚で形成されていることを特徴
とする。
Further, the stress relaxation layer is formed to have a predetermined film thickness that follows a difference in expansion between the printed circuit board and the electronic component caused by a difference in thermal expansion coefficient.

【0013】また、本発明における上記の微細導体柱
は、長さが応力緩和層の膜厚よりも5〜10%長く形成
されていることが、プリント基板と電子部品の熱膨張係
数差により発生するはんだバンプへの応力の緩和時に、
微細導体柱の断線を防止できるので好ましい。また、本
発明における上記の微細導体柱は、応力緩和層の中で湾
曲又はコイル状に形成されていることが、微細導体柱の
断線防止にとって好ましい。
In the present invention, the fine conductor pillar is formed to have a length 5 to 10% longer than the thickness of the stress relaxation layer due to a difference in thermal expansion coefficient between the printed circuit board and the electronic component. When relaxing the stress on the solder bump
It is preferable because disconnection of the fine conductive column can be prevented. In addition, it is preferable that the above-mentioned fine conductor pillar in the present invention is formed in a curved or coiled shape in the stress relaxation layer in order to prevent disconnection of the fine conductor pillar.

【0014】[0014]

【発明の実施の形態】次に、本発明の実施の形態につい
て図面と共に説明する。図1は本発明になるプリント基
板の一実施の形態の断面図を示す。同図に示すように、
プリント基板は、コア層1、ビルドアップ層2、内層導
体パターン3、応力緩和層4、微細導体柱5及び部品接
続電極6からなる。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a printed circuit board according to an embodiment of the present invention. As shown in the figure,
The printed board includes a core layer 1, a build-up layer 2, an inner conductor pattern 3, a stress relaxation layer 4, fine conductor pillars 5, and component connection electrodes 6.

【0015】コア層1は、ビルドアップ基板の耐熱性ガ
ラスエポキシ基板等で形成された内層導体パターンを含
む。このコア層1は、電子部品実装時におけるプリント
基板の反り量を軽減するため、層厚が1.4mm以上あ
ることが望ましい。ビルドアップ層2は、フォトリソグ
ラフィ技術を用いて、順次構築するビルドアップ工法に
より形成される層である。このビルドアップ層2は、絶
縁材であるエポキシ系樹脂等を材料としており、樹脂塗
布と内層導体パターン3を繰り返して形成する。
The core layer 1 includes an inner conductor pattern formed of a heat-resistant glass epoxy substrate as a build-up substrate. The core layer 1 preferably has a thickness of 1.4 mm or more in order to reduce the amount of warpage of the printed circuit board when mounting electronic components. The build-up layer 2 is a layer formed by a build-up method of sequentially building using a photolithography technique. The build-up layer 2 is made of an epoxy resin or the like, which is an insulating material, and is formed by repeatedly applying the resin and the inner conductor pattern 3.

【0016】内層導体パターン3は、ビルドアップ層2
に形成されており、サブストラクティブやアディティブ
法等により形成され、通常は銅が材料となっている。応
力緩和層4は、シリコーンゴム等の耐熱低弾性絶縁物を
材料とし、弾性率がはんだバンプに応力を加えることな
く変形するために、共晶はんだのヤング率(3.06×
1010Pa)より小さいこと、電子部品はんだ付け時の
リフロー加熱における変質を防ぐため、250℃以上の
耐熱性をもつこと、耐溶剤性であると、絶縁性(1012
Ω・m以上)であること、などが条件である。応力緩和
層4の層厚については、層厚が薄いと応力緩和のための
微細導体柱5も短くなり、プリント基板と電子部品の熱
膨張差への追従性が劣ることから、100μm厚以上が
好ましい。
The inner conductor pattern 3 is composed of the build-up layer 2
And is formed by a subtractive or additive method or the like, and is usually made of copper. The stress relaxation layer 4 is made of a heat-resistant and low-elastic insulator such as silicone rubber, and has a Young's modulus of eutectic solder (3.06 ×
10 10 Pa), having a heat resistance of 250 ° C. or more to prevent deterioration due to reflow heating during soldering of electronic components, and an insulating property (10 12
Ω · m or more). As for the layer thickness of the stress relaxation layer 4, if the layer thickness is small, the fine conductor pillars 5 for stress relaxation also become short, and the ability to follow the difference in thermal expansion between the printed circuit board and the electronic component is inferior. preferable.

【0017】微細導体柱5は、ビルドアップ層2に形成
された内層導体パターン3より引き出された応力緩和の
ための導体柱で、例えば、銅を材料とし、柔軟性を求め
るため直径は30μmφ以下、高さは100μm以上と
することが望ましい。また、微細導体柱5の長さは、プ
リント基板と電子部品の熱膨張係数差により発生する応
力の緩和時に斜め方向に延ばされることから、断線を防
止するために応力緩和層4の層厚より5〜10%長いこ
とが好ましく、更に応力緩和層4内で湾曲していたりコ
イル状になっていることが好ましい。
The fine conductor pillar 5 is a conductor pillar for relaxing stress drawn from the inner conductor pattern 3 formed on the build-up layer 2, and is made of copper, for example, and has a diameter of 30 μmφ or less for obtaining flexibility. The height is desirably 100 μm or more. In addition, the length of the fine conductor pillar 5 is extended in an oblique direction when the stress generated due to the difference in thermal expansion coefficient between the printed circuit board and the electronic component is relaxed. It is preferably 5 to 10% longer, and more preferably, it is curved or coiled in the stress relaxation layer 4.

【0018】部品接続電極6は、フリップチップ等の電
子部品を接続するための電極で、導体柱5上に銅を材料
にして形成され、酸化防止のためにニッケル及び薄金メ
ッキ処理を施す場合もある。
The component connection electrode 6 is an electrode for connecting an electronic component such as a flip chip or the like. The component connection electrode 6 is formed of copper as a material on the conductor pillar 5 and may be plated with nickel and thin gold to prevent oxidation. is there.

【0019】次に、本発明のプリント基板の組み立て
(製造)方法について図2(a)〜(g)の断面図と共
に説明する。同図中、図1と同一構成部分には同一符号
を付してある。まず、図2(a)に示すように、内層導
体パターンを含む耐熱性ガラスエポキシ基板等を材料と
するコア層1に、エポキシ等を材料とするビルドアップ
層2をビルドアップ工法で形成した後、サブトラクティ
ブやアディティブ法で内層導体パターン3をビルドアッ
プ層2に形成する。
Next, the method of assembling (manufacturing) the printed circuit board of the present invention will be described with reference to the sectional views of FIGS. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. First, as shown in FIG. 2A, a build-up layer 2 made of epoxy or the like is formed on a core layer 1 made of a heat-resistant glass epoxy substrate or the like including an inner layer conductor pattern by a build-up method. Then, the inner conductor pattern 3 is formed on the build-up layer 2 by a subtractive or additive method.

【0020】続いて、図2(b)に示すように、シリコ
ーンゴム等の耐熱低弾性絶縁物を材料とする応力緩和層
4を内層導体パターン3が形成されているビルドアップ
層2上に形成する。すなわち、液状樹脂のコーティング
やドライフィルム上に半硬化させた樹脂を圧着する方法
等によりビルドアップ層2上に耐熱低弾性絶縁物を形成
した後、それを加熱や紫外線、赤外線等により硬化させ
て応力緩和層4を形成する。
Subsequently, as shown in FIG. 2B, a stress relaxation layer 4 made of a heat-resistant and low-elastic insulator such as silicone rubber is formed on the build-up layer 2 on which the inner conductor pattern 3 is formed. I do. That is, after forming a heat-resistant and low-elastic insulator on the build-up layer 2 by a method of applying a liquid resin coating or a semi-cured resin on a dry film by pressure bonding, it is cured by heating, ultraviolet rays, infrared rays, or the like. The stress relaxation layer 4 is formed.

【0021】次に、図2(c)に示すように、応力緩和
層4上に、微細導体柱5を形成する部分に同径程度の開
口又は色抜きされているフォトマスク7を被せた後、同
図(d)に示すように、レーザ、エッチング法等により
微細導体柱5と接続する内層導体パターン3まで微細導
体柱生成ホール8を貫通させる。その後、図2(e)に
示すように、フォトマスク7を取り外して微細導体柱生
成ホール8を形成する。
Next, as shown in FIG. 2 (c), an opening having the same diameter or a photomask 7 which has been colored is placed on the stress relaxing layer 4 at a portion where the fine conductor pillar 5 is to be formed. Then, as shown in FIG. 3D, the fine conductor pillar generation hole 8 is penetrated to the inner conductor pattern 3 connected to the fine conductor pillar 5 by a laser, an etching method or the like. Thereafter, as shown in FIG. 2E, the photomask 7 is removed to form the fine conductor pillar generation holes 8.

【0022】続いて、図2(f)に示すように、応力緩
和層4に形成された微細導体柱生成ホール8内にアディ
ティブ法等により微細導体柱5を形成する。その後、図
2(g)に示すように、微細導体柱5にフリップチップ
等の電子部品を接続するための部品接続電極6をサブト
ラクティブやアディティブ法等により形成する。部品接
続電極6の酸化を防止するために、部品接続電極6上に
ニッケル及び薄金メッキを施す場合もある。このように
して、図1の断面図に示す応力緩和構造を有するプリン
ト基板が作成される。
Subsequently, as shown in FIG. 2 (f), the fine conductor columns 5 are formed in the fine conductor column generation holes 8 formed in the stress relaxation layer 4 by an additive method or the like. Thereafter, as shown in FIG. 2G, a component connection electrode 6 for connecting an electronic component such as a flip chip to the fine conductor pillar 5 is formed by a subtractive or additive method. In order to prevent oxidation of the component connection electrode 6, the component connection electrode 6 may be plated with nickel and thin gold. In this way, a printed board having the stress relaxation structure shown in the cross-sectional view of FIG. 1 is produced.

【0023】次に、本実施の形態のプリント基板にフリ
ップチップを実装した場合の動作について説明する。図
3は図1に示した本実施の形態のプリント基板に、フリ
ップチップを実装した場合の一例の断面図を示す。同図
中、図1及び図2と同一構成部分には同一符号を付して
ある。図3において、部品接続電極6とフリップチップ
10とが、はんだバンプ9で接続されている。
Next, the operation when a flip chip is mounted on the printed circuit board of the present embodiment will be described. FIG. 3 is a cross-sectional view showing an example of a case where a flip chip is mounted on the printed circuit board of the present embodiment shown in FIG. In the figure, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals. In FIG. 3, the component connection electrode 6 and the flip chip 10 are connected by solder bumps 9.

【0024】接続しているはんだバンプ9は、フリップ
チップ10側と部品接続電極6側が共に共晶はんだの場
合、フリップチップ10側が鉛含有量の高い高融点はん
だで、部品接続電極6側が共晶はんだの場合、フリップ
チップ10側と部品接続電極6側が共に金の場合など、
様々な種類がある。
When the solder bumps 9 connected to the flip chip 10 and the component connection electrode 6 are both eutectic solder, the flip chip 10 side is a high melting point solder having a high lead content and the component connection electrode 6 side is eutectic. In the case of solder, when the flip chip 10 side and the component connection electrode 6 side are both gold,
There are various types.

【0025】本実施の形態のプリント基板によれば、図
3に示すように、フリップチップ10とはんだバンプ9
で接続されている状態で温度上昇が発生した場合、図4
(a)に示すように、プリント基板の熱膨張係数(約1
6〜20ppm/℃)が、フリップチップ10の熱膨張
係数(約3.5ppm/℃)に比べて大きいため、プリ
ント基板はフリップチップ10より膨張する。
According to the printed circuit board of this embodiment, as shown in FIG.
FIG. 4 shows a case where a temperature rise occurs while
As shown in (a), the thermal expansion coefficient of the printed circuit board (about 1
6 to 20 ppm / ° C.) is larger than the thermal expansion coefficient of the flip chip 10 (about 3.5 ppm / ° C.), so that the printed circuit board expands from the flip chip 10.

【0026】しかし、この実施の形態では、低弾性であ
る応力緩和層4内にある微細導体柱5がプリント基板と
フリップチップ10の膨張差に対応して、図4(b)に
示すように応力緩和層4と共に変形し、膨張差を吸収す
るため、はんだバンプ9が歪むことはなく、応力が加わ
ることがない。従って、本実施の形態では、フリップチ
ップ10を実装した場合に、製品動作時の発熱冷却の繰
り返しにおいて発生するはんだバンプ9の破壊が誘発さ
れることはなく、接続寿命を向上できる。
However, in this embodiment, as shown in FIG. 4B, the fine conductive pillars 5 in the low-elasticity stress relaxation layer 4 correspond to the expansion difference between the printed board and the flip chip 10, as shown in FIG. Since the solder bump 9 is deformed together with the stress relaxation layer 4 and absorbs the difference in expansion, the solder bump 9 is not distorted and no stress is applied. Therefore, in the present embodiment, when the flip chip 10 is mounted, destruction of the solder bumps 9 caused by repeated heat generation and cooling during product operation is not induced, and the connection life can be improved.

【0027】また、本実施の形態では、プリント基板と
フリップチップの間隙に補強樹脂を充填し、はんだバン
プ及びプリント基板とフリップチップの間隙を樹脂で固
め補強する従来のプリント基板のような、補強樹脂を使
用していないため、機能検査等においてフリップチップ
の不具合が検出された場合、フリップチップを容易に交
換することができ、また、補強樹脂充填のために樹脂の
購入及び充填設備や樹脂硬化設備の購入等を不要にでき
る。
In this embodiment, the gap between the printed board and the flip chip is filled with a reinforcing resin, and the solder bump and the gap between the printed board and the flip chip are solidified with the resin and reinforced, as in a conventional printed board. Since no resin is used, if a failure of the flip chip is detected in a function test, etc., the flip chip can be easily replaced. Equipment purchases can be eliminated.

【0028】なお、上記の実施の形態では、プリント基
板にフリップチップ10を実装するように説明したが、
フリップチップ10以外の他の電子部品を実装する場合
にも同様に本発明を適用することができる。
In the above embodiment, the flip chip 10 is mounted on the printed circuit board.
The present invention can be similarly applied to a case where other electronic components other than the flip chip 10 are mounted.

【0029】[0029]

【発明の効果】以上説明したように、本発明によれば、
フリップチップ等の電子部品を部品接続電極にはんだバ
ンプで接続した状態で、温度上昇があったときには、微
細導体柱が応力緩和層と共に変形してプリント基板と電
子部品の熱膨張係数の差によるプリント基板と電子部品
の膨張差を吸収することができるため、以下の特長を有
する。 (1)製品動作時の発熱冷却の繰り返しにおいて発生す
る、はんだバンプへの応力を大幅に低減することができ
る。 (2)はんだバンプへの応力が低減するため、従来のプ
リント基板に電子部品を実装する場合に比べて、接続寿
命を向上できる。 (3)はんだバンプへの応力低減を目的とするプリント
基板と電子部品の間隙への補強樹脂の充填を不要にでき
るため、補強樹脂充填のための樹脂及び設備の購入を不
要にでき、安価な構成とすることができる。 (4)プリント基板と電子部品の間隙に補強樹脂を充填
していた従来のプリント基板に比べ、機能検査等におい
てフリップチップ等の電子部品の不具合が検出された場
合、補強樹脂を電子部品から取り外す工程及びプリント
基板に残った補強樹脂を除去する工程などが一切不要で
あり、容易に電子部品を交換することができる。
As described above, according to the present invention,
When the temperature rises when electronic components such as flip chips are connected to component connection electrodes by solder bumps, the fine conductor pillars are deformed together with the stress relaxation layer and printing is performed due to the difference in thermal expansion coefficient between the printed circuit board and the electronic components. Since the difference in expansion between the substrate and the electronic component can be absorbed, it has the following features. (1) It is possible to greatly reduce the stress on the solder bump, which is generated when the heat generation and cooling are repeated during the operation of the product. (2) Since the stress on the solder bumps is reduced, the connection life can be improved as compared with the case where electronic components are mounted on a conventional printed circuit board. (3) Filling of the gap between the printed circuit board and the electronic component for the purpose of reducing the stress on the solder bumps with the filling of the reinforcing resin is not required, so that the purchase of the resin and equipment for filling the reinforcing resin is unnecessary, and the cost is low. It can be configured. (4) When a defect of an electronic component such as a flip chip is detected in a function test or the like as compared with a conventional printed circuit board in which a gap between the printed circuit board and the electronic component is filled with the reinforcing resin, the reinforcing resin is removed from the electronic component. The step and the step of removing the reinforcing resin remaining on the printed circuit board are not required at all, and the electronic components can be easily replaced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

【図2】本発明の一実施の形態の製造工程説明用素子断
面図である。
FIG. 2 is a cross-sectional view of an element for explaining a manufacturing process according to an embodiment of the present invention.

【図3】本発明の一実施の形態のプリント基板にフリッ
プチップを実装した場合の一例の断面図である。
FIG. 3 is a cross-sectional view illustrating an example in which a flip chip is mounted on a printed circuit board according to an embodiment of the present invention.

【図4】本発明の一実施の形態にフリップチップが実装
されている状態で温度上昇があったときの説明図であ
る。
FIG. 4 is an explanatory diagram when a temperature rise occurs in a state where a flip chip is mounted in one embodiment of the present invention;

【図5】従来の一例のプリント基板にフリップチップが
実装されている状態で温度上昇があったときの説明図で
ある。
FIG. 5 is an explanatory diagram when a temperature rise occurs in a state where a flip chip is mounted on a printed circuit board of a conventional example.

【符号の説明】[Explanation of symbols]

1 コア層 2 ビルドアップ層 3 内層導体パターン 4 応力緩和層 5 微細導体柱 6 部品接続電極 7 フォトマスク 8 微細導体柱生成ホール 9 はんだバンプ 10 フリップチップ DESCRIPTION OF SYMBOLS 1 Core layer 2 Build-up layer 3 Inner layer conductor pattern 4 Stress relaxation layer 5 Fine conductor pillar 6 Component connection electrode 7 Photomask 8 Fine conductor pillar generation hole 9 Solder bump 10 Flip chip

フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 1/11 H01L 23/12 F Fターム(参考) 5E317 AA24 BB02 BB12 CC25 CC31 CC51 CD32 CD34 GG09 GG11 5E338 AA03 AA16 BB25 BB63 BB72 CC01 EE01 EE28 5E346 AA06 AA12 AA15 AA25 AA35 AA38 AA43 BB01 BB16 CC08 CC32 CC37 CC38 DD02 DD03 EE31 FF01 FF35 FF45 GG40 HH07 Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (Reference) H05K 1/11 H01L 23/12 FF Term (Reference) 5E317 AA24 BB02 BB12 CC25 CC31 CC51 CD32 CD34 GG09 GG11 5E338 AA03 AA16 BB25 BB63 BB72 CC01 EE01 EE28 5E346 AA06 AA12 AA15 AA25 AA35 AA38 AA43 BB01 BB16 CC08 CC32 CC37 CC38 DD02 DD03 EE31 FF01 FF35 FF45 GG40 HH07

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 内層導体パターンが形成されているビル
ドアップ層上に、電子部品とはんだバンプで接続される
部品接続電極が形成されているプリント基板において、 前記ビルドアップ層上に形成された応力緩和のための応
力緩和層と、 前記ビルドアップ層に形成された前記内層導体パターン
より前記応力緩和層を貫通して引き出されて前記部品接
続電極と接続する微細導体柱とを有することを特徴とす
るプリント基板。
1. A printed circuit board having a component connection electrode connected to an electronic component by a solder bump formed on a build-up layer on which an inner conductor pattern is formed, wherein a stress formed on the build-up layer A stress relaxation layer for relaxation, and fine conductor pillars drawn out through the stress relaxation layer from the inner conductor pattern formed in the build-up layer and connected to the component connection electrode, Printed circuit board.
【請求項2】 前記応力緩和層は、共晶はんだのヤング
率より小さく、前記電子部品の前記部品接続電極へのは
んだ付け時での耐熱性を有し、耐溶剤性で、絶縁性のあ
る耐熱低弾性絶縁物により構成されていることを特徴と
する請求項1記載のプリント基板。
2. The stress relaxation layer is smaller than the Young's modulus of eutectic solder, has heat resistance when soldering the electronic component to the component connection electrode, has solvent resistance, and has insulating properties. 2. The printed circuit board according to claim 1, wherein the printed circuit board is made of a heat-resistant low-elastic insulator.
【請求項3】 前記応力緩和層は、熱膨張係数の差によ
り発生する前記プリント基板と前記電子部品の膨張差に
対して追従する、所定の膜厚で形成されていることを特
徴とする請求項1又は2記載のプリント基板。
3. The stress relaxation layer according to claim 1, wherein the stress relaxation layer is formed to have a predetermined thickness to follow a difference in expansion between the printed circuit board and the electronic component caused by a difference in thermal expansion coefficient. Item 3. The printed circuit board according to item 1 or 2.
【請求項4】 前記微細導体柱は、長さが前記応力緩和
層の膜厚よりも5〜10%長く形成されていることを特
徴とする請求項1記載のプリント基板。
4. The printed circuit board according to claim 1, wherein the length of the fine conductor pillar is formed to be 5 to 10% longer than the thickness of the stress relaxation layer.
【請求項5】 前記微細導体柱は、前記応力緩和層の中
で湾曲又はコイル状に形成されていることを特徴とする
請求項1記載のプリント基板。
5. The printed circuit board according to claim 1, wherein the fine conductor pillar is formed in a curved or coiled shape in the stress relaxation layer.
【請求項6】 前記応力緩和層は、シリコーンゴムによ
り構成されていることを特徴とする請求項1又は2記載
のプリント基板。
6. The printed circuit board according to claim 1, wherein the stress relaxation layer is made of silicone rubber.
JP2000111637A 2000-04-13 2000-04-13 Printed board Pending JP2001298272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000111637A JP2001298272A (en) 2000-04-13 2000-04-13 Printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000111637A JP2001298272A (en) 2000-04-13 2000-04-13 Printed board

Publications (1)

Publication Number Publication Date
JP2001298272A true JP2001298272A (en) 2001-10-26

Family

ID=18623937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000111637A Pending JP2001298272A (en) 2000-04-13 2000-04-13 Printed board

Country Status (1)

Country Link
JP (1) JP2001298272A (en)

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