JP2001298182A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress floating diffusion and parasitic capacity of the input gate of an output transistor as well as a reset transistor to obtain a high electric charge-voltage conversion efficiency, related to an output circuit of a solid-state imaging device. SOLUTION: Related to a gate oxide film structure of a CCD solid-state imaging device, an MONOS structure is provided to a horizontal CCD while an MOS structure is provided for a reset transistor 8. So, due to characteristics of the MONOS structure at a transfer part, the thickness of an oxide film under each gate layer is formed constant. Due to the MOS structure of the film thickness of gate oxide film of the reset transistor 9, a threshold level VTH of the reset transistor 8 is stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state imaging device, and more particularly to a structure of a transfer unit and an output unit in a solid-state imaging device using a MIS (Metal-Insulator-Semiconductor) structure.

[0002]

2. Description of the Related Art FIG. 9 shows an example of a configuration of a CCD solid-state imaging device of, for example, an interline transfer system. In the figure, the incident light is converted into signal charges for each pixel and stored.
A plurality of photosensors (light receiving units) 1 arranged in a three-dimensional array;
An image pickup area is formed by a vertical CCD (vertical transfer unit) 3 which is arranged for each vertical column of the photosensors 1 and vertically scans by transferring signal charges read out via a readout gate (ROG) 2 in the vertical direction. 4 are configured.

[0003] The signal charges read to the vertical CCD 3 are:
The data is sequentially transferred to a horizontal CCD (horizontal transfer unit) 5 for each scanning line. The horizontal CCD 5 receives the 1 transferred from the vertical CCD 3.
Horizontal scanning is performed by transferring the signal charges for the scanning lines in the horizontal direction. The signal charges transferred by the horizontal CCD 5 are accumulated in a floating diffusion 7 via a horizontal output gate (HOG) 6. The signal charge stored in the floating diffusion 7 is reset by the reset transistor 8. The signal whose voltage has been converted by the floating diffusion 7 is impedance-converted and output by the output unit 9 comprising a source follower.

In this type of CCD solid-state imaging device, an MIS structure in which an oxide film is interposed between a gate electrode and a semiconductor substrate is used everywhere. For example, vertical CCD3
The MIS structure is used for the transfer register of the horizontal CCD 5 and the MOS transistor of the source follower of the output unit 9. In the conventional CCD solid-state imaging device, a single type of oxide film is used for the gate oxide film of the MIS structure in each section. MOS structures and MONOS (Metal-SiO ₂ -Si) are currently the mainstream of this single type of oxide film.
₃ N ₄ —SiO ₂ —Si) structure. Each of these structures will be described below.

First, an example of a manufacturing process of a transfer register having a MOS structure is shown in FIGS. 10 (a) to 10 (f).

In the step (a), the SiO _{2 of the} silicon substrate 11 is
This is a step of depositing a first-layer polysilicon 13 on the oxide film 12. In the step (b), the first-layer polysilicon 13 is etched using the resist 14 as a mask to form an electrode of the resistor. At this time, the SiO ₂ oxide film 12 is simultaneously etched by over-etching for completely etching the polysilicon 13.

In the step (c), the first polysilicon layer 1 is formed to insulate the first and second polysilicon gates from each other.
This is a step of oxidizing No. 3. When the first-layer polysilicon 13 is oxidized by this thermal oxidation, a portion not covered by the polysilicon 13 is also oxidized at the same time. In the step (d), polysilicon 15 is used as an electrode material for the second resist layer.
Is deposited. In the step (e), the resist 16 is used as a mask to form the second layer of electrodes for forming the electrodes of the register.
The layer of polysilicon 15 is etched. Step (f)
Then, polysilicon oxidation is performed to complete the CCD register structure.

MOS manufactured by the above process
In the case of a transfer register having a structure, the first-layer polysilicon 13 is oxidized in step (c) in order to separately form the first-layer and second-layer gate oxide films (SiO ₂ oxide films). At this time, if an attempt is made to secure the thickness of the second-layer gate oxide film, the thickness of the first-layer gate oxide film is increased, and the thicknesses t ₁ and t _{2 of the} respective oxide films are different. There is a disadvantage that the channel potential changes.

Next, FIGS. 11 (a) to 11 (f) show the MONO
An example of a gate manufacturing process of an S-structure transfer register is shown.

In the step (a), ONO of the silicon substrate 11 is performed.
(SiO_Two-Si_ThreeN_Four-SiO_Two) On the oxide film 17, the first polysilicon layer
This is a step of depositing the capacitor 13. In step (b)
Is the first layer of polysilicon using the resist 14 as a mask.
13 is etched. At this time, over etching
Therefore, a thin SiO 2 layer on the ONO oxide film 17_TwoLayer (thick
(For example, about 10 nm) 18 is etched
But polysilicon and Si _ThreeN_FourRIE (Reactive-Ion-
Etching) By increasing the selectivity, the intermediate layer Si_Three
N_Four(The thickness is, for example, about 50 nm) is slightly etched
The etching amount is, for example, 1 nm.
Level, which is negligible when viewed from the overall oxide film thickness
Quantity.

In the step (c), a first polysilicon layer 13 is formed.
This is the step of oxidizing. Polysilicon 1 by thermal oxidation
When oxidizing 3, a portion not covered with polysilicon 13 is also oxidized. However, actually, since the oxidation rates of polysilicon and Si ₃ N ₄ are greatly different, the surface of Si ₃ N ₄ is slightly Only by oxidation, the increase or decrease in the film thickness due to the oxidation can be sufficiently ignored from the viewpoint of the overall oxide film thickness. In step (d), polysilicon 15 is deposited as an electrode material of the second-layer resistor. In step (e), the second-layer polysilicon 15 is etched using the resist 16 as a mask to form an electrode of the second-layer resistor. In the final step (f), polysilicon oxidation is performed to complete the CCD register structure.

In this process, although the first and second gate oxide films are separately formed, the feature that the etching amount and oxidation amount of Si ₃ N ₄ can be made sufficiently small is utilized.
Since the thickness of each oxide film can be made substantially constant, there is an advantage that the potential difference between the channel portion under the first-layer polysilicon and the second-layer polysilicon gate can be reduced as compared with the MOS structure process. Therefore, in the manufacturing process of the transfer register, the MONOS structure using the ONO film 17 having a high RIE selectivity with the gate electrode material (polysilicon) is advantageous.

[0013]

By the way, in recent years, CC
D solid-state imaging devices tend to have more pixels. In order to cope with this increase in the number of pixels, the frequency characteristics of the source follower stage of the output unit 9 must be improved. To increase the frequency characteristics of the source follower stage, it is necessary to increase the mutual conductance g _m of the output transistor, the MONOS towards MOS structure which can reduce the thickness of that reason, the gate oxide film
It is more advantageous than the structure.

As shown in the equivalent circuit of FIG. 12, the output section of the horizontal CCD 5 has a pn junction floating diffusion 7 for converting a signal charge from the horizontal CCD 5 into a voltage, and a voltage change of the floating diffusion 7. It comprises an output transistor 10 of a source follower that outputs an impedance-converted signal, and a reset transistor 8 for resetting the charge of the floating diffusion 7.

In this output circuit section, in order to obtain high charge-voltage conversion efficiency, it is necessary to reduce the parasitic capacitance of the floating diffusion 7, the input gate of the output transistor 10, and the reset transistor 8. That is, it is necessary to form the input gate of the first stage of the source follower with a small area. However, in the case of the MONOS structure, such a gate having a small area has a structure similar to that of a memory. Therefore, as shown in FIG.
₃ N ₄ -SiO ₂ liable to affect the charge trapped in the interface, there is a disadvantage of easily threshold level V _TH is changed.

On the other hand, in the case of the MOS structure, Si ₃ N ₄ −
Since the SiO ₂ interface itself does not exist, the change of the threshold level V _TH is hard to occur.
Although the OS structure is more advantageous, as described above, 1
When the thicknesses of the gate oxide films of the second layer and the second layer are different, the channel potential changes, which causes a problem in the CCD register section.

Therefore, the present invention provides a MOS structure and a MONO
Aiming to provide a solid-state imaging device capable of obtaining an oxide film having a stable V _{TH in} a transistor in an output portion and an oxide film having a uniform film thickness in a transfer portion, utilizing both advantages of the S structure. And

[0018]

A solid-state imaging device according to the present invention includes a transfer register for transferring a signal charge, and an impurity diffusion layer for detecting a signal charge transferred by the transfer register and deriving an output signal. And a reset transistor for resetting the signal charge of the impurity diffusion layer, wherein the gate insulating film of the transfer register comprises a first insulating film having a multilayer structure including a nitride film, and the gate insulating film of the reset transistor. Is composed of a second insulating film not containing a nitride film, and the boundary between the first insulating film and the second insulating film is located on the impurity diffusion layer.

In the solid-state imaging device having the above structure, a MONOS structure is used as a gate insulating film structure in a transfer portion.
By using the MOS structure for the output part, the thickness of the insulating film under each gate layer can be made uniform by the characteristic of the MONOS structure in the transfer part, and the V _TH shift can be suppressed by the characteristic of the MOS structure in the output part transistor. Can be. Also, the gate insulating film of the reset transistor has a MOS structure and is formed to be thin, so that the threshold level V of the reset transistor can be reduced.
_{TH is} more stable than that of the MONOS structure. Thus, the amplitude of the reset pulse given to the reset transistor can be small.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a CCD according to an embodiment of the present invention.
FIG. 2 is a cross-sectional structure diagram illustrating a main part of the solid-state imaging device, illustrating only a horizontal transfer portion and an output portion. In FIG. 1, a horizontal CCD 5 and a horizontal output gate 6 which are transfer registers
Adopts a MONOS structure in which a gate insulating film has a multilayer structure including a nitride film, that is, an MONOS structure including an ONO oxide film 17, and the output transistor 10 does not have a charge trap inside the gate insulating film. An MOS structure composed of an insulating film, that is, an SiO ₂ oxide film 12 is employed.

Next, the manufacturing process of the above structure will be described with reference to FIGS. 2 and 3 (steps 1 and 2).

In the step (a), O is implanted on a silicon substrate 11 doped with a predetermined impurity by an ion implanter or the like.
An NO oxide film 17 is formed.
This is a step of depositing a first-layer polysilicon (1Poly) 13 thereon. In the step (b), the first layer of polysilicon 13 is etched using the resist 14 as a mask to form electrodes of the horizontal CCD 5. At this time, the upper thin SiO ₂ layer for the over-etching is etched by taking high RIE selectivity of polysilicon and Si ₃ N _4, only Si ₃ N ₄ of the intermediate layer is slightly etched Thus, this etching amount can be sufficiently ignored from the viewpoint of the entire oxide film thickness.

In the step (c), the Si _{3 in the} MOS formation portion is
To remove the N ₄ —SiO ₂ film, etching is performed using the resist 19 as a mask. Step (d) is a step of oxidizing the first-layer polysilicon 13 in order to insulate the first-layer and second-layer polysilicon gates. When the polysilicon 13 is oxidized by thermal oxidation, a portion that is not covered with the polysilicon 13 is also oxidized. However, since the Si ₃ N ₄ —SiO ₂ film remains in the resistor forming portion, the Si 13 N _{Even when} 3N ₄ is slightly oxidized, the amount of increase or decrease in the film thickness at this time is sufficiently negligible when viewed from the oxide film thickness under the first polysilicon layer 13. On the other hand, the MOS formation portion is sufficiently oxidized because the oxide film has been removed in advance, and has a shape as shown in FIG.
_{2 An} oxide film can be formed.

In the step (e), polysilicon (2Poly) 15 is deposited as a second layer electrode material. In the step (f), the resist 16 is used as a mask for forming the second-layer resistor electrodes and the MOS gate electrodes.
The layer of polysilicon 15 is etched. Then, in the final step, as shown in FIG. 1, polysilicon oxidation is performed, and ion implantation for source / drain is performed by self-alignment to form a MOS transistor structure.

By the above manufacturing process, the MONO is stored in the transfer portion (CCD register) in the same CCD solid-state imaging device.
A CCD solid-state imaging device having an S structure and a MOS structure in an output portion can be realized. As a result, the thickness of the oxide film under each gate layer can be made uniform by using the MONOS structure in the CCD register portion, and the MOS transistor is provided in the output portion of the transistor.
The structure can be used to suppress V _TH shift. Further, by the thickness of the gate oxide film of the output transistor can be formed thinner by a MOS structure, it is possible to increase the mutual conductance g _m of the output transistor 10, since it is possible to increase the frequency characteristics of the resulting source-follower stage Therefore, it is possible to cope with an increase in the number of pixels.

FIG. 4 shows a CC according to another embodiment of the present invention.
FIG. 2 is a cross-sectional structural view showing a main part of a solid-state imaging device D, and shows only a horizontal transfer portion and an output portion.

In the CCD solid-state imaging device according to the present embodiment, a MONOS structure is used for the read gate 2, vertical CCD 3, horizontal CCD 5 and horizontal output gate (HOG) 6 in FIG. In addition, a MOS structure is used for the reset transistor 8 and the output unit 9, and a boundary between the ONO oxide film 17 and the SiO ₂ oxide film 12 is provided on the floating diffusion 7.

Next, the manufacturing process of this structure will be described with reference to FIG.
The process will be described with reference to FIGS. Note that the basic manufacturing process is the same as that of the previous embodiment, and only different portions will be described for simplification of the description.

In step (c), etching is performed to remove the Si ₃ N ₄ —SiO ₂ film. At this time, the boundary to be etched is a floating diffusion (FD) forming portion (see FIG. 4). ). In the step (f), the second-layer polysilicon 15 is etched using the resist 16 as a mask in order to form an electrode of the second-layer resistor and a MOS gate electrode of the reset transistor 8.

In the step (g), the second polysilicon layer 1
5 is oxidized to form, for example, about 60 nm of Si.
An O ₂ oxide film can be obtained. In the step (h), the resist 20 is used as a mask in order to form a high-concentration region of the floating diffusion 7 and a drain (RD) portion of the resetting transistor 8, and a part of the impurity is ion-implanted by self-alignment. . In the final step, as shown in FIG. 4, contact holes 21 are formed in the drain (RD) portions of the floating diffusion 7 and the reset transistor 8.
a and 21b are formed, and the Al electrodes 22a and 22b are patterned to form the present structure.

By adopting the above structure, since the gate structure of the reset transistor 8 is a MOS structure, the threshold level V _TH of the reset transistor 8 is
It is more stable than the NOS structure. For this reason, the reset pulse amplitude can be small, and the power consumption can be reduced. This will be described with reference to FIG.

FIG. 7A shows the reset amplitude required for the MONOS structure, and FIG. 7B shows the reset amplitude required for the MOS structure. In FIG. 7A, a reset amplitude 1 is not only a minimum amplitude 2 originally required for resetting, but also a margin 3 for absorbing variation in impurity dose amount and variation in power supply of a reset pulse driver, and V
_{It consists of} a margin 4 for absorbing variations in the _TH shift.

For example, (reset pulse amplitude 1) = 9 V
Of these, if (margin 4 for absorbing variation in _VTH shift) = 2 V, MO that is less likely to cause _VTH shift
In the case of the S structure, as shown in FIG. 7B, since the margin 4 for absorbing the variation of the V _TH shift is not required,
(Reset pulse amplitude 1) = 7V is sufficient. Since the power consumption is proportional to the square of the pulse amplitude, MONOS
Compared to the structure, the power consumption of the MOS structure is (7 ×
7/9/9) = 0.6, that is, 60%.

At this time, the SiO ₂ oxide film 12 and the ON
Since the boundary of the O-oxide film 17 is located on the floating diffusion 7, a problem due to a difference in film quality does not occur. When provided in the horizontal output gate (HOG) 6 or the reset transistor 8 other than the floating diffusion 7, for example, even if the electrical film thicknesses of the SiO ₂ oxide film 12 and the ONO oxide film 17 are the same, As shown in FIG. 8, electrons are easily trapped at the boundary of the ONO oxide film 17, so that the channel potential changes at the boundary and the transfer of charges is hindered.

[0036]

As described above, according to the present invention,
As the gate insulating film structure of the solid-state imaging device, M
Since the ONOS structure is configured to use the MOS structure for the output portion, the thickness of the insulating film under each gate layer can be made uniform due to the characteristics of the MONOS structure in the transfer portion, and the MOS transistor for the output portion has the MOS structure. _VTH shift can be suppressed depending on the characteristics.

Further, the gate insulating film of the reset transistor is formed thin by the MOS structure,
Reset transistor threshold level V _TH
Is more stable than that _{of the} MONOS structure,
The reset pulse amplitude can be small, and power consumption can be reduced. Further, since the boundary between the gate insulating films of the transfer register and the reset transistor is located on the impurity diffusion layer, there is no problem that the charge transfer is hindered by a difference in film quality.

[Brief description of the drawings]

FIG. 1 is a sectional structural view showing only a main part of a CCD solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a process chart (1) showing a manufacturing process of the CCD solid-state imaging device according to the embodiment;

FIG. 3 is a process diagram (part 2) illustrating a manufacturing process of the CCD solid-state imaging device according to the embodiment;

FIG. 4 is a sectional structural view showing only a main part of a CCD solid-state imaging device according to another embodiment of the present invention.

FIG. 5 is a process chart (1) showing a manufacturing process of a solid-state imaging device according to another embodiment.

FIG. 6 is a process diagram (part 2) illustrating a manufacturing process for the solid-state imaging device according to another embodiment;

FIG. 7 is a diagram showing a relationship between reset pulse amplitudes.

FIG. 8 is a channel potential diagram of a horizontal output gate (HOG) portion.

FIG. 9 is a configuration diagram showing an example of an interline transfer type CCD solid-state imaging device.

FIG. 10 is a process chart showing an example of a manufacturing process of a MOS structure.

FIG. 11 is a process chart showing an example of a manufacturing process of a MONOS structure.

FIG. 12 is an equivalent circuit diagram of an output unit.

FIG. 13 is a diagram showing charge trapping in the MONOS structure.

[Explanation of symbols]

1: photo sensor, 3: vertical CCD, 5: horizontal CCD,
7 ... floating diffusion, 8 ... reset transistor, 10 ... output transistor, 11 ... silicon substrate, 12 ... SiO ₂ oxide film, 17 ... ONO oxide film

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Michio Yamamura 6-35, Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Hideo Kobe 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Shuji Abe 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Michio Mano 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni (72) Inventor Machio Yamagishi 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (1)

[Claims] 1. A transfer register for transferring a signal charge, an impurity diffusion layer for detecting a signal charge transferred by the transfer register to derive an output signal, and resetting a signal charge of the impurity diffusion layer. A reset transistor, wherein the gate insulating film of the transfer register comprises a first insulating film having a multilayer structure including a nitride film, and wherein the gate insulating film of the reset transistor does not include a nitride film. A solid-state imaging device comprising a film, wherein a boundary between the first insulating film and the second insulating film is located on the impurity diffusion layer.