JP2008124395A - Solid state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state imaging apparatus of which a potential amplitude is large and increase in 1/f noise is suppressed. <P>SOLUTION: The solid state imaging apparatus comprises a light receiving part in which pixel cells 1 are arranged by a plurality of numbers, and a peripheral circuit part which drives the pixel cells 1 for taking out signals. The pixel cell 1 at least comprises a phtodiode 2 which receives light to generate signal charges, a transfer transistor 3 which transfers the signal charges generated by the photodiode 2, a floating diffusion layer 5 which converts the transferred signal charge into voltage, a reset transistor 4 which resets the floating diffusion layer 5 to a specified voltage, and an amplifying transistor 6 whose gate input is the potential of the floating diffusion layer 5. The gate oxide film of at least the transfer transistor 3 or the reset transistor 4 is formed in a first film thickness, and the gate oxide film of the amplifying transistor 6 is formed in a second film thickness, with the first film being thicker than the second film. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a structure of a solid-state imaging device, particularly a MOS type solid-state imaging device.

  In recent years, with the progress of miniaturization of semiconductor devices, the miniaturization of MOS-type solid-state imaging devices has also progressed. In the MOS type solid-state imaging device, by reducing the pitch of the pixel cells, even if the area of the light receiving region where the pixel array exists is constant, the light receiving region having a constant area has a larger optical size. Cells can be arranged, and a high-resolution solid-state imaging device can be configured.

  In a solid-state imaging device, when the pixel cell pitch is reduced, priority is given to securing the area of the photodiode region and maintaining the characteristics of sensitivity and the number of saturated electrons. For this reason, the pixels of the pixel cell and the peripheral circuit are miniaturized without reducing the area of the photodiode as much as possible without simply reducing all the elements in proportion.

  FIG. 4 is a circuit diagram illustrating a partial configuration of a conventional solid-state imaging device. A signal from the pixel cell 101 is output to the peripheral circuit portion via the vertical signal line 109. The signal charge generated in the photodiode 102 is transferred to the floating diffusion layer 105 through the transfer transistor 103. The potential in the floating diffusion layer 105 due to the transferred signal charge becomes the gate input of the amplification transistor 106 that constitutes the load transistor 108 and the source follower circuit. The potential of the floating diffusion layer 105 is reset to the potential of the power source 107 by the reset transistor 104.

  Next, the potential amplitude between when the transfer transistor 103 is on and when it is off will be described. FIG. 5 is a diagram illustrating the potential of the photodiode 102, the transfer transistor 103, and the floating diffusion layer 105 with respect to electrons near the surface of the semiconductor substrate. Note that the potential of the boundary region between the transfer transistor 103 and the photodiode 102 and the floating diffusion layer 105 is not displayed.

  In FIG. 5A, a signal charge band 116 is formed by signal charges generated in the photodiode 102 in response to external incident light. A potential 111 indicated by a solid line is a potential when the transfer transistor 103 is off. A potential 112 indicated by a broken line is a potential when the transfer transistor 103 is on, and is displayed together for comparison. The potential 112 has a potential barrier with respect to the signal charge band 116. The difference between the off-time potential 111 and the on-time potential 112 is a potential amplitude 114. The potential 117 is a potential at the time of resetting the floating diffusion layer 105, and is set so as to be higher than the potential of the signal charge band 116 (the lower one is higher in the figure).

  FIG. 5B is a diagram showing the potential when the potential amplitude of the transfer transistor 103 is larger than in the case of FIG. A potential barrier is not formed in the on-state potential 113.

  FIG. 6A is a potential diagram showing a charge transfer state in the transfer transistor 103 having the potential amplitude shown in FIG. In FIG. 6A, the on-state potential 112 is indicated by a solid line, and the off-state potential 111 is indicated by a broken line. A part of the signal charge constituting the signal charge band 118 shown in FIG. 5A moves over the potential 112 at the time of turning on to the floating diffusion layer 105 to form a signal charge band 119. Further, the signal charge remaining in the photodiode 102 forms a signal charge band 118. The remaining signal charge affects the image as an afterimage.

  FIG. 6B is a potential diagram showing a charge transfer state in the transfer transistor 103 having the potential amplitude shown in FIG. In FIG. 6B, the on-state potential 113 is indicated by a solid line, and the off-state potential 111 is indicated by a broken line. For comparison, the potential 112 when the transfer transistor shown in FIG. 6A is on is indicated by a broken line. Since the on-time potential 113 does not serve as a barrier to the signal charge band 116 shown in FIG. 5B, all signal charges move to the floating diffusion layer 105 and form the signal charge band 120. Therefore, the lowest potential of the signal charge band 119 is higher than the lowest potential of the signal charge band 120.

  Next, the influence of the charge accumulation amount in the photodiode 102 due to the magnitude of the potential amplitude in the transfer transistor 103 will be described. FIG. 7 is a diagram showing the magnitude of the potential amplitude for electrons near the surface of the semiconductor substrate of the photodiode 102, the transfer transistor 103, and the floating diffusion layer 105 between the on time and the off time.

  In FIG. 7A, a potential 121 indicated by a solid line is a potential when the transfer transistor 103 is off. A potential 122 indicated by a broken line is a potential when the transfer transistor 103 is on, and is displayed together for comparison. The difference between the off-time potential 121 and the on-time potential 122 is a potential amplitude 124.

  A signal charge is generated in the photodiode 102 by external incident light, and a signal charge band 126 is formed by the signal charge. When the amount of external incident light is large, a part of the signal charge constituting the signal charge band 126 exceeds the barrier of the potential 121 when turned off, and the signal charge moves to the floating diffusion layer 105.

  FIG. 7B is a diagram showing the potential when the potential amplitude of the transfer transistor 103 is larger than in the case of FIG. The off-state potential 123 has a higher potential barrier than the off-state potential 121. Therefore, even if the amount of external incident light is large, signal charges can be accumulated in the photodiode 102.

  FIG. 8A is a potential diagram showing a charge transfer state in the transfer transistor 103 having the potential amplitude shown in FIG. The signal charge accumulated in the photodiode 102 moves to the floating diffusion layer 105 to form a signal charge band 128. Similarly, FIG. 8B is a potential diagram showing a charge transfer state in the transfer transistor 103 having the potential amplitude shown in FIG. 7B, and the signal charge accumulated in the photodiode 102 is floating. It moves to the diffusion layer 105 and forms a signal charge band 129.

  The signal charge band 128 is formed by signal charges that have not leaked among the signal charges generated in the photodiode 102. On the other hand, the signal charge band 129 is formed by all signal charges generated by the photodiode 102.

  Therefore, by increasing the potential amplitude of the transfer transistor 103, signal charge leakage can be suppressed and the dynamic range of the pixel cell 1 shown in FIG. 1 can be widened.

  Next, the magnitude of the reset margin due to the magnitude of the potential amplitude of the reset transistor 104 and the accumulation of signal charges in the floating diffusion layer 105 will be described. FIG. 9 is a diagram showing the potential from the floating diffusion layer 105 to the power supply 107 through the reset transistor 104. FIG. 9A shows a case where the on-time potential 131 is slightly higher than the potential (2.9 V) of the power source 107. If the reset margin 132 is small, the reset margin 132 may not become a positive value due to variations in the potential amplitude of the reset transistor 104 of the reset transistor 104. In this case, the floating diffusion layer 105 is reset to the potential of the power source 107. Can not do it.

  FIG. 9B shows a case where the potential 134 at the time of ON is sufficiently higher than the potential (2.9 V) of the power source 107. With this reset transistor, a sufficient reset margin 135 can be obtained, so that the floating diffusion 105 can be reset to the potential of the power source 107.

  FIG. 10 is a diagram showing the potential from the floating diffusion layer 105 to the power supply 107 through the reset transistor 104. FIG. 10A shows a case where the off-time potential 136 is low. A part of the signal charge forming the signal charge band 133 exceeds the off-time potential 136 and reaches the power source 107. For this reason, the signal charges cannot be sufficiently accumulated in the floating diffusion layer 105. FIG. 10B shows a case where the off-time potential 137 is high. Since the off-time potential 137 has a higher potential barrier than the signal charge band 133, signal charges can be accumulated in the floating diffusion layer 105. Therefore, by increasing the potential amplitude, it is possible to increase the reset margin and prevent leakage at the time of OFF.

  However, the miniaturization of the element goes against the requirement to increase the potential amplitude. As a means conventionally used in a solid-state imaging device, a method of maintaining a gate voltage without scaling a voltage and a gate oxide film thickness even when an element is miniaturized is employed.

The potential amplitude for the gate voltage is
(Cox / (Cox + Cdepl)) × ΔVG (Expression 11)
It is represented by Cox is a gate oxide film capacitance, Cdep1 is a depletion layer capacitance, and ΔVG is a change amount of the gate voltage. In order to increase the value of the potential amplitude, the first method in which the gate oxide film is thinned (1 / k times) with the gate voltage fixed, and the second method in which the gate voltage is increased (k times) with the gate oxide film thickness fixed. There is a way. The potential amplitudes in the first method and the second method are respectively
(K × Cox / (k × Cox + Cdepl)) × ΔVG (Expression 12)
(Cox / (Cox + Cdepl)) × ΔVG × k (Equation 13)
It is represented by In the range of k> 1, the potential amplitude of the second method is always larger. That is, it is more efficient to increase the potential amplitude by increasing the gate voltage than by reducing the thickness of the oxide film.

Further, if the area of the gate electrode is reduced in order to reduce the pixel cell pitch, 1 / f noise increases. In order to solve this problem, a method is also known in which the gate oxide film is thinned (see, for example, Patent Document 1).
JP-A-6-216385

  However, in order to use a high gate applied voltage, it is necessary to match the voltage and set the gate oxide film thickness so that the electric field applied to the oxide film has a strength with which the reliability is guaranteed. In the thermal oxide film, the upper limit of the electric field including reliability is about 5 MV / cm. On the other hand, when the gate oxide film is thickened, the problem is that 1 / f noise increases.

In general, 1 / f noise is
Vn ² = K / (Cox · W · L · f) (Expression 14)
Vn: Noise voltage density [V / Hz ^1/2 ]
K: Constant
Cox: Gate oxide film capacitance [F / μm ² ]
W: Gate width [μm]
L: Gate length [μm]
f: Frequency [Hz]
It is represented by An amplification transistor in a pixel cell in which a size close to the minimum gate length / minimum gate width is used with miniaturization is one of the transistors that are most susceptible to 1 / f noise. If the gate oxide film is made thicker (Cox is made smaller) in order to increase the potential amplitude, 1 / f noise further increases from Equation 14. As described above, increasing the thickness of the gate oxide film for all the transistors in the pixel cell in order to use a high gate application voltage causes a deterioration in the S / N ratio of the solid-state imaging device. This is also a problem for CCDs.

  The present invention has been made to solve the above-described problem, and provides a solid-state imaging device that has a large potential amplitude of at least one of a transfer transistor and a reset transistor and suppresses an increase in 1 / f noise. Objective.

  The solid-state imaging device of the present invention includes a light receiving unit in which a plurality of pixel cells are arranged, and a peripheral circuit unit that drives the pixel cell to extract a signal, and the pixel cell receives light to generate a signal charge. , A transfer transistor for transferring the signal charge generated by the photodiode, a floating diffusion layer for converting the transferred signal charge to a voltage, and a reset transistor for resetting the floating diffusion layer to a predetermined voltage And an amplifying transistor having the potential of the floating diffusion layer as a gate input. In order to solve the above problem, at least one gate oxide film of the transfer transistor and the reset transistor is formed with a first film thickness, and the gate oxide film of the amplification transistor is formed with a second film thickness. The first film thickness is greater than the second film thickness.

  According to the present invention, it is possible to provide a solid-state imaging device that has a large potential amplitude and suppresses an increase in 1 / f noise by increasing the thickness of the gate insulating film in at least one of the transfer transistor and the reset transistor. it can.

  In the solid-state imaging device of the present invention, the maximum value of the gate voltage applied to the transfer transistor or the reset transistor formed with the first film thickness is equal to the maximum value of the gate voltage applied to the amplification transistor. Or it can be a high configuration.

  In addition, among the transfer transistor, the reset transistor, and the amplification transistor, the amplification transistor can be configured to have a minimum gate area. With this configuration, the capacitance of the floating diffusion layer can be reduced, the charge-voltage conversion efficiency can be increased, and noise can be reduced.

  Further, the gate oxide film of the load transistor constituting the amplification transistor and the source follower circuit may be formed with the second film thickness. With this configuration, 1 / f noise of the load transistor can be reduced.

  The area of the gate of the load transistor that constitutes the amplification transistor and the source follower circuit is larger than the area of the gate of the amplification transistor, and the gate oxide film of the load transistor is formed with the first film thickness. Can be configured. Also with this configuration, 1 / f noise of the load transistor can be reduced.

  Further, the channel impurity profile of the amplification transistor may be common to at least one of the channel profiles of the transistors in the peripheral circuit portion.

  Hereinafter, solid-state imaging devices according to embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a partial configuration of a solid-state imaging device according to an embodiment of the present invention.

  A signal from the pixel cell 1 driven by a peripheral circuit unit (not shown) is transmitted to the peripheral circuit unit via the vertical signal line 9 to form image data. The photodiode 2 generates a signal charge corresponding to the amount of received light. The transfer transistor 3 controls the transfer of the signal charge generated by the photodiode 2 to the floating diffusion layer 5. The floating diffusion layer 5 is connected to the gate electrode of the amplification transistor 6, the transfer transistor 3, and the reset transistor 4. The reset transistor 4 resets the potential of the floating diffusion layer 5 to the potential of the power source 7. The amplifying transistor 6 forms a source follower circuit with the load transistor 8 and outputs a potential corresponding to the potential of the floating diffusion layer 5 to the vertical signal line 9. In the solid-state imaging device according to the embodiment of the present invention, a plurality of pixel cells 1 are arranged to form a light receiving unit.

  FIG. 2 is a cross-sectional view showing the configuration of the photodiode 2, the transfer transistor 3, and the floating diffusion layer 5. The transfer transistor 3 includes a gate oxide film 13 (insulating oxide film) formed on the semiconductor substrate 11 between the photodiode 2 and the floating diffusion layer 5, and a gate electrode 12 formed on the gate oxide film 13. have. Although not shown, the reset transistor 4 and the amplification transistor 6 shown in FIG. 1 also have a gate oxide film and a gate electrode formed on the gate oxide film.

  At least one of the transfer transistor 3 and the reset transistor 4 has a gate oxide film formed with a first film thickness, and the gate oxide film of the amplification transistor 6 has a second film thickness smaller than the first film thickness. ing. The maximum value of the gate voltage applied to the transfer transistor 3 and the reset transistor 4 formed with the first film thickness is set equal to or higher than the maximum value of the gate voltage applied to the amplification transistor 6. With this configuration, the potential amplitude can be increased without deteriorating 1 / f noise.

  The amplification transistor 6 is formed such that the gate area (gate length L × gate width W) is the smallest among the gate areas of the transistors of the pixel cell 1 (transfer transistor 3, reset transistor 4, and amplification transistor 6). ing.

  Further, the gate oxide film of the load transistor 8 is formed with the second film thickness.

  In addition, the transistor and the amplification transistor in the peripheral circuit portion have a common impurity concentration and a channel profile in the depth direction, and are configured such that the thicknesses of the gate oxide films are different.

  Hereinafter, the reason why the potential amplitude can be increased without increasing the 1 / f noise in the solid-state imaging device according to the present embodiment will be described in more detail.

  First, in the transistor of the pixel cell 1, the first film thickness is made thicker than the second film thickness, and the maximum voltage applied to the transfer transistor 3 and the reset transistor 4 is made larger than the potential applied to the increasing transistor 6. Will be described in detail.

  For example, when the voltage of the power supply 7 of the pixel cell 1 is 2.5 V, the first film thickness is 9 nm, and the second film thickness is 5 nm, the gate oxide film capacitance Cox in the amplification transistor 6 is equal to the transfer transistor 3. It becomes 9/5 of the gate oxide film capacitance Cox (thickness 9 nm). Therefore, from Equation 14, the 1 / f noise of the amplification transistor 6 can be suppressed to 5/9 of the 1 / f noise of the transfer transistor 3.

  When the upper limit of the electric field of the insulating oxide film is 5 MV / cm, a voltage of 4.5 V at the maximum can be applied to the transfer transistor 3 (film thickness 9 nm). Here, when a maximum voltage of 2.5 V is applied at a film thickness of 5 nm (Equation 1) and when a maximum voltage of 4.5 V is applied at a film thickness of 9 nm (Equation 2), Calculate the potential amplitude.

  Here, ε is the dielectric constant of the gate insulating film, S is the area of the gate insulating film, and Cdepl is the capacity of the depletion layer. When actually calculated based on the actual device parameters, the value of Expression 1> the value of Expression 2 is obtained.

  Therefore, the maximum value of the gate voltage applied to at least one of the transfer transistor 3 and the reset transistor 4 is set equal to or higher than the maximum value of the gate voltage applied to the amplification transistor 6. The transfer transistor 3 and the reset transistor 4 are formed with a thicker gate oxide film than the amplification transistor 6, and the upper limit of the electric field of the gate oxide film is high. By applying a high gate voltage, the potential amplitude of the transfer transistor 3 and the reset transistor 4 can be increased, and the residual charge and the off-state leakage current can be reduced.

  Next, a configuration in which the area of the gate of the amplification transistor 6 is the smallest among the transistors of the pixel cell 1 will be described in detail.

The floating diffusion layer 5 is influenced by many parasitic capacitances as shown in FIG. The parasitic capacitance of the floating diffusion layer 5 includes a capacitance C _J with the substrate 11, a capacitance C _R with the gate electrode of the reset transistor 22, a capacitance C _H with the gate electrode of the transfer transistor 21, and a capacitance with the drain side of the amplification transistor 6. C _D , a capacitor C _S with the source side of the amplification transistor 6 and the like are connected in parallel. The combined capacitance C (effective stray capacitance) of the floating diffusion layer 5 is
C = C _J + C _R + C _H + C _D + C _S (1-G) (Formula 3)
It is. Here, G is the gain of the amplification transistor. The gate width W and gate length L of the amplification transistor 6 contribute to the capacitance _CD and the capacitance _CS value. It is proportional to the gate width W is facing length between the gate electrode and the drain capacitance C _D is the amplifying transistor 6, the gate width W is facing length between the gate electrode and the source of the capacitance C _S amplifying transistor 6 This is because it is proportional.

  In the solid-state imaging device, the charge Q accumulated in the photodiode is converted into charge-voltage by the capacitance C of the floating diffusion layer to obtain the input potential of the amplification transistor. However, the larger the value of input potential = Q / C is Since the S / N ratio is improved, it is desirable to make the capacitance C of the floating diffusion layer as small as possible. Therefore, in this case, by reducing the gate width W and the gate length L of the amplification transistor to reduce the gate capacitance, the capacitance of the effective floating diffusion layer 5 can be reduced and the conversion gain can be increased.

  Further, by shortening the gate width W and the gate length L, the area of the gate of the amplifying transistor 6 in the pixel cell 1 is reduced, so that the photodiode 2 can be made larger.

  As shown in Expression 14, when the gate width W and the gate length L are shortened, 1 / f noise increases. However, by keeping the gate oxide film of the amplifying transistor 6 relatively thin (second film thickness) relative to the gate oxide film of the reset transistor 4 and the transfer transistor 3, the gate capacitance per unit area can be increased. It is possible to suppress the increase in 1 / f noise.

  The gate oxide film of the load transistor 8 is preferably formed with a second film thickness. By configuring the load transistor 8 with the second film thickness, the 1 / f noise can be reduced because the film thickness is small as shown in Expression 14.

  When the gate oxide film of the load transistor 8 is thick (first film thickness), the area of the load transistor 8 (gate length L × gate width W) is set to the area of the amplification transistor 6 (gate length L × gate width). It is desirable to reduce the 1 / f noise by setting a value larger than W). Since the load transistor 8 serves as a constant current source for controlling the current flowing through the amplification transistor 6 of the source follower circuit, the change in the noise current of the load transistor 8 is generated as noise in the output voltage of the amplification transistor 6. Superimposed. Therefore, the reduction of 1 / f noise generated in the load transistor 8 is a reduction in the output noise of the source follower circuit.

  That is, for the load transistor 8, (1) the gate oxide film is formed with the second film thickness as in the amplification transistor 6 of the pixel cell, or (2) the gate oxide film is formed with the first film thickness, Increasing the size of the gate electrode (the load transistor 8 is often arranged in a peripheral circuit, and it is not necessary to reduce the transistor size as the photodiode 2 is enlarged so that the pixel cell 1 is laid out) ) As a guide for the size, at least one of making it larger than the amplification transistor 6 may be performed.

  Further, the gate oxide film thickness of the peripheral circuit transistor (for example, load transistor 8) and the amplifying transistor 6 are different, and the amplifying transistor 6 and the load transistor 8 have a common impurity concentration and a channel profile in the depth direction. Such a configuration may be adopted. In this configuration, the amplification transistor 6 and the load transistor 8 have different transistor characteristics such as threshold voltage. If an attempt is made to make the threshold voltage of the amplification transistor 6 the same as that of the load transistor 8, an additional ion implantation step for adjusting the channel impurity profile is required.

  However, it is not necessary to provide an additional ion implantation step by doing the following. That is, even if the threshold voltage of the amplifying transistor 6 is different from the threshold voltage of the load transistor 8, the drain current of the load transistor 8 constituting the source follower circuit is adjusted by changing the gate bias voltage of the load transistor 8. By doing so, the operating point of the source follower circuit can be changed. Thus, if the operating range is set by adjusting the gate bias voltage setting value of the load transistor 8, it can be used as a source follower circuit. That is, in this configuration, the manufacturing process (the channel impurity profile forming process of the amplification transistor 6) can be reduced by setting the amplification transistor 6 to a common channel impurity profile with the load transistor 8.

  Further, in the case where a CMOS transistor having several types of channel impurity profiles is formed in the peripheral circuit portion of the solid-state imaging device, if one of the CMOS transistors is combined with the formation process of the amplification transistor, additional ion implantation is performed. There is no need to perform a process.

  With the above configuration, the solid-state imaging device according to this embodiment can have a large potential amplitude, and can prevent leakage current when the transistor is off and residual charge when the transistor is on. . Even if the potential amplitude is increased, the increase in 1 / f noise can be suppressed.

  The present invention can be used as a solid-state imaging device having an effect of improving the S / N ratio in a high-resolution solid-state imaging device having fine cells.

1 is a circuit diagram showing a configuration of part of a solid-state imaging device according to an embodiment of the present invention; Sectional drawing which shows the cross-sectional structure of the transfer transistor of a solid-state imaging device same as the above. Circuit diagram showing parasitic capacitance in floating diffusion layer of solid-state imaging device Circuit diagram showing the configuration of part of a conventional solid-state imaging device Potential diagram of the transfer transistor from the photodiode in which the transfer transistor of the conventional solid-state imaging device is off to the floating diffusion layer The potential diagram of the transfer transistor from the photodiode in which the transfer transistor of the solid-state imaging device is on to the floating diffusion layer Potential diagram of the transfer transistor from the photodiode in which the transfer transistor of the conventional solid-state imaging device is off to the floating diffusion layer The potential diagram of the transfer transistor from the photodiode in which the transfer transistor of the solid-state imaging device is on to the floating diffusion layer Potential diagram of reset transistor of conventional solid-state imaging device Potential diagram of reset transistor of conventional solid-state imaging device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel cell 2 Photodiode 3 Transfer transistor 4 Reset transistor 5 Floating diffusion layer 6 Amplification transistor 7 Power supply 8 Load transistor 9 Vertical signal line 11 Substrate 12 Gate electrode 13 Gate insulating film 21 Gate electrode of transfer transistor 22 Gate electrode of reset transistor

Claims (6)

A light receiving unit in which a plurality of pixel cells are arranged;
A peripheral circuit unit that drives the pixel cell and extracts a signal;
The pixel cell is
A photodiode that receives light and generates a signal charge;
A transfer transistor for transferring signal charges generated by the photodiode;
A floating diffusion layer for converting the transferred signal charge into a voltage;
A reset transistor for resetting the floating diffusion layer to a predetermined voltage;
In a solid-state imaging device having at least an amplification transistor having a gate input of the potential of the floating diffusion layer,
At least one gate oxide film of the transfer transistor and the reset transistor is formed with a first film thickness,
The gate oxide film of the amplification transistor is formed with a second film thickness,
The solid-state imaging device, wherein the first film thickness is thicker than the second film thickness.   The solid value according to claim 1, wherein the maximum value of the gate voltage applied to the transfer transistor or the reset transistor formed with the first film thickness is equal to or higher than the maximum value of the gate voltage applied to the amplification transistor. Imaging device.   The solid-state imaging device according to claim 1, wherein the amplification transistor has a minimum gate area among the transfer transistor, the reset transistor, and the amplification transistor.   4. The solid-state imaging device according to claim 1, wherein a gate oxide film of a load transistor constituting the amplification transistor and the source follower circuit is formed with the second film thickness. The area of the gate of the load transistor constituting the amplification transistor and the source follower circuit is larger than the area of the gate of the amplification transistor,
The solid-state imaging device according to claim 1, wherein a gate oxide film of the load transistor is formed with the first film thickness.   6. The solid-state imaging device according to claim 1, wherein a channel impurity profile of the amplification transistor is common to at least one of channel profiles of the transistors in the peripheral circuit portion.

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