KR100728644B1 - Method for manufacturing the cmos image sensor - Google Patents

Abstract

A method for fabricating a CMOS image sensor is provided to increase the capacitance of a floating diffusion node by adding an MIS(Metal Insulator Silicon) capacitor in the floating diffusion node. A silicon substrate(200) having a gate(202) is prepared, and a photodiode and a floating diffusion region(206) are formed in the substrate. A nitride layer(209) is deposited on the substrate with the gate. A metal layer(210a) is formed on a portion of floating diffusion region and the corresponding nitride layer. An insulation layer is deposited on the metal layer, and the insulation layer and the nitride layer are selectively etched to form a trench(214) for exposing a portion of the gate and floating diffusion region and a contact hole(216) for exposing a portion of the metal layer.

Description

Method for manufacturing the CMOS image sensor

1 is a cross-sectional view showing the structure of a CMOS image sensor according to the prior art.

2 is a cross-sectional view illustrating a structure of a CMOS image sensor according to an embodiment of the present invention.

3A to 3F are cross-sectional views sequentially illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention.

<Code Description of Main Parts of Drawing>

200: semiconductor substrate 201: device isolation film

202: gate 203: N-photodiode region

204: P0 region 205: depletion layer

206: floating diffusion region 207: spacer

208: buffer oxide film 209: nitride film

210: metal film 211: etch stop film

212: first insulating film 213: second insulating film

214: trench 215: metal wiring

216: contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a CMOS image sensor, and more particularly, to a method of manufacturing a CMOS image sensor that can increase dynamic capacitance by increasing capacitance of a floating diffusion node of a CMOS image sensor. will be.

CMOS image sensor is a semiconductor device that converts an optical image into an electrical signal. The CMOS image sensor is composed of a light sensing part that detects light and a logic circuit part that processes and converts the detected light into an electrical signal. A switching method is used in which MOS transistors are made by the number of pixels, and the outputs are sequentially detected using the MOS transistors.

The unit pixel of the CMOS image sensor is composed of one photodiode and four NMOS transistors, and four NMOS transistors are transfer transistors for transporting photocharges collected from the photodiodes to the floating node, and nodes at desired values. A reset transistor for setting the potential of and discharging the charge to reset the floating node, a drive transistor acting as a source follower buffer amplifier, and a select transistor addressing to the switching role It consists of.

Recently, as the demand for high-performance CMOS image sensors increases, studies on improving the characteristics of pixels have been actively conducted. In particular, many studies have been conducted on how to improve the dynamic range of pixels.

The dynamic range refers to how much light intensity of a wide area can be discerned, and a large dynamic range means that light intensity can be discerned over a wide range from weak light to strong light.

On the other hand, since the larger the capacitance of the floating diffusion node, the larger the space for storing electrons generated by light, the dynamic region is closely related to the capacitance of the floating diffusion node. .

Therefore, when the capacitance of the floating diffusion region node is increased, even though strong light is incident, the charges stored in the floating diffusion region node are not saturated, and the charges can be stored. The optical characteristics of the image sensor can be improved.

Hereinafter, a structure and a method of forming a CMOS image sensor according to the prior art will be described with reference to the accompanying drawings.

1 is a cross-sectional view showing the structure of a CMOS image sensor according to the prior art.

The CMOS image sensor structure according to the related art includes a silicon substrate 100 provided with an isolation layer 101, as shown in FIG. A gate 102 is formed on the silicon substrate 100. An N-photodiode region 103 having a P0 region 104 formed thereon is formed in the substrate 100 on one side of the gate 102, and floating in the substrate 100 on the other side of the gate 102. The diffusion region 106 is formed. At this time, the depletion layer 105 is formed by the PN junction.

In addition, spacers 107 are formed on both side walls of the gate 102, and the buffer oxide film 108, the nitride film 109, and the first film are formed on the substrate 100 including the gate 102 and the spacer 107. The insulating film 110 and the second insulating film 111 are formed. In the predetermined portions of the films, trenches 112 are formed to expose portions of the floating diffusion region 106 and the upper surface of the gate 102.

In addition, metal trenches 113 electrically connected to the gate 102 and the floating diffusion region 106 are formed in the respective trenches 112. .

As such, the CMOS image sensor can be formed in the following manner.

That is, after the gate electrode film is deposited on the silicon substrate 100 on which the device isolation film 101 is formed, the gate electrode film is selectively etched to form the gate 102.

Then, after the N-photodiode region 103 is formed in the substrate 100 on one side of the gate 102 through an N-type ion implantation process, a P-type is selectively formed on the N-photodiode region 103. An ion implantation process is performed to form the P0 region 104 on top of the N-photodiode region 103. At this time, the depletion layer 105 is formed by the PN junction.

Next, a floating diffusion region 106 is formed in the substrate 100 on the other side of the gate 102 through an impurity ion implantation process. Subsequently, after the nitride film for forming the gate spacer is formed on the silicon substrate 100 including the gate 102, the entire surface is etched to form gate spacers 107 on both sidewalls of the gate 102.

Then, a buffer oxide film 108, a borderless contact (BLC) film 109, a first insulating film 110 and a second insulating film 111 are sequentially deposited on the entire structure obtained therefrom, and then the second insulating film 111 is deposited. The first insulating layer 110, the nitride layer 109, and the buffer oxide layer 108 are selectively etched to form a trench 112 that exposes a portion of an upper surface of the gate 102 and the floating diffusion region 106.

Next, a metal film is formed on the trench 112 and then chemical mechanical polishing (CMP) to form respective metal wires 113 electrically connected to the gate 102 and the floating diffusion region 106. .

However, there is a limit in increasing the junction capacitance of the node in the floating diffusion region 106 formed according to the prior art. Therefore, when strong light is incident, the bonding capacitance of the floating diffusion region 106 node can be easily saturated, resulting in a problem of whitening of the screen and deterioration of light sensitivity characteristics.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to add a metal-insulator-silicon (MIS) capacitor to the floating diffusion node, thereby increasing the capacitance of the floating diffusion node, The present invention provides a method of manufacturing a CMOS image sensor in which the capacitance of the floating diffusion node is not saturated even when light is incident.

In order to achieve the above object, the present invention is to provide a gated silicon substrate, forming a photodiode and a floating diffusion region in the silicon substrate on one side and the other side of the gate, respectively, and on the silicon substrate comprising the gate Depositing a nitride film on the nitride film, forming a metal film on the nitride film corresponding to a portion of the floating diffusion region, depositing an insulating film on the resultant, selectively etching the insulating film and the nitride film, and forming a gate and Forming a trench for exposing a portion of an upper surface of the floating diffusion region and a contact hole for exposing a portion of the metal film; and forming a copper wiring for filling the trench and the contact hole. to provide.

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In the method of manufacturing a CMOS image sensor of the present invention, the forming of the trench and the contact hole may include forming a first photoresist pattern on the insulating layer to expose a portion corresponding to a portion of the gate and the floating diffusion region. Forming respective trenches that expose portions of the gate and the floating diffusion region by etching the insulating layer and the nitride layer using the first photoresist pattern as an etch mask, and removing the first photoresist pattern; Forming a contact hole by forming a second photoresist layer pattern exposing a portion corresponding to a portion of the metal layer on the resultant, etching the insulating layer using the second photoresist pattern as an etch mask, and forming the contact hole; It is preferable to include the step of removing the photosensitive film pattern.

In addition, in the method for manufacturing a CMOS image sensor of the present invention, it is preferable to further include forming a buffer oxide film before forming the nitride film.

In the method of manufacturing a CMOS image sensor of the present invention, the metal film is preferably formed using a TaN film and a TiN film.

In addition, the insulating film is preferably formed by sequentially stacking a BPSG film and a TEOS film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals designate like parts throughout the specification.

Now, a CMOS image sensor and a method of manufacturing the same according to an exemplary embodiment will be described in detail with reference to the accompanying drawings.

CMOS  Image sensor structure

2 is a cross-sectional view illustrating a structure of a CMOS image sensor according to an exemplary embodiment of the present invention.

As illustrated in FIG. 2, a CMOS image sensor according to an exemplary embodiment of the present invention includes a silicon substrate 200 having an isolation layer 201. The gate 202 is formed on the silicon substrate 200.

An N-photodiode region 203 is formed in the substrate 200 on one side of the gate 202, and a P0 region 204 is formed on the N-photodiode region 203. At this time, the depletion layer 205 is formed by the PN junction.

In addition, a floating diffusion region 206 is formed in the substrate 200 on the other side of the gate 202, and spacers 207 are formed on both walls of the gate 202.

On the substrate 200 including the gate 202 and the spacer 207, a buffer oxide film 208, a nitride film 209, a first insulating film 212, and a second insulating film 213 are formed in this order. The trench 214 may be formed at the site to expose a portion of the gate 202 and the floating diffusion region 206. In this case, the first insulating film 212 is made of a BPSG film, and the second insulating film 213 is made of a TEOS film.

In addition, a metal film 210a is formed on a portion of the upper surface of the nitride film 209 between the trenches 214. Here, the metal film 210a is formed of a TaN film or a TiN film.

That is, according to the exemplary embodiment of the present invention, the MIS capacitor including the silicon substrate 200 having the metal film 210a, the insulator below the floating diffusion region 206, and the floating diffusion region 206 is formed at the node of the floating diffusion region 206. It can be seen that formed. Here, the insulator may have a two-layer structure of the buffer oxide film 208 and the nitride film 209.

In addition, contact holes 216 are formed in the first and second insulating films 212 and 213 corresponding to the metal film 210a of the MIS capacitor to expose the upper portion of the metal film 210a. Meanwhile, reference numeral 211, which is not described in the drawings, is an etch stop film which serves as an etch stop during the etching process for forming the contact hole 216, and may be formed of a nitride film.

In each of the trenches 214 and the contact holes 216, metal wirings 215 electrically connected to the gate 202 and the floating diffusion region 106 are formed.

CMOS  Manufacturing Method of Image Sensor

3A to 3F are cross-sectional views sequentially illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention.

As shown in FIG. 3A, after the gate electrode film is deposited on the silicon substrate 200 on which the device isolation film 201 is formed, the gate electrode film is selectively etched to form the gate 202.

Then, an N-photodiode region 203 is formed in the substrate 200 on one side of the gate 202 through an N-type ion implantation process. Next, a P-type ion implantation process is selectively performed on the N-photodiode region 203 to form the P0 region 204 on the N-photodiode region 203. At this time, the depletion layer 205 is formed by the PN junction. Next, a floating diffusion region 206 is formed in the substrate 200 on the other side of the gate 202 through an impurity ion implantation process.

Next, after the nitride film for forming the gate spacer is formed on the silicon substrate 200 including the gate 202, the gate spacer 207 is formed on both sidewalls of the gate 202.

Subsequently, the buffer oxide film 208 and the nitride film 209 are sequentially deposited on the entire structure obtained therefrom.

3B, the metal film 210 and the etch stop film 211 are sequentially deposited on the nitride film 209. The metal film 210 is formed of a TaN film or a TiN film, and serves as a metal film of a subsequently formed MIS capacitor. In addition, the etch stop layer 211 is formed of a nitride layer, and serves as an etch stop layer during an etching process for forming a subsequent contact hole.

Next, as shown in FIG. 3C, the etch stop film 211 and the metal film 210 corresponding to the remaining areas except a part of the floating diffusion region 206 are selectively etched.

Accordingly, in the present embodiment, an MIS capacitor formed of the silicon substrate 200 on which the etched metal film 210a, the insulator and the floating diffusion region 206 are formed is formed.

In this case, the insulator is formed in a two-layer structure of the buffer oxide film 208 and the nitride film 209. That is, since the insulator of the MIS capacitor according to the present invention is formed in the two-layer structure of the buffer oxide film 208 and the nitride film 209, the thickness of the buffer oxide film 208 and the nitride film 209 is adjusted to adjust the thickness of the MIS capacitor. The capacitance can be adjusted to your needs.

In addition, in the present invention, as the MIS capacitor is added to the floating diffusion region 206 node, the capacitance of the floating diffusion region 206 node increases. Therefore, even when strong light is incident, since the capacitor of the floating diffusion region 206 node is not easily saturated, the dynamic region characteristic is improved, and the optical characteristic of the CMOS image sensor is improved.

Then, as shown in FIG. 3D, the first insulating film 212 and the second insulating film 213 are sequentially deposited on the resultant. Here, BPSG may be used as the first insulating layer 212 and TEOS may be used as the second insulating layer 213.

Thereafter, as shown in FIG. 3E, a first photoresist pattern (not shown) defining a trench formation region exposing a portion of the gate 202 and the floating diffusion region 206 is formed on the resultant.

The gate 202 and the floating diffusion region 206 are selectively etched by selectively etching the second insulating film 213, the first insulating film 212, the nitride film 209, and the buffer oxide film 208 using the photoresist pattern as an etching mask. Each trench 214 is formed to expose a portion of the top surface. Then, the first photoresist pattern is removed.

Subsequently, a second photoresist pattern (not shown) is formed on the resultant to expose a region corresponding to a portion of the metal film 210a formed on a part of the nitride film 209 between the trenches 214. . By using the second photoresist layer pattern as an etching mask, the second insulating layer 213, the first insulating layer 212, and the etch stop layer 211 formed on the metal layer 210a are etched to form the metal layer 210a. Contact hole 216 is formed to expose a portion of the &lt; RTI ID = 0.0 &gt; Then, the second photosensitive film pattern is removed.

As described above, instead of separately forming the trenches 214 and the contact holes 216 using the respective etching masks, the trenches 214 and the contact holes 216 may be simultaneously formed using one etching mask.

Next, as shown in FIG. 3F, a metal film is formed on the resultant material to fill the trench 214 and the contact hole 216, and then CMP is formed to form the metal layer in the trench 214 and the contact hole 216. 202 and electrically connected to floating diffusion region 206 form respective metallizations 215.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, but various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also within the scope of the present invention.

As described above, according to the CMOS image sensor and the forming method according to the present invention, the capacitance of the floating diffusion node can be increased by adding an MIS capacitor to the floating diffusion region node.

Accordingly, the capacitor of the floating diffusion region does not easily saturate even when strong light is input, so that the dynamic region characteristic is improved and the light sensitivity characteristic of the CMOS image sensor is improved.

In addition, by controlling the thickness of the insulator formed of the two-layer structure of the buffer oxide film and the nitride film, there is an advantage that the capacitance of the MIS capacitor can be adjusted.

Claims (9)

delete delete delete delete Providing a gated silicon substrate; Forming a photodiode and a floating diffusion region in the silicon substrate on one side and the other side of the gate, respectively; Depositing a nitride film on a silicon substrate including the gate; Forming a metal film on a nitride film corresponding to a portion of the floating diffusion region; Depositing an insulating film on the resultant; Selectively etching the insulating film and the nitride film to form respective trenches exposing portions of upper surfaces of gates and floating diffusion regions and contact holes exposing portions of the metal film; And And forming a copper wiring filling the trench and the contact hole. The method of claim 5, Forming the trench and the contact hole, Forming a first photoresist pattern on the insulating layer to expose a portion corresponding to a portion of the gate and the floating diffusion region; Etching each of the insulating layer and the nitride layer using the first photoresist pattern as an etch mask to form respective trenches that expose portions of the gate and floating diffusion regions; Removing the first photoresist pattern; Forming a second photoresist pattern on the resultant portion, the second photoresist pattern exposing a portion corresponding to a portion of the metal film; Forming a contact hole by etching the insulating layer using the second photoresist pattern as an etch mask; And And removing the second photoresist pattern. The method of claim 5, Before forming the nitride film, further comprising forming a buffer oxide film. The method of claim 5, The metal film is a CMOS image sensor manufacturing method, characterized in that formed using a TaN film and TiN film. The method of claim 5, The insulating film is a CMOS image sensor manufacturing method, characterized in that formed by sequentially stacking the BPSG film and TEOS film.

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