KR20120138532A - Cmos image sensor and method for fabricating the same - Google Patents

Cmos image sensor and method for fabricating the same Download PDF

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KR20120138532A
KR20120138532A KR1020110058082A KR20110058082A KR20120138532A KR 20120138532 A KR20120138532 A KR 20120138532A KR 1020110058082 A KR1020110058082 A KR 1020110058082A KR 20110058082 A KR20110058082 A KR 20110058082A KR 20120138532 A KR20120138532 A KR 20120138532A
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layer
image sensor
cmos image
type impurity
conductivity type
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KR1020110058082A
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Korean (ko)
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박유배
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주식회사 동부하이텍
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Publication of KR20120138532A publication Critical patent/KR20120138532A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607—Geometry of the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

According to the present invention, a photodiode layer is formed on an insulating layer formed by etching a portion of a semiconductor substrate, thereby blocking a electrical connection between the photodiode layers to fundamentally block signal interference between pixels, and a CMOS image sensor It relates to a manufacturing method.
To this end, a method of manufacturing a CMOS image sensor according to an embodiment of the present invention includes forming an insulating layer for etching a portion of a substrate to isolate pixels, and depositing a conductive material on the insulating layer to form a photodiode layer. Forming the first and second conductivity type impurity ion layers by injecting different impurity ions into both sides of the photodiode layer, and forming first and second contacts respectively connected to the first and second conductivity type impurity ion layers. Forming a metal wire for a reset electrode connected to the first contact and a metal wire for connection to the first conductivity type impurity ion layer and the sensing gate through the second contact after the formation;

Description

CMOS image sensor and its manufacturing method {CMOS IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a semiconductor device, and more particularly, to a CMOS image sensor which can fundamentally block signal interference between pixels by forming a photodiode layer on an insulating layer formed by etching part of a semiconductor substrate, and fabrication thereof. It is about a method.

Currently, CMOS image sensors are dominant in the field of solid-state imaging because they are easier to manufacture and can be produced at lower cost than charge coupled devices (CCDs). Such a CMOS image sensor may be implemented in a narrower area than a CCD as the unit pixel is composed of MOS transistors, thereby providing high resolution. Furthermore, signal processing logic such as correlated double sampling (CDS), analog digital convertor (ADC), and ramp generators can be formed simultaneously with the MOS transistors that make up the pixel, Another advantage is that one chip manufacturing is possible.

The unit pixel of the CMOS image sensor is composed of a photodiode for sensing an image and transistors for delivering a signal sensed by the photodiode to a signal processing circuit. Is shown.

Referring to FIG. 1, in the conventional CMOS image sensor arrangement method, M columns are arranged based on one column of 1-N pixels to convert an incident light source signal into an electrical image signal.

A process of manufacturing the CMOS image sensor illustrated in FIG. 1 will be described below with reference to FIG. 2.

FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1. Like reference numerals in FIGS. 1 and 2 denote the same regions or layers.

As illustrated in FIG. 2, a method of manufacturing a CMOS image sensor may be largely formed by a process for forming a photodiode and a process for isolation. That is, after forming a device isolation mask, for example, an insulating layer on the semiconductor substrate 10, the trench is formed by etching an area of the semiconductor substrate 10 exposed by the device separation mask, and an insulating material is embedded in the trench. The separator 20 is formed.

Thereafter, an ion implantation process is performed on a region other than the region formed in the device isolation layer 20 to form a photodiode 30 for optical signal sensing. That is, the photodiode 30 for sensing the optical signal is formed by forming an N-type impurity layer between the device isolation layers 20 by performing an opposite type, for example, an N-type impurity ion implantation process, to the semiconductor substrate 10. .

The CMOS image sensor produced according to the prior art is manufactured by closely adhering pixels to the left and right for high resolution, so that an optical signal to be incident on an adjacent pixel enters a pixel to be read out or an electrical signal generated within the adjacent pixel is read out. There is a problem that crosstalk such as propagation to a target pixel occurs.

In addition, there is a problem in that the incident light signal and the electric signal is small when going to the dense small pixels.

On the other hand, there is a problem in that an afterimage is generated by acting as a barrier to the movement of electrons generated in the pixel by increasing parasitic capacitance generated at the connection portion of the readout circuit and the pixels.

In order to solve the problems described above, an object of the present invention is to form a photodiode layer on top of the insulating layer formed through the STI process, thereby blocking the electrical connection between the photodiode layer to reduce the signal interference between each pixel It is to provide a CMOS image sensor that can be fundamentally blocked and a manufacturing method thereof.

In addition, the present invention provides a CMOS image sensor and a method of manufacturing the same to form a reset control gate on the photodiode layer to reduce reverse voltage leakage after reset.

The present invention provides a CMOS image sensor and a method of manufacturing the same, by selecting the readout control gate 152 on the photodiode layer.

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, the method for manufacturing a CMOS image sensor according to an embodiment of the present invention comprises the steps of forming an insulating layer for etching a portion of the substrate to isolate between pixels, and a conductive material on top of the insulating layer Forming a photodiode layer, implanting different impurity ions into both sides of the photodiode layer to form first and second conductivity type impurity ion layers, and forming the first and second conductivity type impurity ion layers After forming the first and second contacts connected to each other, the metal wiring for the reset electrode connected to the first contact and the metal wiring for connecting the first conductive impurity ion layer and the sensing gate through the second contact are formed. It includes a step.

The forming of the insulating layer in the CMOS image sensor manufacturing method according to an embodiment of the present invention, after etching a portion of the substrate through an STI process to form the insulating layer by embedding an insulating material in the etched region. It is characterized by.

In the CMOS image sensor manufacturing method according to an embodiment of the present invention, the conductive material is characterized in that the P-type or N-type polysilicon or silicon crystal material.

The method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention may further include forming a control gate on an upper portion of the gate insulating layer after forming a gate insulating layer on the photodiode layer. .

In the method of manufacturing a CMOS image sensor according to an embodiment of the present disclosure, the forming of the control gate may include forming a reset control gate in an upper portion of the photodiode layer so as to be connected to the first conductivity type impurity ion layer. do.

In the method of manufacturing a CMOS image sensor according to an embodiment of the present disclosure, the forming of the control gate may include forming a readout control gate in an upper portion of the photodiode layer to be connected to the second conductivity type impurity ion layer. It is done.

The forming of the control gate in the method of manufacturing a CMOS image sensor according to an embodiment of the present disclosure may include forming a reset control gate in an upper portion of the photodiode layer so as to be connected to the first conductivity type impurity ion layer; And forming a readout control gate in another area of the photodiode layer so as to be connected to the second conductivity type impurity ion layer.

In the CMOS image sensor manufacturing method according to an embodiment of the present invention, the control gate is formed using a metal material or a metal silicide.

In the method of manufacturing a CMOS image sensor according to an embodiment of the present invention, the second conductivity type impurity ion layer is formed through an ion implantation process using impurity ions to form a diode with the first conductivity type impurity ion layer. It is done.

According to another aspect of the present invention, a CMOS image sensor according to an embodiment of the present invention, an insulating layer formed to etch a portion of the substrate to isolate between pixels, a photodiode layer formed on the insulating layer, and the photo First and second conductivity type impurity ion layers formed on both sides of the diode layer, first and second contacts respectively connected to the first and second conductivity type impurity ion layers, and metal wiring for reset electrodes connected to the first contact; And a connection metal wiring connecting the second conductivity type impurity ion layer to the sensing gate through the second contact.

In the CMOS image sensor according to an exemplary embodiment of the present invention, the insulating layer is formed by etching a portion of the substrate through an STI process and then embedding an insulating material.

In the CMOS image sensor according to the embodiment of the present invention, the photodiode layer is formed using a P-type or N-type polysilicon or a silicon crystal material.

The CMOS image sensor may further include a gate insulating layer formed on the photodiode layer and a control gate formed on a portion of the gate insulating layer.

In the CMOS image sensor according to an exemplary embodiment of the present disclosure, the control gate may be a reset control gate formed in an upper portion of the photodiode layer to be connected to the first conductivity type impurity ion layer.

In the CMOS image sensor according to an exemplary embodiment of the present disclosure, the control gate may be a readout control gate formed in a portion of the photodiode layer so as to be connected to the second conductivity type impurity ion layer.

In the CMOS image sensor according to an exemplary embodiment of the present disclosure, the control gate may be connected to a reset control gate formed at an upper portion of the photodiode layer so as to be connected to the first conductivity type impurity ion layer and the second conductivity type impurity ion layer. Preferably, the lead-out control gate is formed in another area of the photodiode layer.

In the CMOS image sensor according to an embodiment of the present invention, the control gate is formed using a metal material or a metal silicide.

According to the CMOS image sensor manufacturing method according to an embodiment of the present invention, by forming a photodiode layer on the insulating layer formed through the STI process, it is possible not only to block the electrical connection between the photodiode layer but also incident of the optical signal Since the voltage signal generated in the photodiode layer is blocked by the insulating layer, there is an effect that can fundamentally block the signal interference between each pixel.

In addition, according to an embodiment of the present invention, by forming the reset control gate and the readout control gate on the photodiode layer, not only can the reverse voltage leakage be reduced after reset, but also the readout time point can be selected, so that the timing at the readout time can be reduced. Can increase the stability.

1 is a view for explaining an arrangement structure of a CMOS image sensor according to the prior art,
FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1;
3 is a layout showing a CMOS image sensor device according to an embodiment of the present invention;
4 is a cross-sectional view taken along the line BB 'of FIG.
5A illustrates a state in which only a reset control gate is formed in a CMOS image sensor according to an exemplary embodiment of the present invention;
5B is a view illustrating a state in which only a readout control gate is formed in a CMOS image sensor according to an embodiment of the present invention;
6A through 6E are cross-sectional views illustrating a process of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a CMOS image sensor and a manufacturing method thereof capable of minimizing crosstalk and readout signal delay between adjacent pixels will be described in detail with reference to the accompanying drawings.

3 is a layout diagram illustrating a CMOS image sensor device according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along the line BB ′ of FIG. 3. The same reference numerals in FIGS. 3 to 4 denote the same regions or layers.

3 to 4, a CMOS image sensor according to an embodiment of the present invention defines an insulating layer 102 and an active region 103 formed to etch a portion of the semiconductor substrate 100 to isolate pixels from each other. The device isolation film 104, the photodiode layer 110 formed on the insulating layer 102, and the first and second conductivity type impurity ion layers 112 and 114 formed on both sides of the photodiode layer 110. First and second contacts 120 and 122 connected to the first and second conductivity type impurity ion layers, respectively, the metal wiring 130 for the reset electrode connected to the first contact 120 and the second through the second contact 122. A metal wiring 132 for connecting the conductive impurity ion layer 114 and the sensing gate 158, a reset control gate electrode 150, an output control gate electrode 152, a pixel lead-out connection wiring 154, and a switching. The gate 156, the sensing gate 158, and the like may be included.

The insulating layer 102 may be formed through an STI process for forming the device isolation layer 104. That is, the insulating layer 102 may be formed by etching a portion of the semiconductor substrate 100 and then embedding an insulating material in the etched region. .

In the CMOS image sensor according to the exemplary embodiment of the present invention, the photodiode layer 110 is formed on the insulating layer 102, so that the photodiode layer 110 of each pixel can be separated without electrical connection. That is, the voltage signal formed by the incidence of the optical signal may be protected by the insulating layer 102 to fundamentally block signal interference between each pixel.

Meanwhile, the photodiode layer 110 may be formed using polysilicon, for example, P-type or N-type polysilicon or a silicon crystalline material (intrinsic semiconductor material) used as the gate electrode.

Then, in order to use the photodiode layer 110 as a diode in a pixel of the CMOS image sensor, an impurity ion implantation process is performed to form source / drain regions in some regions of both sides of the photodiode layer 110. The two conductivity type impurity ion layers 112 and 114 can be formed. Here, the first conductivity type impurity ion layer 112 may be formed through an N + impurity ion implantation process, and the second conductivity type impurity ion layer 114 may be formed through a P + impurity ion implantation process.

In addition, spacers 110a may be formed on both sidewalls of the first and second conductivity type impurity ion layers 112.

On the other hand, the CMOS image sensor according to an embodiment of the present invention, the reset control gate 150 and the readout control formed on the gate insulating layer 116 and the upper portion of the gate insulating layer 116 on the photodiode layer 110. It may further include a gate 152. That is, after forming a gate insulating layer 116 by forming a nitride film of a predetermined insulating material, for example, a thin film on the photodiode layer 110, the reset control gate 150 to be used as an electrode layer and read out control thereon. The gate 152 may be formed.

The reset control gate 150 and the readout control gate 152 according to the embodiment of the present invention may be formed using a metal or a silicide layer of metal.

According to an exemplary embodiment of the present disclosure, the control gates may be disposed at both ends of the photodiode layer 110 to separate the reset and read-out time points, and thus, the reverse voltage leakage after the photodiode layer 110 is reset. In addition to reducing leaks, the lead-out time can be selected.

In the exemplary embodiment of the present invention, the reset control gate 150 and the readout control gate 152 are formed at both ends of the photodiode layer 110, but the first conductive type is illustrated as shown in FIG. 5A. Only the reset control gate 150 is formed in a portion of the upper portion of the photodiode layer 110 so as to be connected to the impurity ion layer 112, or as shown in FIG. 5B, the photodiode layer is connected to the second conductivity type impurity ion layer 114. Only the readout control gate 152 may be formed in a portion of the upper portion 110.

A process of manufacturing a CMOS image sensor having the above structure will be described with reference to FIGS. 6A to 6E.

6A through 6E are cross-sectional views illustrating a process of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention.

As shown in FIG. 6A, first, a portion of the semiconductor substrate 100 is etched, and then an insulating layer for isolating the device isolation layer 104 and the pixel for defining an active region by filling an insulating material in the etched region. 102 can be formed. That is, after insulating a portion of the semiconductor substrate 100 through a shallow trench isolation (STI) process, an insulating material is deposited, and a planarization process, for example, a chemical mechanical polishing process, on the deposited insulating material is performed to form an insulating layer 102. ) And the device isolation layer 104 may be formed.

6B, a conductive material is deposited on the insulating layer 102 to form the photodiode layer 110, and then a spacer 110a is formed on the sidewalls of the photodiode layer 110. Herein, the conductive material may be P type polysilicon, N type polysilicon, or silicon crystalline material (intrinsic semiconductor material).

Thereafter, as shown in FIG. 6C, a photoresist pattern (not shown) for opening a portion of the photodiode layer 110, that is, a left portion of the photodiode layer 110 is formed, and then using the photoresist pattern. The N + impurity ion implantation process is performed to form the first conductivity type impurity ion layer 112, and the photoresist pattern is removed through a strip process. Then, after forming a photoresist pattern (not shown) that opens the right portion of the photodiode layer 110, a P + impurity ion implantation process using the photoresist pattern is performed to form the second conductivity type impurity ion layer 114. And remove the photoresist pattern through a strip process.

In the exemplary embodiment of the present invention, the second conductive impurity ion layer 114 is formed by performing an N + impurity ion implantation process. For example, the first conductive impurity ion layer 112 and the diode may be formed. It will be apparent to those skilled in the art that the second conductivity type impurity ion layer 114 can be formed using impurity ions.

6D, the gate insulating layer 116 is formed on the photodiode layer 110 including the first and second conductivity type impurity ion layers 112 and 114, and then the gate insulating layer ( The reset control gate 150 and the readout control gate 152 are formed on the top of the 116. More specifically, after the gate insulating layer 116 of the thin film is formed on the photodiode layer 110, the reset control gate (not shown) may be formed at the boundary of the first conductivity type impurity ion layer 112 through a metal silicide or metal deposition process. In addition, the lead-out control gate 152 is formed at the boundary of the second conductivity type impurity ion layer 114.

Subsequently, as shown in FIG. 6E, the first and second contacts 120 and 122 are formed through the metal wiring process, and the reset electrode metal wiring 130 and the second contact are connected to the first contact 120. A connection metal line 132 for connecting the second conductivity type impurity ion layer 114 to the sensing gate 158 through 122 is formed.

According to the CMOS image sensor manufacturing method according to an embodiment of the present invention, by forming a photodiode layer 110 on the insulating layer 102 formed through the STI process, the electrical connection between the photodiode layer 110 is blocked. In addition, since the voltage signal generated in the photodiode layer 110 is blocked by the insulating layer 102 by the incidence of the optical signal, it is possible to fundamentally block signal interference between the pixels.

In addition, according to an embodiment of the present disclosure, by forming the reset control gate 150 and the readout control gate 152 on the photodiode layer 110, the reverse voltage leakage after the reset may be reduced as well as readout. You can select a time point.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand.

100 semiconductor substrate 102 insulating layer
104: device isolation layer 110: photodiode layer
110a: spacer
112 and 114: first and second conductivity type impurity ion layers
116: gate insulating layer 120, 122: first and second contacts
130: metal wiring for the reset electrode 132: metal wiring for the connection
150: reset control gate 152: readout control gate 1

Claims (18)

Etching a portion of the substrate to form an insulating layer for isolating pixels;
Depositing a conductive material on top of the insulating layer to form a photodiode layer;
Implanting different impurity ions into both sides of the photodiode layer to form first and second conductivity type impurity ion layers;
Forming first and second contacts connected to the first and second conductivity type impurity ion layers, respectively, and sensing the first conductive type impurity ion layer and the second conductive metal wire for reset electrode connected to the first contact. Forming a metal wire for connection to the gate;
CMOS image sensor manufacturing method.
The method of claim 1,
In the forming of the insulating layer, after etching a portion of the substrate through an STI process, an insulating material is embedded in the etched region to form the insulating layer.
CMOS image sensor manufacturing method.
The method of claim 1,
The conductive material is characterized in that the P-type or N-type polysilicon or silicon crystal material
CMOS image sensor manufacturing method.
The method of claim 1,
The CMOS image sensor manufacturing method,
And forming a control gate on the upper portion of the gate insulating layer after forming the gate insulating layer on the photodiode layer.
CMOS image sensor manufacturing method.
The method of claim 4, wherein
The forming of the control gate may include forming a reset control gate in an upper portion of the photodiode layer so as to be connected to the first conductivity type impurity ion layer.
CMOS image sensor manufacturing method.
The method of claim 4, wherein
The forming of the control gate may include forming a readout control gate in an upper region of the photodiode layer so as to be connected to the second conductivity type impurity ion layer.
CMOS image sensor manufacturing method.
The method of claim 4, wherein
Forming the control gate,
Forming a reset control gate in a portion of an upper portion of the photodiode layer so as to be connected to the first conductivity type impurity ion layer;
And forming a readout control gate in an upper region of the photodiode layer so as to be connected to the second conductivity type impurity ion layer.
CMOS image sensor manufacturing method.
8. The method according to any one of claims 4 to 7,
The control gate is formed using a metal material or a metal silicide
CMOS image sensor manufacturing method.
The method of claim 1,
The second conductivity type impurity ion layer is formed through an ion implantation process using impurity ions to form a diode with the first conductivity type impurity ion layer.
CMOS image sensor manufacturing method.
An insulating layer formed to etch a portion of the substrate to isolate the pixels;
A photodiode layer formed on the insulating layer;
First and second conductivity type impurity ion layers formed on both sides of the photodiode layer;
First and second contacts connected to the first and second conductivity type impurity ion layers, respectively;
A metal wiring for a reset electrode connected to the first contact;
And a connection metal wiring connecting the second conductivity type impurity ion layer to the sensing gate through the second contact.
CMOS image sensor.
11. The method of claim 10,
The insulating layer is formed by etching a portion of the substrate through an STI process and then embedding an insulating material.
CMOS image sensor.
11. The method of claim 10,
The photodiode layer is formed using a P-type or N-type polysilicon or silicon crystal material
CMOS image sensor.
11. The method of claim 10,
The CMOS image sensor,
A gate insulating layer formed on the photodiode layer;
And a control gate formed on an upper portion of the gate insulating layer.
CMOS image sensor.
The method of claim 13,
The control gate may be a reset control gate formed in an upper portion of the photodiode layer so as to be connected to the first conductivity type impurity ion layer.
CMOS image sensor.
The method of claim 13,
The control gate is a lead-out control gate formed in a portion of the upper portion of the photodiode layer so as to be connected to the second conductivity type impurity ion layer.
CMOS image sensor.
The method of claim 13,
The control gate,
A reset control gate formed in an upper portion of the photodiode layer so as to be connected to the first conductivity type impurity ion layer;
And a lead-out control gate formed in another region of the photodiode layer so as to be connected to the second conductivity type impurity ion layer.
CMOS image sensor.
The method according to any one of claims 13 to 16,
The control gate is formed using a metal material or a metal silicide
CMOS image sensor.
11. The method of claim 10,
The second conductivity type impurity ion layer is formed through an ion implantation process using impurity ions to form a diode with the first conductivity type impurity ion layer.
CMOS image sensor.
KR1020110058082A 2011-06-15 2011-06-15 Cmos image sensor and method for fabricating the same KR20120138532A (en)

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