JP2001284824A - Manufacturing method of printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To propose a manufacturing method of a printed wiring board which enables to connect accurately a via-hole to a terminal of a capacitor contained on a core board. SOLUTION: An opening for a via-hole 42 is formed with a laser device on a resin layer insulation layer 40 on a core board 30 which contains a chip capacitor. On both sides thereof a hole for a through-hole 46 is formed with the same laser machining device, by which a misregistration is avoided and connecting terminals 21 and 22 of the chip capacitor 20 and a via-hole is assured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board in which front and back surfaces are electrically connected via through holes, upper and lower conductive circuits are insulated by an interlayer insulating layer, and both are connected by via holes. In particular, the present invention relates to a printed wiring board having a built-in capacitor.

[0002]

2. Description of the Related Art Conventionally, build-up multilayer printed wiring boards are disclosed in, for example, Japanese Patent Application Laid-Open Nos. 9-130050 and 9-1.
53683, JP-A-9-172261, JP-A-9-172
It is manufactured by a method disclosed in JP-A-246724, JP-A-10-135538 and the like. That is, a through hole is formed in the core substrate with a drill, and a through hole is formed in the core substrate. Thereafter, an interlayer resin insulating layer is laminated on the substrate, and a via hole is formed in the interlayer resin insulating layer by exposure and development processing or laser to form a circuit pattern. By repeating this, a build-up multilayer printed wiring board is obtained. Here, the through-hole and the via-hole are aligned based on the positioning marks formed on the core substrate, and are opened by separate devices.

Further, the present applicant has filed Japanese Patent Application No. 11-24831.
No. 1 proposed a technique in which a concave portion is formed in a core substrate and a chip capacitor is accommodated in the concave portion for the purpose of smoothly supplying power to an IC chip of a printed wiring board for a package substrate.

[0004]

However, since the formation of the through-hole and the formation of the via-hole are performed by different devices and methods, an error occurs in the positioning mark every time the alignment is performed, and the through-hole and the via-hole are formed. Misalignment has occurred between via holes. Further, there is a problem that the positioning mark itself is shifted. This will be described with reference to FIG. As shown in FIG. 10A, a conductor circuit 343 and a positioning mark 345 are provided on a core substrate 330, and an interlayer resin insulating layer 340 is formed on the conductor circuit 343. First, the positioning mark 345 is photographed by the camera 80, aligned, and a through hole 346 for a through hole is formed by a drill (not shown) (FIG. 10B). Then, after the resin residue remaining in the through hole 346 is removed by desmearing, annealing is performed to remove the interlayer resin insulating layer 34.
Cure 0. At this time, as shown in FIG. 10C, the entire substrate 430 contracts due to thermal contraction, and the positioning mark 345 is shifted. Then, even if the shifted positioning mark 345 is imaged by the camera 80 and the opening 348 for the via hole is formed by the laser, the through hole 34
6 and the conductor circuit 343 is displaced (FIG. 10C).

Here, FIGS. 10 (F1), (F2), (F
3) accommodates the chip capacitor 320 in the core substrate,
The via hole 360 allows the terminal 32 of the chip capacitor
1 shows a state where an attempt is made to establish a connection with the device 1. FIG.
(F1) shows a state in which the via hole 360 is properly connected to the terminal 321. FIG. 10 (D)
As described above with reference to FIG. 10, the via hole is displaced, and the via hole 360 is poorly connected to the terminal 321 as shown in FIG. 10 (F2), or as shown in FIG. 10 (F3). There is a problem that it is not connected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method of manufacturing a printed wiring board capable of reliably connecting via holes to terminals of a capacitor built in a core substrate. It is to propose.

[0007]

In order to achieve the above object, according to the first aspect of the present invention, an interlayer resin insulating layer is provided on a substrate having a built-in capacitor and electrically connected on the front and back sides through through holes. In a method of manufacturing a printed wiring board in which conductive circuits are alternately laminated and each conductive layer is connected by a via hole, the technical feature is that the through hole and the via hole are formed by the same laser processing. I do. That is, they are formed by the same laser processing apparatus.

According to the first aspect, the through hole and the via hole are formed by using the same laser processing apparatus. That is, since the positioning is not separately performed in the through-hole forming step and the via-hole forming step, there is no positional error due to the device and the method in the through-hole forming step and the via-hole forming step. Further, since no heat or stress is applied to the substrate between the through-hole forming step and the via-hole forming step, the positioning mark does not shift due to contraction or warpage of the substrate, and the through-hole and via hole are formed in the substrate. Holes can be formed. Since there is no positional error of the via hole, the via hole can be accurately connected to the terminal of the capacitor housed in the core substrate. There is no displacement between the through hole and the via hole, and it is possible to prevent disconnection, poor connection and short circuit of wiring.

The method for manufacturing a printed wiring board according to claim 2 is
Technical features include at least the following steps (a) to (e): (a) a step of incorporating a capacitor in the core substrate; and (b) a step of forming an interlayer resin insulating layer on the core substrate. (C) mounting the core substrate on a processing table of a laser processing apparatus, and providing an opening for forming a via hole to the interlayer resin insulating layer by irradiating a laser to a terminal of the capacitor; (d) Before and after the step (c), a step of forming a through-hole for a through-hole in the substrate while being placed on a processing table of the laser processing apparatus used in the step (c); (e) the through-hole And forming a conductive film in the opening, and providing a through hole and a via hole.

According to a second aspect of the present invention, an interlayer resin insulating layer is laminated on a core substrate in which a capacitor is formed, and then a via hole opening reaching a terminal of the capacitor is formed by a laser. Further, before and after the via hole opening forming step, through-holes for through holes are formed by the same laser processing apparatus. That is, since alignment is not performed by a separate apparatus and method in the through-hole forming step and the via-hole forming step, the position error due to the apparatus and the construction method is reduced in the through-hole forming step and the via-hole forming step. Does not occur.
Since no positional error occurs in the via hole, the via hole can be accurately connected to the terminal of the capacitor housed in the core substrate. Further, since no heat is applied to the substrate between the through-hole forming step and the via-hole forming step, the through-holes and via-holes are formed on the substrate without any displacement of the positioning mark due to contraction or warpage of the substrate. Can be formed. There is no displacement between the through hole and the via hole, and it is possible to prevent disconnection or short circuit of the wiring.

The technical feature of the method for manufacturing a printed wiring board according to the third aspect is that the method includes at least the following steps (a) to (e): (a) a step of incorporating a capacitor in a core substrate; b) a step of forming an interlayer resin insulation layer on the core substrate; (c) placing the core substrate on a processing table of a laser processing apparatus, and irradiating the interlayer resin insulation layer with a laser to thereby provide terminals of the capacitor Providing an opening for forming a via hole and an opening for forming a through hole leading to; (d) placing the opening for forming the through hole in a state of being mounted on the processing table of the laser processing apparatus used in the step (c). Irradiating the opening with a laser to form a through-hole for the through-hole in the substrate; (e) forming a conductive film in the through-hole and the opening, and providing a through-hole and a via-hole.

According to a third aspect of the present invention, an interlayer resin insulating layer is laminated on one side of the core substrate containing the capacitor, and then a via hole opening and a through hole forming opening are formed in the interlayer resin insulating layer by laser. Then, the laser is irradiated to the opening for forming the through hole with the same laser processing device,
A through hole for a through hole is formed. That is, since alignment is not performed by a separate apparatus and method in the through-hole forming step and the via-hole forming step, the position error due to the apparatus and the construction method is reduced in the through-hole forming step and the via-hole forming step. Does not occur. Further, since no heat is applied to the substrate between the through-hole forming step and the via-hole forming step, the through-holes and via-holes are formed on the substrate without any displacement of the positioning mark due to contraction or warpage of the substrate. Can be formed. Since there is no displacement of the via hole, the via hole can be accurately connected to the terminal of the capacitor housed in the core substrate. Further, since the opening for forming the via hole and the opening for forming the through hole are formed at the same time, when the through hole is formed in the opening for forming the through hole with a laser, the opening for the via hole and the through hole are formed. Misalignment with the through hole can be reduced. Therefore, it is possible to prevent disconnection or short circuit of the wiring.

According to a fourth aspect, the opening diameter of the through hole is set to 8
It is 0 to 250 μm. If it is less than 80 μm, it becomes difficult to form a conductor layer on the inner wall, and if it exceeds 250 μm, it becomes difficult to increase the density, and the superiority of laser processing over drilling is lost. A desirable range is 100 to 20
0 μm. This range is because the aperture of the laser is stable.

According to a fifth aspect of the present invention, the opening diameter of the via hole is set to 2
It is 5 to 125 μm. If it is less than 25 μm, it will be difficult to connect to the upper wiring, and if it exceeds 125 μm, it will be difficult to achieve high density. A desirable range is 50-1.
00 μm. This range is because the aperture of the laser is stable.

According to the present invention, the capacitor is housed in the recess formed in the core substrate. Thus, since the capacitor is arranged in the core substrate, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. In addition, since a large number of capacitors can be accommodated in the recess, high integration of the capacitors is possible.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIG. The printed wiring board 10 includes a core substrate 30 accommodating a plurality of chip capacitors 20 and a build-up wiring layer 80 formed on the upper surface of the core substrate 30. The build-up wiring layer 80 includes an interlayer resin insulating layer 40 in which the conductor circuit 58 and the via hole 60 are formed,
It comprises a conductor circuit 158 and an interlayer resin insulation layer 140 in which a via hole 160 is formed. Interlayer resin insulation layer 140
A solder resist layer 70 is formed on the upper surface of the core substrate 30 and a solder bump 76U is formed in the via hole 160 through the opening 71U of the solder resist 70 on the upper surface, and the opening of the solder resist 70 on the lower surface is formed. The solder bump 76 is formed in the via hole 160 via the portion 71D.
D is formed. The solder bumps 76U on the upper surface side and the solder bumps 76D on the lower surface of the printed wiring board
It is connected via a through-hole 62 formed at zero. An IC chip is mounted on the upper surface side solder bump 76U, and the lower surface solder bump 76D is connected to the daughter board.

The chip capacitor 20 includes a first electrode 21 and a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes.
A plurality of first conductive films 24 connected to the first electrode 21 side and a plurality of second conductive films 25 connected to the second electrode 22 side are arranged on the dielectric 23.

First terminal 21 and second terminal 22 of chip capacitor 20 are connected to via hole 160 formed in interlayer resin insulation layer 140 via via hole 60 formed in interlayer resin insulation layer 40. You. In the present embodiment, since the capacitor 20 is arranged in the core substrate 30,
The distance between the IC chip (not shown) attached to the solder bumps 76U on the upper surface and the capacitor 20 is reduced, and the loop inductance can be reduced.

Next, a laser processing apparatus for processing the through hole 62 and the via hole 60 of the printed wiring board will be described with reference to FIG. Laser oscillator 18
The light emitted from 1 enters the galvano head 170 via a transfer mask 182 for sharpening the focus on the substrate. The galvano head 170 includes a galvanometer mirror 174X that scans the laser beam in the X direction and a galvanometer mirror 174Y that scans the laser beam in the Y direction.
4Y is driven by control motors 172X, 172Y. The motors 172X and 172Y adjust the angles of the mirrors 174X and 174Y in accordance with a control command from a control device (not shown), and transmit detection signals from a built-in encoder to the control device. .

The laser light is applied to galvanomirrors 174X, 1
Vias 74 </ b> Y are scanned in the X and Y directions, respectively, pass through the f-lock lens 176, and via holes 44 are formed in the multi-piece core substrate 30 via the mask 44. The multi-cavity substrate 30 has X
It is placed on an XY table 90 that moves in the −Y direction. The laser processing apparatus includes a camera 180,
The positioning is performed by imaging the positioning mark on the substrate 30.

Next, the method for manufacturing a printed wiring board according to the first embodiment of the present invention will be described. B. a resin film for an interlayer resin insulation layer; The resin filler will be described.

A. Preparation of Resin Film for Interlayer Resin Insulation Layer Bisphenol A type epoxy resin (Epoxy equivalent 46
9. Yuka Shell Epoxy Epicoat 1001) 30
Parts by weight, 40 parts by weight of a cresol novolak type epoxy resin (epoxy equivalent: 215, Epicron N-673 manufactured by Dainippon Ink and Chemicals, Inc.) Light KA-705
2) 30 parts by weight were dissolved by heating in 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha while stirring, and epoxidized polybutadiene rubber (Denalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) was added thereto.
15 parts by weight, 1.5 parts by weight of a crushed product of 2-phenyl-4,5-bis (hydroxymethyl) imidazole, 2 parts by weight of finely divided silica, and 0.5 part by weight of a silicon-based antifoaming agent are added to the epoxy resin composition. Is prepared. The resulting epoxy resin composition is applied on a 38 μm-thick PET film using a roll coater so that the thickness after drying becomes 50 μm, and then dried at 80 to 120 ° C. for 10 minutes to form an interlayer resin. A resin film for an insulating layer is produced.

B. Preparation of Resin Filler 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., molecular weight: 310, YL983U), silane coupling agent coated on the surface, average particle diameter is 1.6 μm, maximum particle diameter Is less than 15 μm
iO2 spherical particles (CRS 1101-
CE) 170 parts by weight and 1.5 parts by weight of a leveling agent (Perenol S4 manufactured by San Nopco Co.) are placed in a container, and the mixture is stirred and mixed to have a viscosity of 45-4 at 23 ± 1 ° C.
A resin filler of 9 Pa · s is prepared. In addition, as a curing agent, an imidazole curing agent (2E4MZ- manufactured by Shikoku Chemicals Co., Ltd.)
CN) 6.5 parts by weight are used.

Next, a method of manufacturing the printed wiring board described above with reference to FIG. 5 will be described with reference to FIGS.

(1) First, a core substrate 30 made of an insulating resin substrate is used as a starting material (see FIG. 1A). As the core substrate 30, a core material such as glass cloth impregnated with a resin can be used.
R-5, RCC and the like can be suitably used. Next, a concave portion 30a for disposing a capacitor is formed on one surface of the core substrate 30 by counterboring. Here, the recess is provided by counterboring, but the recess may be formed by laminating a resin plate having an opening and a resin plate having no opening. After that, the adhesive material 32 is applied to the recess 30a using a printing machine (see FIG. 1B). At this time, potting may be performed in addition to the application.

(2) Next, a plurality of chip capacitors 20 made of ceramic are placed on the adhesive material 32 in the recesses 30a (see FIG. 1C). By placing a plurality of capacitors 20 in one recess 30a,
0 can be highly integrated. After that, a thermosetting resin is filled between the chip capacitors 20 in the recesses 30a, and is cured by heating to form a resin layer 34 (see FIG. 1D). At this time, as the thermosetting resin, epoxy, phenol, polyimide, and triazine are preferable. This allows
The chip capacitor 20 in the recess 30a can be fixed.

(3) On both surfaces of the substrate 30, a resin film for an interlayer resin insulation layer slightly larger than the substrate 30 prepared in the above A is placed on the substrate 30, and pressure is 4 kgf / cm ² , temperature is 80 ° C., and pressure bonding is performed. After temporarily compressing and cutting under the condition of a time of 10 seconds, the interlayer resin insulating layer 40 is formed by pasting using a vacuum laminator device by the following method (see FIG. 2A). That is, a resin film for an interlayer resin insulating layer is formed on the substrate 30 with a degree of vacuum of 0.5 Torr,
The final press bonding is performed under the conditions of a pressure of 4 kgf / cm ² , a temperature of 80 ° C., and a pressing time of 60 seconds, and then heat curing at 170 ° C. for 30 minutes. The interlayer resin insulating layer is formed by application or pressure bonding of a film. The film is a thermosetting resin, a thermoplastic resin or a composite thereof, as specific examples, an epoxy resin film, an olefin-based film,
A resin composite film of an epoxy resin-phenoxy resin or the like can be used. Further, resin particles, inorganic particles and the like may be blended in the above-mentioned resin. Alternatively, a portion that is hardly soluble in an acid or an oxidizing agent and a portion that is soluble in an acid or an oxidizing agent may be separately provided (in this case, the hardly soluble portion,
Soluble is the difference in the dissolution rate of the same solution, and relatively slow ones are called poorly soluble, and fast ones are called chemical solubility).
However, since the melting point of the interlayer resin insulating layer is 300 ° C. or less, if a temperature exceeding 350 ° C. is applied, the interlayer resin insulating layer is dissolved and carbonized.

(4) Next, the core substrate 30 is placed on the XY table 90 of the laser processing apparatus described above with reference to FIG.
An image is taken at 0 and positioning is performed. Then, a 1.2-mm-thick mask 44 having a through-hole (diameter 1.0 mm) 44a formed thereon is mounted on the interlayer resin insulating layer 40 of the core substrate 30 with reference to the positioning mark. Thereafter, a beam diameter of 4.0 mm, a single mode, and a pulse width of 8.0 are output from a laser oscillator (CO ₂ gas laser having a wavelength of 10.4 μm) 181.
The laser light is irradiated to the interlayer resin insulating layer 40 under the condition of 0 μsec and one shot, and the first terminal 2 of the chip capacitor 20 is irradiated.
1. A via hole opening 42 having a diameter of 80 μm reaching the second terminal 22 is formed (see FIG. 2B). The opening diameter of the via hole opening 42 is desirably 50 to 100 μm. If the thickness is 50 μm or less, it is difficult to connect to the upper wiring, and if it is 100 μm or more, it is difficult to increase the density.

(5) Next, with the core substrate 30 mounted on the XY table 90 of the above-mentioned laser processing apparatus, a through hole (diameter 1.2 mm) 48a is formed with reference to the positioning mark of the core substrate. A 1.2 mm thick mask 48 is placed. A laser beam is emitted from the laser oscillator (CO ₂ gas laser having a wavelength of 10.4 μm) 181 to the interlayer resin insulating layer 40 under the conditions of a beam diameter of 4.0 mm, a single mode, a pulse width of 60.0 μsec, and 12 shots. A through hole 46 having a thickness of 120 μm is formed (see FIG. 2C). In addition, the opening diameter of the through hole 46 for a through hole is desirably 100 to 200 μm. If the thickness is less than 100 μm, it becomes difficult to form a conductor layer, and if it is more than 200 μm, it becomes difficult to increase the density, and the superiority of laser processing over drilling is lost.

In the manufacturing method of the present embodiment, since the alignment is not performed by a separate apparatus and method in the step of forming the through hole 46 for the through hole and the step of forming the opening 42 for the via hole, the through hole 46 for the through hole is not used. And the via hole opening 42 does not cause a position error. Further, since no heat is applied to the substrate between the step of forming the through hole 46 for the through hole and the step of forming the opening 42 for the via hole, the positioning mark does not shift due to contraction or warpage of the substrate.
A through hole 46 for a through hole and an opening 42 for a via hole can be formed in the substrate. Via holes can be accurately connected to the terminals 21 and 22 of the capacitor 20 housed in the core substrate 30, and reliability can be improved.
In addition, there is no displacement between the through hole and the via hole, and it is possible to prevent disconnection, poor connection and short circuit of the wiring.

(6) The substrate 30 in which the opening 42 for the via hole and the through hole 46 for the through hole are formed, is
Immersed in a solution at 80 ° C. containing permanganic acid for 10 minutes,
By dissolving and removing the epoxy resin particles present on the surface of the interlayer resin insulation layer 40, the roughened surface 40α is formed on the surface of the interlayer resin insulation layer 40 including the inner wall of the via hole opening 42 and the through hole 46. (FIG. 2)
(D)).

(7) Next, the substrate 30 after the above processing
Is immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. Further, by applying a palladium catalyst to the surface of the substrate 30 which has been subjected to a surface roughening treatment (roughening depth: 3 μm),
Catalyst nuclei are attached to the surface of the interlayer resin insulating layer 40, the inner wall surfaces of the via hole openings 42, and the through holes 46.

(8) Next, the substrate 30 is immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film 50 having a thickness of 0.6 to 3.0 μm over the roughened surface 40α. (See FIG. 3A). [Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyridyl 40 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless plating conditions] 40 minutes at a liquid temperature of 35 ° C

(9) A commercially available photosensitive dry film is affixed to the electroless copper plating film 50, and a mask is placed thereon.
A plating resist 52 having a thickness of 30 μm is provided by exposing at 0 mJ / cm ² and developing with a 0.8% aqueous solution of sodium carbonate (see FIG. 3B).

(10) Then, the substrate 30 is washed with water at 50 ° C., degreased, washed with water at 25 ° C., further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions, 2
An 0 μm electrolytic copper plating film 54 is formed (see FIG. 3C). [Electroplating aqueous solution] sulfuric acid 2.24 mol / l copper sulfate 0.26 mol / l additive 19.5 ml / l (manufactured by Atotech Japan, Capparaside HL) [electroplating conditions] current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ℃

(11) The plating resist 52 is made of 5% NaO
After removing with H, the electroless plating film 50 under the plating resist 52 is dissolved and removed by etching treatment with a mixed solution of sulfuric acid and hydrogen peroxide, and is composed of the electroless copper plating film 50 and the electrolytic copper plating film 54. A conductor circuit 58 (including the via hole 60) and a through hole 62 having a thickness of 18 μm are formed. Thereafter, the substrate 30 is rinsed with water, acid-degreased, and then soft-etched. Then, an etching solution is sprayed on both surfaces of the substrate 30 to spray the surface of the conductor circuit 58 and the surface of the land 62a of the through hole 62. Thus, a roughened surface 64β is formed on all surfaces of the conductor circuit 58 and the through hole 62 (see FIG. 3D). As an etching solution, an etching solution (Mec etch bond, manufactured by Mec Co.) consisting of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride is used.

(12) After preparing the resin filler described in B above, a layer of the resin filler 66 is formed in the through hole 62 within 24 hours after the preparation by the following method. That is, first, the resin filler 66 is pushed into the through hole 62 using a squeegee, and then dried at 100 ° C. for 20 minutes (see FIG. 4A).

(13) After repeating the above steps (3) and (4), the above steps (6) and (11) are further repeated to form an interlayer resin insulating layer 140 on the substrate.
Then, a conductor circuit 158 (including the via hole 160) is formed (see FIG. 4B).

(14) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was used. Oligomer for imparting properties (molecular weight: 4000) 46.6
7 parts by weight, 80% by weight dissolved in methyl ethyl ketone
Of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., Ltd.
Trade name: Epicoat 1001) 15.0 parts by weight, imidazole hardener (manufactured by Shikoku Chemicals, trade name: 2E4MZ-C)
N) 1.6 parts by weight, a bifunctional acrylic monomer which is a photosensitive monomer (trade name: R604, manufactured by Nippon Kayaku Co., Ltd.) 4.5
Parts by weight, also polyvalent acrylic monomer (manufactured by Kyoei Chemical Co.,
A trade name: 1.5 parts by weight of DPE6A) and 0.71 parts by weight of a dispersion defoaming agent (manufactured by San Nopco, S-65) are placed in a container, stirred and mixed to prepare a mixed composition, and the mixed composition is prepared. Of benzophenone (Kanto Chemical Co., Ltd.) as a photopolymerization initiator and 0.2 part by weight of Michler's ketone (Kanto Chemical Co., Ltd.) as a photosensitizer at 25 ° C. A solder resist composition adjusted to 2.0 Pa · s is obtained. The viscosity was measured with a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) when the rotor No. was 60 rpm. In the case of 4, 6 rpm, the rotor No. Three
According to

(15) Next, the above-mentioned solder resist composition is applied to both sides of the multilayer wiring board in a thickness of 20 μm.
After performing a drying treatment at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm-thick photomask on which a pattern of the solder resist opening is drawn is brought into close contact with the solder resist layer 70 to be 1000 mJ / cm ^2. Exposure with ultraviolet light and development processing with a DMTG solution are performed to form openings 71U and 71D having a diameter of 200 μm. And furthermore, 80
1 hour at 100 ° C, 1 hour at 100 ° C, 1 hour at 120 ° C,
Heat treatment is performed at 50 ° C. for 3 hours to cure the solder resist layer, thereby forming a solder resist layer 70 having openings 71U and 71D and a thickness of 20 μm (see FIG. 4C). . As the solder resist composition, a commercially available solder resist composition can be used.

(16) Next, the substrate on which the solder resist layer 70 has been formed is coated with nickel chloride (2.3 × 10 ^-1 mol).
/ L), sodium hypophosphite (2.8 × 10 ^-1 mol)
/ L), sodium citrate (1.6 × 10 ^-1 mol /
2) in the electroless nickel plating solution having pH = 4.5 containing l)
By immersing for 0 minute, a nickel plating layer 72 having a thickness of 5 μm is formed in the openings 71U and 71D. Furthermore, the substrate gold potassium cyanide ^{(7.6 × 10 -3 mol / l} ), ammonium chloride ^{(1.9 × 10 -1 mol / l} ), sodium citrate (1.2 × 10 ^-1 mol / l), immersed in an electroless gold plating solution containing sodium hypophosphite (1.7 × 10 ^-1 mol / l) at 80 ° C. for 7.5 minutes to form a layer having a thickness of A gold plating layer 74 of 0.03 μm is formed (see FIG. 4D).

(17) Thereafter, a solder paste containing tin-lead is printed on the opening 71U of the solder resist 70 on the surface of the substrate on which the IC chip is to be mounted, and further on the opening 71D on the other surface. Print a solder paste containing tin-antimony. Thereafter, the solder bumps 76U and 76D are formed by reflow at 200 ° C., and the printed wiring board 10 is completed (see FIG. 5).

(Second Embodiment) The printed wiring board of the second embodiment is almost the same as the first embodiment. However, the second
In the embodiment, when forming the via hole opening 42 in the interlayer resin insulating layer 40, the through hole forming opening 45 is also formed at the same time. By forming an opening 45 for forming a through-hole in the interlayer resin insulating layer 40 in advance, the core substrate 30 is directly irradiated with a laser, and the through-hole 4 for a through-hole is formed.
6 can be formed. The manufacturing process of the second embodiment also includes
Steps (1) to (3) are the same as in the first embodiment. Step (4) and subsequent steps will be described with reference to FIG.

(4) As in the first embodiment, the core substrate 30 is placed on the XY table 90 of the laser processing apparatus, and a positioning mark (not shown) of the core substrate is imaged by the camera 180 and positioned. Then, a 1.2-mm-thick mask 44 having a through-hole (diameter 1.0 mm) 44a formed thereon is mounted on the interlayer resin insulating layer 40 of the core substrate 30 with reference to the positioning mark. After that, the laser transmitter (wavelength 1
0.4 μm CO ₂ gas laser) 181, beam diameter 4.0 mm, single mode, pulse width 8.0 μsec, 1
Under the conditions of the shot, the interlayer resin insulating layer 40 has a diameter of 80 μm.
The via hole opening 42 and the through hole forming opening 45 are formed (see FIG. 7A).

(5) Next, with the core substrate 30 placed on the XY table 90 of the above-mentioned laser processing apparatus, the above-mentioned mask 44 is removed, and the laser oscillator (wavelength 10.
4 μm CO ₂ gas laser) 181 to beam diameter 4.0
Under a condition of mm, single mode, pulse width of 60.0 μsec, and 12 shots, a laser beam is irradiated to the through-hole forming opening 45 of the interlayer resin insulating layer 40 to form a through-hole through hole 46 having a diameter of 120 μm ( FIG. 7 (B)).
Note that the subsequent manufacturing steps are (6) to (1) of the first embodiment.
The description is omitted because it is the same as 7).

In the second embodiment, a via hole forming opening 42 and a through hole forming opening 45 are simultaneously formed using a mask 44. Therefore, when the through-hole 46 is formed in the through-hole forming opening 45 by laser thereafter, the positional deviation between the via-hole opening 42 and the through-hole through-hole 45 is made smaller than in the first embodiment. be able to.

(Third Embodiment) FIG. 8 is a sectional view of a printed wiring board according to a third embodiment of the present invention. This third
The printed wiring board of the embodiment is almost the same as that of the first embodiment. However, in the third embodiment, interlayer resin insulation layers are formed on both surfaces of the substrate.

The configuration of the printed wiring board according to the third embodiment of the present invention will be described. The printed wiring board 10 includes a core substrate 30 containing a plurality of chip capacitors 20.
And the build-up wiring layers 80A and 80B formed on the upper surface of the core substrate 30. Build-up wiring layer 80
A is composed of an interlayer resin insulation layer 40 on which the conductor circuit 58 and the via hole 60 are formed, and an interlayer resin insulation layer 140 on which the conductor circuit 158 and the via hole 160 are formed. The build-up wiring layer 80B includes an interlayer resin insulating layer 140 on which the conductor circuit 158 and the via hole 160 are formed.
Consists of The build-up wiring layer 80A and the build-up wiring layer 80B are connected via a through-hole 62 formed in the core substrate 30. Interlayer resin insulation layer 140
A solder resist layer 70 is formed on the substrate, and through the openings 71U and 71D of the solder resist 70,
Solder bump 7 on conductive circuit 158 and via hole 160
6U and 76D are formed.

(Fourth Embodiment) The method of manufacturing a printed wiring board according to the fourth embodiment is substantially the same as that of the first embodiment.
However, in the fourth embodiment, an olefin resin film is used for the interlayer resin insulating layer 40 instead of the epoxy resin film. In order to use an olefin-based film, in the fourth embodiment, the condition of the CO ₂ gas laser at the time of providing the via hole opening is set to a pulse width of 15.0 μsec and five shots.

(Fifth Embodiment) The method for manufacturing a printed wiring board according to the fifth embodiment is substantially the same as that of the second embodiment.
However, in the fifth embodiment, an olefin-based resin film was used for the interlayer resin insulating layer instead of the epoxy resin film. In order to use an olefin-based film, in the fifth embodiment, the condition of the CO ₂ gas laser when providing the opening for the via hole is set to a pulse width of 15.0 μsec and five shots.

(Sixth Embodiment) The method of manufacturing a printed wiring board according to the sixth embodiment is substantially the same as that of the first embodiment.
However, in the sixth embodiment, an epoxy resin-phenoxy resin composite film is used for the interlayer resin insulating layer instead of the epoxy resin film. In the sixth embodiment, an excimer laser is used as a laser,
At 150 Hz with an energy of 1.0 J
Area masks were placed on each of the opened masks and processed into areas to form via holes with a very small diameter of 25 μm and through holes of 100 μm.

(Seventh Embodiment) The method of manufacturing a printed wiring board according to the seventh embodiment is substantially the same as that of the second embodiment.
However, in the seventh embodiment, a resin composite film of an epoxy resin-phenoxy resin was used for the interlayer resin insulating layer instead of the epoxy resin film. In the seventh embodiment, an excimer laser is used as a laser,
At 150 Hz with an energy of 1.0 J
Area masks were placed on each of the opened masks and processed into areas to form via holes with a very small diameter of 25 μm and through holes of 100 μm.

(Eighth Embodiment) FIG. 9 is a sectional view of a printed wiring board according to an eighth embodiment of the present invention. This 8th
The printed wiring board of the embodiment is almost the same as that of the first embodiment. However, in the eighth embodiment, the lid plating 161 is formed on the top of the through hole 62, and the via hole 160 is formed directly above the through hole 62 via the lid plating 161. Also in the eighth embodiment, similarly to the first embodiment, the laser processing of the via hole 60 of the interlayer resin insulating layer 40 and the laser processing of the through hole 62 are performed in the same step.

[0054]

According to the present invention, as described above, the through hole and the via hole are formed using the same laser processing apparatus. That is, since positioning is not separately performed in the through hole forming step and the via hole forming step, no positional error occurs between the through hole forming step and the via hole forming step. Further, since no heat is applied to the substrate between the through hole forming step and the via hole forming step, the through holes and via holes are formed in the substrate without the positioning marks being displaced by contraction or warpage of the substrate. Can be formed. Since there is no displacement in the via hole, the via hole can be accurately connected to the terminal of the capacitor housed in the core substrate. Since there is no misalignment between the through hole and the via hole, it is possible to prevent disconnection, poor connection and short circuit of the wiring. Further, damage and deterioration of the interlayer resin insulating layer by the laser can be reduced, and the adhesion of the wiring, which is the upper conductive layer, can be improved.

[Brief description of the drawings]

FIGS. 1A, 1B, 1C, and 1D are manufacturing process diagrams of a printed wiring board according to a first embodiment of the present invention.

FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 3A, 3B, 3C, and 3D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 4A, 4B, 4C, and 4D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of the printed wiring board according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a laser processing apparatus used for through-hole and via-hole processing.

FIGS. 7A and 7B are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.

FIG. 8 is a sectional view of a printed wiring board according to a third embodiment of the present invention.

FIG. 9 is a sectional view of a printed wiring board according to an eighth embodiment of the present invention.

FIGS. 10A, 10B, 10C, and 10D are manufacturing process diagrams of a conventional printed wiring board, and FIGS.
(F2) and (F3) are explanatory diagrams of a connection state between a via hole and a capacitor terminal.

[Explanation of symbols]

 REFERENCE SIGNS LIST 20 chip capacitor 21 first terminal 22 second terminal 30 core substrate 30 a capacitor accommodation recess 34 resin layer 40 interlayer resin insulation layer 42 via hole opening 45 through hole formation opening 46 through hole through hole 50 electroless plating film 54 Electroplating film 58 Conductor circuit 60 Via hole 62 Through hole 66 Resin filler 70 Solder resist layer 71U, 71D Opening 72 Nickel plating layer 74 Gold plating layer 76U, 76D Solder bump 80 Build-up wiring layer 144 Interlayer resin insulation layer 158 Conductor circuit 160 via hole

Continued on the front page (72) Inventor Katsutoshi Ito 1-1 Ikagawa-cho, Ibi-gun, Ibi-gun, Gifu F-term in Ogaki-kita Plant (reference) 5E346 AA42 AA43 EE20 FF09 FF10 FF15 FF24 FF45 GG15 HH07 HH31

Claims (6)

[Claims] An interlayer resin insulating layer and a conductive circuit are alternately laminated on a substrate having a built-in capacitor and electrically connected to each other via a through hole, and each conductive layer is connected by a via hole. A method of manufacturing a printed wiring board, comprising: forming the through hole and the via hole by the same laser processing. 2. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (e): (a) a step of incorporating a capacitor in a core substrate; and (b) a step of incorporating a capacitor in the core substrate. Forming the interlayer resin insulating layer; (c) mounting the core substrate on a processing table of a laser processing apparatus, and irradiating the interlayer resin insulating layer with a laser to form a via hole reaching a terminal of the capacitor. (D) before and after the step (c), a through-hole for a through hole is formed in the substrate while being placed on a processing table of the laser processing apparatus used in the step (c). (E) forming a conductive film in the through hole and the opening, and providing a through hole and a via hole. 3. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (e): (a) a step of incorporating a capacitor in a core substrate; and (b) a step of incorporating a capacitor in the core substrate. Forming the interlayer resin insulating layer; (c) mounting the core substrate on a processing table of a laser processing apparatus, and irradiating the interlayer resin insulating layer with a laser to form a via hole reaching a terminal of the capacitor. Providing an opening for forming a through-hole and an opening for forming a through-hole; (d) irradiating a laser to the opening for forming a through-hole while being placed on a processing table of the laser processing apparatus used in the step (c). Forming a through hole for a through hole in the substrate; (e) forming a conductive film in the through hole and the opening, and forming a through hole and a via hole. 4. The through hole has an opening diameter of 80 to 2
The method for producing a printed wiring board according to claim 1, wherein the thickness is 50 μm. 5. An opening diameter of said via hole is 25-1.
The method for manufacturing a printed wiring board according to claim 1, wherein the thickness is 25 μm. 6. The printed wiring board according to claim 1, wherein a plurality of the capacitors are accommodated in one recess formed in the core substrate. Method.