JP2001284520A - Circuit board for semiconductor chip mounting, manufacturing method for the circuit board, circuit board for relay connecting, semiconductor device and connecting structure between the semiconductor devices - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve a trade-off problem which is observed between a requiring of deducing a signal delay caused by a too long wiring which is generated by accompanied by making a high density, a high integration and a high speed operation of a semiconductor device and a requiring of eases for several tests such as burn-in and so on and for repairing. SOLUTION: Circuit patterns 104 and 105 are formed on both upper and lower surfaces of an insulating body 101 and a circuit board 100A is made while connecting electrodes 107 for terminal surface type external input and output by performing dicing under the condition of passing through vias 106 which connects both the circuit patterns. Flip chip bonding of a semiconductor chip 200A with a circuit board 100A is made. When a plurality of semiconductor device 300A and 300A are mounted on a mother board 401, direct connection of the connecting electrodes 107 and 107 for external input and output is made (direct connecting part 404) to connect a semiconductor chip 200A and 200A each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring pattern formed on an insulator and having a connection portion with a semiconductor chip to be mounted on the insulator at an inner end side of the wiring pattern. The present invention relates to a wiring board for mounting a semiconductor chip having a connection portion for input and output with the outside, and a method for manufacturing such a wiring board. Further, the present invention relates to a semiconductor device having a semiconductor chip mounted using such a wiring board. Further, the present invention relates to a connection structure between semiconductor devices in which a plurality of such semiconductor devices are mounted on a mother board and semiconductor chips are connected to each other. More specifically, there is a demand for a reduction in signal delay caused by a large wiring length and various tests such as burn-in and repair (repair), which are caused by high density, high integration, and high speed operation of semiconductor devices. The present invention relates to a technique for solving the problem of a trade-off (a trade-off) between the requirement for ease of use and the requirement for ease of use.

[0002]

2. Description of the Related Art Generally, a semiconductor device has a form in which a semiconductor chip is housed in a package. This is mainly to protect the semiconductor chip.

In recent years, miniaturization of the above-described semiconductor devices has been promoted for miniaturization of electronic equipment. One of the packages in which such miniaturization is performed is a plastic package. This is because a semiconductor chip is mounted on a lead frame punched into a shape in which a semiconductor mounting portion, a signal wiring portion, a power supply wiring portion, and the like are arranged at predetermined positions, and the electrodes of the semiconductor chip are connected to the lead frame with a bonding wire such as Au. The electrodes are electrically connected and packaged with a thermosetting resin such as an epoxy resin.

However, in this plastic package type semiconductor device, the electrical connection is made by a bonding wire, so that the area around the semiconductor mounting portion on the lead frame is
It is necessary to provide a wiring region for performing wire bonding, which inevitably requires a larger area than the semiconductor chip itself, which is an obstacle to miniaturization of the package.

Further, as the operating speed of a semiconductor chip becomes higher, there is an increasing demand for a package for accommodating the semiconductor chip to reduce the signal delay as much as possible. It has been.

Therefore, in order to meet the above-mentioned demand for miniaturization, the electrodes of the semiconductor chip are applied to the electrodes of the semiconductor carrier within a size range of the semiconductor chip itself in a state where the electrodes of the semiconductor chip are opposed to the semiconductor carrier without using a bonding wire. The use of so-called face-down semiconductor devices for connection has been increasing. As described above, a semiconductor device whose package size is almost the size of a semiconductor chip,
This is called a chip size package (CSP). By using such a method, the wiring in the package can be performed with the shortest wiring length, so that the connection distance between the semiconductor chips can inevitably be reduced.

A conventional semiconductor device of the face-down type according to the prior art will be described with reference to FIG. FIG. 19A is a cross-sectional view of a conventional face-down type semiconductor device.

[0008] The semiconductor carrier 50A is provided on the insulating substrate 11.
, A plurality of via electrodes 12 are provided so as to penetrate from the top surface to the bottom surface, and the upper surface electrode 13 is electrically connected to each via electrode 12 on the upper surface of the insulating substrate 11.
However, a bottom electrode 14 is formed on the lower surface. As the insulating substrate 11, there is a substrate obtained by impregnating an epoxy resin using ceramic or glass woven fabric as a core.

The semiconductor chip 50B has a semiconductor chip main body 21 and bumps 23 made of solder, gold, or the like, which are joined to the electrodes 22 exposed on the lower surface thereof.

The bumps 23 of the semiconductor chip 50B are placed on the upper surface electrode 13 of the semiconductor carrier 50A in alignment with each other, are joined via a conductive resin 31, and are further joined by a sealing resin 32 to the semiconductor carrier 50A and the semiconductor chip 50B. Between the semiconductor carriers 50
The reliability of the connection between A and the semiconductor chip 50B is ensured.

The back surface (upper surface) of the semiconductor chip 50B is exposed (bare chip). The bottom electrode 14
Is for mounting on a motherboard.

As described above, in the semiconductor device 50C of the face-down type, the bonding between the semiconductor carrier 50A and the semiconductor chip 50B is performed immediately below the semiconductor chip 50B, that is, the semiconductor chip 50B
Instead of being joined in the area around the semiconductor chip 5
Since the bonding is performed within the area occupied by 0B itself,
The above-described obstacle to miniaturization due to the necessity of the wire bonding portion in the plastic package type semiconductor device is eliminated, and the package size can be further reduced.

Meanwhile, there is a multi-chip module (MCM) technology in which a plurality of semiconductor chips are mounted on one wiring board. An example will be described with reference to FIG.

A wiring electrode 62 is provided on the upper surface of the semiconductor carrier 61.
Are formed, and an electrode pad 63 is formed on the lower surface thereof.
Are formed, and the wiring electrodes 62 and the electrode pads 63 are electrically connected via the via electrodes 64 embedded in the semiconductor carrier 61 in a penetrating state.

The semiconductor chip 70B has, as its components, a semiconductor chip body 71 and bumps 72 such as solder.
OB is mounted on the semiconductor carrier 61 in a face-down manner. That is, the electrodes of the semiconductor chip 70B are electrically connected to the wiring electrodes 62 on the semiconductor carrier 61 via bumps 72 such as solder.
1, the space between the semiconductor carrier 61 and the semiconductor chip body 71 is filled.

Although the specific structure of the semiconductor carrier 61 in this case is omitted from the illustration, the MCM-L using an organic substrate as an insulator is briefly described.
Or MCM-C with multilayer structure using ceramic, or MCM-D with multilayer structure of Cu wiring with multilayer polyimide or silicon oxide for high frequency range or large scale system
Etc. are known.

As described above, the semiconductor device 70C is configured as a multi-chip module. According to this multi-chip module, when a plurality of semiconductor chips 70B, 70B are arranged adjacently on a semiconductor carrier 61 and both semiconductor chips are connected via a wiring pattern 62 on the semiconductor carrier 61, the semiconductor chip is mounted in the module. Thus, the connection distance between the semiconductor chips becomes shorter, and as a result, the signal delay between the semiconductor chips can be reduced.

[0018]

Here, FIG.
A case is considered where a plurality of semiconductor devices 50C as a CSP (chip size package) configured as described in (a) and having the shortest wiring length in the package are mounted on a mother board in a multi-chip manner. In this case, to connect the semiconductor chips 50B in the plurality of semiconductor devices 50C, for example, to connect the CPU and the DRAM,
The connection is made via a wiring pattern formed on the mother substrate.

As described above, when the design for wire bonding is changed to the design for flip chip, the chip size can be reduced, so that the chip cost itself can be reduced and high-density multi-chip mounting can be performed.

However, no matter how high-density multi-chip mounting is possible, it is certain that there is naturally a limit.

Here, two semiconductor chips 50B, 50
Considering the connection distance between B, it is CS
In addition to the wiring length of the wiring on the semiconductor carrier 11 used for P (chip size package),
There is a wiring length of the wiring pattern on the mother board,
There is a wiring length of the via electrode 12 in the semiconductor carrier 11.
The connection distance obtained by adding up these wiring lengths becomes considerably long, which causes a high possibility of causing a signal propagation delay. In particular, when a high-speed CPU is mounted as a semiconductor chip, the signal delay becomes a serious problem.

In the case of the multi-chip module (MCM) shown in FIG. 19B, the connection distance between the semiconductor chips 70B, 70B mounted in the module is reduced, but the plurality of semiconductor chips 70B, 70B, Since the semiconductor chips 70B are integrated as a whole, it is naturally impossible to handle the individual semiconductor chips 70B individually. That is, the versatility in the module unit has been lost, and it is inevitable that the cost will increase accordingly.

Nevertheless, it is generally difficult to obtain a known good die (KGD) that has been tested and the quality level of which has been determined, in a timely and inexpensive manner.

For example, in a multi-chip module on which four semiconductor chips are mounted, if the defect rate of each semiconductor chip is, for example, 5%, the non-defective rate is 95%.
, Which is reduced to 81.5% in total, and about 1/5 is defective. However, since the cost of mounting the semiconductor chip already mounted is high, the scrap cannot be easily scrapped, and the defective chip must be identified and replaced.

In the case of flip-chip mounting, if solder is used as the bump 72 in bonding, removal of a defective chip and mounting or repair of a new semiconductor chip are relatively easy. However, when various tests (such as DC / AC test) and burn-in (such as bump displacement due to temperature rise) are performed on a multi-chip module, it is not easy to specify which semiconductor chip is defective. Absent. For example, a semiconductor chip is a CPU
When the other semiconductor chip is a DRAM, it is difficult to specify whether the defect has occurred in the CPU, the DRAM, or both. As the number of semiconductor chips mounted as a multi-chip module increases, the difficulty of identifying defective chips increases exponentially.

As described above, in the case of a multi-chip module, there is a problem that the yield when modularized is significantly deteriorated depending on the semiconductor chip to be mounted.

As described above, the connection distance for connecting a plurality of semiconductor chips is reduced as much as possible to reduce the signal delay, the handling in a module unit when a multi-chip is formed, and various types of processing including burn-in. The ease of test or repair is in a trade-off relationship. In the past, this was recognized.

The present invention has been made in order to solve the above-mentioned problems, and solves the above-mentioned trade-off relationship and reduces the signal delay by shortening the connection distance for connecting a plurality of semiconductor chips as much as possible. Of advanced semiconductor devices that can meet both the requirements of a single chip and the ease of handling of various modules including burn-in and the ease of various tests and repairs. Is what you do.

[0029]

According to the present invention, there is provided a wiring board having a wiring pattern formed on the surface of an insulator for connecting a semiconductor chip. An external input / output connection electrode is formed on an end face of the insulator in a state of being connected to the wiring pattern. Then, a semiconductor chip is mounted on such a wiring board to form a semiconductor device. Further, in mounting a plurality of the semiconductor devices configured as described above on a mother board, by connecting the external input / output connection electrodes of each of the adjacent semiconductor devices, the wiring length of the connection between the two semiconductor chips is reduced to the mother length. This can be shortened by the amount not passing through the substrate, and can satisfy the demand for reducing a signal delay caused by a long wiring length. In addition, a package for each semiconductor chip can be provided, and inspection or burn-in of such a package alone can be realized, and versatility as a module alone can be secured.

Therefore, according to the present invention, there are two problems (reduction of signal delay due to a long wiring length, various tests such as burn-in, and easy tests and repairs) which have conventionally been considered as a trade-off. Requirements) can be eliminated simultaneously.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be generally described.

The wiring board for mounting a semiconductor chip according to the first invention of the present application is provided on an end face of the insulator in a state of being connected to a wiring pattern formed on the surface of the insulator for connecting the semiconductor chip. The configuration is such that input / output connection electrodes are formed. When a plurality of semiconductor devices configured by mounting semiconductor chips using this wiring board are arranged adjacent to each other and electrical connection between the semiconductor chips is to be performed,
It is possible to connect between the external input / output connection electrodes of both semiconductor devices, and by such a connection, the wiring length of the connection between the two semiconductor chips is shortened by not passing through the mother board, Signal delay can be reduced. In addition, a package for each semiconductor chip can be provided, and inspection or burn-in of such a package alone can be realized, and versatility as a module alone can be secured. That is, it is possible to satisfy both the requirement for reducing the signal delay due to the long wiring length and the requirement for the ease of various tests such as burn-in and repair.

According to a second aspect of the present invention, in the wiring board for mounting a semiconductor chip according to the first aspect, the external input / output connection electrode on the insulator end face is connected to the wiring pattern on the insulator surface. Thus, it is formed by cutting a via provided in a through hole formed in the insulator. Providing a via in a through-hole is generally performed in the field of semiconductor manufacturing, and dicing of an insulator when cutting a via is also commonly performed. In other words, the equipment and instruments necessary for this and the material surface are in place, and its manufacture is relatively easy, so that a wiring board having external input / output connection electrodes on the insulator end face can be manufactured at low cost. Can be provided. In addition, the connection between the semiconductor chips in adjacent semiconductor devices via the external input / output connection electrodes is performed by directly connecting both external input / output connection electrodes via, for example, a precoat solder or a conductive adhesive. It can be realized with a simple joining.

According to a third aspect of the present invention, in the wiring board for mounting a semiconductor chip according to the first aspect, the external input / output connection electrode on the insulator end face is continuous with the wiring pattern on the insulator surface. Thus, it is formed by cutting a tubular conductor plated on the inner peripheral wall surface of a through hole formed in the insulator. In this case, basically, the same operation as the above first invention is exhibited, but in addition, since the connector can be engaged with the cylindrical conductor, the control of the alignment at the time of mounting is easy. It will be.

According to a fourth aspect of the present invention, in the wiring board for mounting a semiconductor chip according to the first to third aspects, the external input / output connection electrodes are arranged in a matrix on the end face of the insulator. It is that there is. this is,
It is a multi-layered insulator, and external input / output connection electrodes are arranged in both the horizontal and vertical directions. However, it goes without saying that the individual external input / output connection electrodes must be separated from each other. Semiconductor chips tend to have more and more pins, but if the number of pins is the same, it is possible to arrange the necessary external input / output connection electrodes in a narrower range. If it is arranged inside, more external input / output connection electrodes can be arranged. Normally, it exhibits sufficient responsiveness to the tendency to increase the number of pins.

In a wiring board for mounting a semiconductor chip according to a fifth aspect of the present invention, in the first aspect, an end face of the insulator on which the external input / output connection electrodes are formed is an inclined end face. That is. The external input / output connection electrode formed on the inclined end face of the insulator has a larger area than the external input / output connection electrode formed on the vertical end face.
Therefore, the bonding area between the two external input / output connection electrodes is large, and the bonding area is also large on the entire inclined end surface of the insulator. Therefore, bonding can be performed more firmly, and connection reliability can be improved.

A wiring board for mounting a semiconductor chip according to a sixth aspect of the present invention includes a wiring pattern formed on one surface of an insulator for connecting a semiconductor chip, and a wiring pattern formed on the insulator for mounting on a mother board. A wiring pattern formed on the other surface, and an external input / output connection electrode formed on an end face of the insulator in a state of being connected to both of the wiring patterns. And the connection electrodes for external input / output are formed by transfer of a wiring layer attached to the insulator with pressure bonding to the insulator. It is relatively easy to attach the wiring layer to the insulator and transfer it by crimping.Moreover, it is assumed that the external input / output connection electrodes formed on the insulator end faces have high shape accuracy. Become.

According to a seventh aspect of the present invention, in the wiring board for mounting a semiconductor chip according to the first to sixth aspects, at least one side of the outer shape of the insulator is formed on a step side for positioning. It is that there is. The recessed side of the stepped side of one wiring board is aligned with the protruding side of the stepped side of the other wiring board, and the protruding side of the stepped side of the one wiring board is connected to the other wiring. By positioning the wiring board at the recessed side of the stepped side of the board, the positioning of both wiring boards can be performed extremely easily and with high accuracy.

According to an eighth aspect of the present invention, in the wiring board for mounting a semiconductor chip according to the first to seventh aspects, an inner end of a wiring pattern formed on a surface of an insulator for connecting the semiconductor chip is provided. The arrangement order of the connection lands to the chip electrode pads of the semiconductor chip on the side is the same as the arrangement order of the external input / output connection electrodes or a mirror image relationship. If there is no such arrangement relationship or mirror image relationship in the arrangement order and a plurality of wiring patterns are in a random positional relationship within the same plane of the insulator, in order to wire without crossing, where crossing may occur. Must be a crossover. In other words, routes such as vertical connection bodies such as through holes and vias inside them, wiring patterns on the opposite surface, and vertical connection bodies to be restored and wiring patterns on the original surface are necessarily required for routing the wiring pattern. Become. But,
If the arrangement order is the same relation or mirror image relation, a vertical connector is not necessarily required in the routing of the wiring pattern, and the wiring is completed only in the same plane. Therefore, it is possible to promote the reduction of the wiring length of the wiring pattern.

According to a ninth aspect of the present invention, in the wiring board for mounting a semiconductor chip, the wiring pattern formed on the surface of the insulator for connecting the semiconductor chip extends beyond the underfill region of the sealing resin. It extends to the edge or the vicinity of the edge, and the extended portion is configured as an external input / output connection electrode. When the external input / output connection electrode is formed on the end face of the insulator, it is necessary to perform cutting simultaneously with dicing, but such work requires a certain degree of accuracy or more. On the other hand, in the case of the present invention, the insulator is extended in the surface direction, the wiring pattern is also extended, and the extended portion is used as an external input / output connection electrode. This eliminates the need for machining, and allows normal dicing. In addition, since the external input / output connection electrodes are formed on the surface of the insulator, the formation itself becomes easier. However, the extension of the insulator increases the area.

According to a tenth aspect of the present invention, in the wiring board for mounting a semiconductor chip according to the first to fourth aspects, an external input / output connection electrode formed on an end face of the insulator for connection to a semiconductor chip is provided. Are formed in a concave shape, and the other side portions of the insulator are formed with positioning concave portions having substantially the same size and the same arrangement as the concave external input / output connection electrodes. It is. In this case, the connector can be engaged with the recessed external input / output connection electrode, and the connector can also be engaged with the positioning recesses of the other sides, and as a whole, when mounting, The control of the alignment becomes very easy.

According to an eleventh aspect of the present invention, there is provided a wiring board for relay connection, wherein the wiring board for relay connection is arranged in parallel with the wiring board of the tenth aspect. The wiring pattern for relay connection formed on the surface of the insulator is formed on the end face of at least two sides of the insulator in a state of being connected to the wiring pattern for relay connection. The positioning recesses are formed in substantially the same size and the same arrangement as the external input / output connection electrodes. This describes a wiring board for relay connection used in combination with a wiring board for mounting a semiconductor chip in the case of the tenth invention. That is, a plurality of types of wiring boards are standardized as modules, and various combinations can be freely developed by combining these modules, and the degree of freedom of connection between a plurality of semiconductor devices can be increased.

The twelfth aspect of the present invention is directed to a semiconductor device, and uses the wiring board for mounting a semiconductor chip according to any of the first to tenth aspects to connect to the wiring pattern on the wiring board. In this configuration, a semiconductor chip is mounted on the wiring board. In this semiconductor device, when a plurality of the semiconductor devices are arranged adjacent to each other and the semiconductor chips are to be electrically connected to each other, it is possible to connect the external input / output connection electrodes of both semiconductor devices. By connecting, the wiring length of the connection between the two semiconductor chips becomes shorter by not passing through the mother board, and it is possible to reduce the signal delay. In addition, a package for each semiconductor chip is possible,
Inspection, burn-in, etc. of such a package alone can be realized, and versatility as a module alone can be secured. That is, it is possible to satisfy both the requirement for reducing the signal delay due to the long wiring length and the requirement for the ease of various tests such as burn-in and repair.

A thirteenth invention of the present application relates to a connection structure between semiconductor devices, wherein a plurality of semiconductor devices each having a semiconductor chip mounted on an insulator are mounted on a mother board, and the semiconductor device in each of the semiconductor devices described above is mounted. A structure for connecting semiconductor chips to each other, wherein each of the semiconductor devices includes an end face of the insulator connected to a wiring pattern formed on a surface of the insulator for connecting the semiconductor chip. A semiconductor device having external input / output connection electrodes formed thereon is used, and the external input / output connection electrodes of adjacent semiconductor devices are directly joined to each other. According to this, not only the function of the thirteenth invention is basically exerted, but also the connection between the semiconductor chips in the adjacent semiconductor devices via the external input / output connection electrodes is performed by the external input / output connection electrodes. The electrodes can be realized by direct bonding via, for example, a precoat solder or a conductive adhesive, and the above-described signal delay can be prevented without increasing the area or suppressing the increase in the area. It is possible to produce a great advantage of reduction.

According to a fourteenth aspect of the present invention, in the thirteenth aspect, each of the semiconductor devices uses the second, fourth to eighth wiring boards as its wiring board. It has become something. While exhibiting the advantages of each wiring board, there is a demand for reduction of signal delay caused by a long wiring length and burn-in, which are caused by high density, high integration and high speed operation of semiconductor devices. Of the various tests and the ease of repair (repair) that can be solved.

In the fifteenth aspect of the present invention, the semiconductor device connection structure comprises mounting a plurality of semiconductor devices each having a semiconductor chip mounted on an insulator on a mother board and connecting the semiconductor chips in each of the semiconductor devices. In each of the semiconductor devices, a wiring pattern formed on a surface of the insulator for connecting the semiconductor chip extends beyond an underfill region of a sealing resin or an edge of the insulator. A semiconductor device, which is extended to near the edge, and whose extended portion is configured as an external input / output connection electrode, connects the external input / output connection electrodes of adjacent semiconductor devices to each other with a connection wiring board. It is configured to be connected via a. Compared with the butt connection between the external input / output connection electrodes on the insulator end face, the external input / output connection electrodes are both on the insulator surface, and the connection wiring board is bridged between them as a bridge, Since the connection is made in a surface contact with a sufficient contact area, the workability of the connection is good and the joining strength is high. Of course, it is possible to satisfy both the requirement for reducing the signal delay due to the long wiring length and the requirement for the ease of various tests such as burn-in and repair (repair).

A connection structure between semiconductor devices according to a sixteenth aspect of the present invention is the semiconductor device according to the fifteenth aspect, wherein each of the semiconductor devices uses the wiring substrate according to the ninth aspect as its wiring substrate. . This corresponds to a more specific description of the fifteenth invention, and the above-mentioned effect is exerted.

The connection structure between semiconductor devices according to the seventeenth aspect of the present invention is such that a plurality of semiconductor devices each having a semiconductor chip mounted on an insulator are mounted on a motherboard and the semiconductor chips in each of the semiconductor devices are connected to each other. Wherein each of the semiconductor devices is connected to a wiring pattern formed on the surface of the insulator in order to connect the semiconductor chip. Using a semiconductor device having connection electrodes formed thereon,
The external input / output connection electrodes of the adjacent semiconductor devices are connected to each other via a connector which is in common contact with these external input / output connection electrodes and simultaneously performs positioning. It is possible to satisfy both the requirement for signal delay reduction due to the long wiring length and the ease of various tests such as burn-in and the ease of repair (repair). At the same time, the positioning of the mounting is easily controlled.

The connection structure between semiconductor devices according to an eighteenth aspect of the present invention is the semiconductor device according to the seventeenth aspect, wherein each of the semiconductor devices uses the wiring substrate according to the third aspect as its wiring substrate. This corresponds to a more specific description of the seventeenth invention, and the above effects are exerted.

In the eighteenth aspect, the connector may be erected from the mother board, or may be separated from the mother board.

According to the twenty-first connection structure of the present invention, a plurality of semiconductor devices each having a semiconductor chip mounted on an insulator are mounted on a mother board, and the semiconductor chips in each of the semiconductor devices are connected to each other. It has the following configuration requirements. That is, as each of the semiconductor devices, an external input / output connection electrode formed on an end face of the insulator for connecting the semiconductor chip is formed in a concave shape, and on another side of the insulator. A semiconductor device having substantially the same size as the recessed external input / output connection electrodes and the same arrangement of recesses for positioning is used. Further, as a wiring board for relay connection between the plurality of semiconductor devices, a wiring pattern for relay connection formed on the surface of the insulator is formed and connected to the wiring pattern for relay connection. In this state, a wiring board for relay connection, in which at least two sides of the insulator are formed with positioning recesses having substantially the same size and the same arrangement as the external input / output connection electrodes in the semiconductor device, Use. A connector that contacts the external input / output connection electrodes of the semiconductor device and the external input / output connection electrodes of the relay connection wiring board in common to these external input / output connection electrodes and performs positioning simultaneously. Connect through. This corresponds to the tenth and eleventh aspects of the present invention, in which a plurality of types of wiring boards are module-standardized, and various developments can be freely performed by combining these modules. The degree of freedom in connection between a plurality of semiconductor devices can be increased.

The method of manufacturing a wiring board according to the twenty-second aspect of the present invention includes a step of forming a through hole in the insulator, a step of filling the through hole with a conductive paste, and a step of forming the through hole on both upper and lower surfaces of the insulator. A step of forming a wiring pattern in a state connected to the conductive paste and baking the conductive paste into a via, and performing dicing in a state of passing through a via group located at a position corresponding to an outer peripheral portion to cut a cut end surface of the via Forming a connection electrode for external input / output in an exposed state. Although this corresponds to the wiring board for mounting a semiconductor chip according to the second aspect of the invention, it is suitable for manufacturing the wiring board, and the wiring board can be easily manufactured.

The method for manufacturing a wiring board according to the twenty-third aspect of the present invention includes a step of forming a through-hole in the insulator, a step of filling the through-hole with a conductive paste, and a step of forming the through-hole on both upper and lower surfaces of the insulator. A step of forming a wiring pattern in a state connected to the conductive paste and firing the conductive paste to form vias; a step of laminating a plurality of wiring boards obtained as a result of each of the steps; Dicing in a state of passing through a group of vias arranged in a matrix to form a cut end surface of the via in an exposed state to form a matrix-like external input / output connection electrode. This corresponds to the wiring board for mounting a semiconductor chip of the fourth invention,
This is suitable for manufacturing the wiring board, and the wiring board can be easily manufactured.

The method of manufacturing a wiring board according to the twenty-fourth aspect of the present invention includes a step of forming a conductor foil on both upper and lower surfaces of an insulator; a step of forming through holes in the insulator and the conductor foil; A step of forming a cylindrical conductor on the inner peripheral wall surface of the hole so as to be continuous with the two conductor foils; a step of patterning both conductor foils on the insulator surface to form a wiring pattern; Dicing in a state of passing through the cylindrical conductor group to form a cut end surface of the cylindrical conductor as an exposed external input / output connection electrode. Although this corresponds to the wiring board for mounting a semiconductor chip according to the third aspect of the present invention, it is suitable for manufacturing the wiring board, and the wiring board can be easily manufactured.

In the method for manufacturing a wiring board according to the twenty-fifth aspect of the present invention, a step of superposing an insulator on a support substrate on which a wiring layer of a predetermined pattern is formed, Forming a wiring pattern on the surface of the insulator by simultaneously transferring the wiring layer to the contact surface and the end face of the insulator by pressure bonding, and removing the supporting base material while leaving the wiring layer. And exposing a connection electrode for external input / output to an end face of the insulator. This corresponds to the wiring board for mounting a semiconductor chip according to the sixth aspect, but is suitable for manufacturing the wiring board, and the wiring board can be easily manufactured.

The method of manufacturing a wiring board according to the twenty-sixth aspect of the present invention includes a step of laminating and bonding an insulator and a supporting base material, and forming a V-shaped groove in the insulator to form an end face of the insulator. Forming an inclined surface; forming a wiring pattern on the surface and the inclined surface of the insulator; removing the support base and dividing the insulator to form an external input / output on the inclined surface of the insulator. And a step of forming a connection electrode. This corresponds to the wiring board for mounting a semiconductor chip according to the fifth aspect, but is suitable for manufacturing the wiring board, and the wiring board can be easily manufactured.

(Specific Embodiment) Hereinafter, specific embodiments of a wiring board for mounting a semiconductor chip, a method of manufacturing a wiring board, a semiconductor device, and a connection structure between semiconductor devices according to the present invention will be described with reference to the drawings. This will be described in detail.

(Embodiment 1) FIG. 1 is a process sectional view schematically showing a method of manufacturing a wiring board used for a semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is a process schematically showing a method of manufacturing a semiconductor device. FIG. 3A is a cross-sectional view, FIG. 3A is a plan view schematically showing the configuration of the semiconductor device, FIG. 3B is a side view showing the end face type external input / output connection electrodes in the semiconductor device, and FIG. 4A is a cross-sectional view schematically showing a connection structure between semiconductor devices, and FIG. 4B is a plan view schematically showing a connection structure between semiconductor devices.

First, a method for manufacturing a wiring board used for a semiconductor device will be described. FIG. 1 schematically shows the manufacturing method.
In the figure, 100A is a wiring board, 101 is an insulator, 102 is a through hole formed in the insulator 101, 103
Denotes a conductive paste filled in the through hole 102, 104,
Reference numeral 105 denotes a wiring pattern formed on the upper and lower surfaces of the insulator 101, 106 denotes a via formed by sintering the conductive paste 103, and 106a denotes an end of the via 106, and the end is exposed by cutting. The exposed end face vias 104a and 105a
The exposed wiring pattern end face which is located at the end face and which is exposed by cutting out of the end faces 4, 105, 107 is an end face type external input / output composed of upper and lower exposed wiring pattern end faces 104a, 105a and an end face exposed via 106a therebetween. Connection electrode.

Next, a method of manufacturing the wiring board 100A shown in FIG. 1 will be described step by step.

First, as shown in FIG.
A through hole 102 penetrating vertically is formed at a required position 01. As the insulator 101, for example, a ceramic green sheet is used. The formation of the through hole 102 is performed by punching with a metal pin or the like.

Next, as shown in FIG.
02 is filled with a conductive paste 103. As the conductive paste 103, for example, a conductive paste containing copper oxide as a main component is used.

Next, as shown in FIG.
01 on both upper and lower surfaces.
05 is formed. Upper and lower wiring patterns 104 and 105
Are formed in a state where they are electrically connected via the conductive paste 103. The wiring patterns 104 and 105 can be formed by using, for example, a paste containing copper oxide as a main component and printing the paste.

Since the ceramic green sheet as the insulator 101 has a property of shrinking after sintering, the positions of the through hole 102 and the wiring patterns 104 and 105 are determined in advance in consideration of the shrinkage rate.

Next, baking is performed in air at 500 ° C. for about 2 hours to sufficiently remove the organic components in the ceramic green sheet as the insulator 101. Further, firing is performed at 900 ° C. for about 1 hour in a gas atmosphere in which hydrogen and nitrogen are mixed, and the ceramic green sheet from which the organic components have been removed is sintered to form a ceramic layer and a wiring pattern. The copper oxide constituting 104 and 105 is reduced to copper and simultaneously sintered to form a conductor layer.

In this firing, the conductive paste 103 in the through hole 102 is sintered to form a via 106.

Next, as shown in FIG.
01, the via 106 in the through hole 102 at a position corresponding to the rectangular peripheral portion of the wiring board 100A to be cut out.
Is cut in the vertical direction while passing substantially through the center. As a result, the end face exposure via 106a is formed. In the cutting for forming the end face exposed via 106a, the upper and lower wiring patterns 104 and 105 corresponding to the position of the end face exposed via 106a are also cut. The cut end faces of the wiring patterns 104 and 105 are exposed end faces 104 of the wiring pattern.
a and 105a. This exposed wiring pattern end face 104
An external input / output connection electrode 107 of an end face type is formed from the end faces a and 105a and the end face exposed via 106a therebetween. Note that the above-described cutting is so-called dicing, and the plurality of wiring boards 100A are divided into individual pieces. That is, the division of the individual pieces and the formation of the external input / output connection electrodes 107 are performed simultaneously.

As described above, the wiring board 100A having the end face type external input / output connection electrodes 107 is manufactured.

Although not shown in detail in FIG. 1, the insulator 101 serving as the base of the wiring board 100A has a larger area.
, The plurality of wiring boards 100A are divided into individual pieces.

Next, a method of manufacturing a semiconductor device will be described. In FIG. 2 showing a schematic process cross-sectional view of this manufacturing method, reference numeral 200A is a semiconductor chip, 201 is a semiconductor chip main body, 202 is a bump formed on a chip electrode pad on the lower surface of the semiconductor chip main body 201, and 301 is a sealing. The resin, 300A, is a semiconductor device.

Next, a method of manufacturing the semiconductor device 300A shown in FIG. 2 will be described step by step.

First, as shown in FIGS. 2A and 2B,
The semiconductor chip 200A is connected as a flip chip (FC) to the wiring board 100A. Semiconductor chip 20
Reference numeral 0A indicates that the bump 202 made of solder, gold, or the like is bonded to the input / output chip electrode pad exposed on the lower surface of the semiconductor chip body 201. The bump 202 of the semiconductor chip 200A is connected to the wiring board 100.
The bump 202 is bonded to the wiring pattern 104 by positioning and mounting it on the connection land portion of the wiring pattern 104 on the upper surface in A, and performing heating, ultrasonic irradiation, and the like. As a result, the semiconductor chip 200A and the wiring board 100A are electrically connected.

Next, as shown in FIG. 2C, a sealing resin 301 is filled between the lower surface and the side surface of the semiconductor chip 200A and the upper surface of the wiring board 100A, and the sealing resin 301 is filled.
By solidifying the semiconductor device 3, the semiconductor chip 200 A and the wiring substrate 100 A are mechanically and firmly connected to each other, and the semiconductor device 3
00A is obtained. This ensures that the connection reliability between the semiconductor chip 200A and the wiring board 100A is high. As the sealing resin 301, for example, epoxy resin and S
A sealing resin which is a mixture with a filler composed of iO ₂ or the like can be used. The back surface of the semiconductor chip 200A is not covered with the sealing resin 301, and remains exposed.

FIG. 3A is a schematic plan view of the semiconductor device 300A manufactured as described above, and FIG. 3B is a partial side view of the semiconductor device 300A seen from the AA 'direction in FIG. 3A. FIG. 13 is a diagram showing an end face type external input / output connection electrode 107.
Is highlighted.

At the periphery of the semiconductor device 300A, that is, at the periphery of the insulator 101, a large number of external input / output connection electrodes 107 are formed so as to be exposed at the end faces. In the first embodiment, unlike the matrix arrangement of a second embodiment (FIG. 8) described later, a one-dimensional arrangement is used.

Next, a connection structure between semiconductor devices in which a plurality of semiconductor devices are mounted on a mother board will be described. FIG. 4A showing a schematic cross-sectional view of the connection structure between semiconductor devices.
4B showing a plan view, and reference numeral 401 in FIG.
Denotes a mother substrate, 402 denotes an electrode terminal formed on the mother substrate 401, 403 denotes a solder, and 404 denotes a direct bonding portion.

The connection structure between semiconductor devices as shown in FIG. 4 is constructed as follows.

First, the two semiconductor devices 300A, 300
A Solder is pre-coated in advance on the end face type external input / output connection electrodes 107 to be connected to each other. This pre-coated solder will directly become the bonding portion 404 later.

Next, the electrode terminals 40 on the motherboard 401
Print cream solder on 2.

Next, the two semiconductor devices 300A, 300
In A, the solder-precoated end-face type external input / output connection electrodes 107, 107 are aligned with each other, and both semiconductor devices 300A, 300A are mounted on the motherboard 401 while maintaining this alignment state. This mounting is performed by the electrode terminals 402 on the mother substrate 401.
Is performed in a state where the electrode pads of the wiring pattern 105 on the lower surfaces of the semiconductor devices 300A and 300A are aligned.

Next, solder reflow is performed. Thereby, the electrode pads of the wiring pattern 105 of the two semiconductor devices 300A and 300A and the electrode terminals 4 of the motherboard 401 are formed.
02 and two semiconductor devices 300A, 300A, 3
End face type external input / output connection electrode 1 between 00A
07 and 107 are connected simultaneously. The solder connection portion between the external input / output connection electrodes 107 and 107 becomes the direct bonding portion 404.

As described above, this connection structure between semiconductor devices has an external input / output connection electrode 107 of an end surface type.
Are mounted adjacent to each other on the mother board 401 in a state where the two external input / output connection electrodes 107 are directly connected to each other.

The semiconductor chips 200A, 300A of the adjacent semiconductor devices 300A, 300A according to the first embodiment
In connection between 200A, mother board 401
The connection distance is not shown in FIG.
Compared with the case of the related art in which connection is made via the mother substrate shown in FIG. 1A, the wiring length on the mother substrate is reduced and the wiring length of two vias in the semiconductor carrier is reduced. The number of connections has been reduced, and connection with shorter wiring is possible.

Therefore, it is possible to reduce the connection distance as much as the multi-chip module. Moreover, in each semiconductor device 300A, the semiconductor chip 20
Since each of the devices 0A is packaged, it is possible to perform inspection, burn-in, and the like using such a package alone, and as a result, there is no loss of versatility of the semiconductor device to be connected.

In the first embodiment, the method of manufacturing the wiring board 100A and the semiconductor device 300A using the ceramic obtained by sintering the green sheet as the insulator 101 has been described. However, the present invention is not necessarily limited to this. ALIVH using resin as the insulator 101
(Any Layer Inner Via Hole) A substrate may be used, and in this case, similarly to the above, a semiconductor device 300A in which an end face type external input / output connection electrode 107 is formed on the end face of the insulator 101 can be manufactured. It is. For the ALIVH substrate, Japanese Patent No. 2601128 can be referred to.

The requirements for minimizing the wiring pattern in the semiconductor device will be described with reference to FIG.

FIG. 5 is a plan view showing the concept of the arrangement order relationship between the chip electrode pads 203 of the semiconductor chip 200A and the end face type external input / output connection electrodes 107 in the semiconductor device 300A.

Assuming that the face-down method is used as the mounting method of the chip electrode pads 203, the arrangement order of the chip electrode pads 203 of the semiconductor chip 200A and the external input / output connection electrodes 1 on the end face of the insulator 101 are assumed.
The arrangement order of 07 has a mirror image relationship. It is not necessary to use a vertical connector such as a via in the routing of the wiring pattern 104, that is, there is no need for a three-dimensional intersection, and all the wiring patterns can be routed in the same plane, and the shortest wiring is possible. It is. Of course, if conditions permit, the same relationship may be used instead of the mirror image relationship. The mirror image relationship means that the pitch of the external input / output connection electrodes is wider than the pitch of the chip electrode pads, and the same relationship means that the pitches are equal.

Although the above description has been made with respect to the face-down method, in addition to the above, when the wire bonding method is used for mounting the semiconductor chip, the arrangement order of the chip electrode pads formed on the semiconductor chip and the end surface It is preferable that the arrangement order of the type external input / output connection electrodes 107 be a mirror image relationship.

(Embodiment 2) FIG. 6 is a process sectional view schematically showing a method of manufacturing a wiring board used in a semiconductor device according to a second embodiment of the present invention, and FIG. 7 is a process schematically showing a method of manufacturing a semiconductor device. FIG. 8A is a cross-sectional view, FIG. 8A is a plan view schematically showing the configuration of the semiconductor device, FIG. 8B is a side view showing the end face type external input / output connection electrodes in the semiconductor device, and FIG. 1 is a sectional view schematically showing a connection structure between semiconductor devices.

First, a method for manufacturing a wiring board used for a semiconductor device will be described. FIG. 6 schematically showing this manufacturing method.
In the figure, 100B is a wiring board, 101 is an insulator, 102 is a through hole formed in the insulator 101, 103
Denotes a conductive paste filled in the through hole 102, 104,
Reference numeral 105 denotes a wiring pattern formed on the upper and lower surfaces of the insulator 101, 106 denotes a via formed by sintering the conductive paste 103, and 106a denotes an end of the via 106, and the end is exposed by cutting. The exposed end face vias 104a and 105a
4, 105, the end face of the exposed wiring pattern, which is located on the end face and is exposed by cutting.
08 denotes upper and lower exposed wiring pattern end faces 104a and 105a.
And an external input / output connection electrode of an end face type having a two-tiered arrangement composed of an end face exposed via 106a between the two.

Next, a method of manufacturing the wiring board 100B shown in FIG. 6 will be described step by step.

6 (a) to 6 (c) are the same as those described in FIGS. 1 (a) to 1 (c) in the first embodiment. Briefly, first, as shown in FIG. 6A, a through hole 102 is formed at a required position of an insulator 101, and then, as shown in FIG. The conductive paste 103 is filled, and then, as shown in FIG. 6C, wiring patterns 104 and 105 are formed on both upper and lower surfaces of the insulator 101.
It is formed in a state of being electrically connected to each other via the conductive paste 103.

Next, as shown in FIGS. 6D and 6E,
A plurality of insulators 101 manufactured by repeating the above process are stacked and pressed. At this time, the external input / output connection electrodes 107 and 108 of the end-face type of the two-tiered arrangement are arranged so that they are not electrically connected to each other. That is, the insulation is maintained between the uppermost layer and the lowermost layer via the intermediate layer.

Next, baking is performed in air at 500 ° C. for about 2 hours to sufficiently remove the organic components in the ceramic green sheet as the multilayer insulator 101. Further, in a gas atmosphere in which hydrogen and nitrogen are mixed, 90
Baking is performed at 0 ° C. for about 1 hour to sinter the ceramic green sheet from which the organic components have been removed, thereby forming a ceramic layer and forming wiring patterns 104 and 105.
Is reduced to copper and sintered at the same time to form a conductor layer.

In this firing, the conductive paste 103 in the through-hole 102 is sintered to form a via 106.

Next, as shown in FIG.
01 wiring board 100B to be cut from the laminate
Upper and lower through holes 10 at positions corresponding to the rectangular peripheral portion of
The vias 106, 106 in the components 2, 102 are cut in the vertical direction while substantially passing through the center. As a result, end face exposed vias 106a, 106a are formed. In the cutting for forming the end face exposed vias 106a, 106a, the upper and lower wiring patterns 104, 105... Corresponding to the end face exposed vias 106a, 106a are also cut. Such a wiring pattern 104,
Are cut end faces 104a, 105a,... Then, the external input / output connection electrode 107 of the upper end type is formed from the exposed wiring pattern end surfaces 104a, 105a on the upper layer side and the end surface exposed via 106a therebetween, and the lower-layer exposed wiring pattern end surfaces 104a, 105a are formed. End face exposed via 10 between
6a and lower end face type external input / output connection electrode 1
08 will be formed. The above-mentioned cutting is so-called dicing.

As described above, the wiring board 100B having the external input / output connection electrodes 107 and 108 of the end face type arranged in the upper and lower two stages is manufactured.

Although not shown in detail in FIG. 1, the insulator laminate that forms the basis of the wiring board 100B has a larger area, and a plurality of wiring boards 100B are formed from such an insulator laminate. Is divided into individual pieces.

Next, a method of manufacturing a semiconductor device will be described. In FIG. 7 showing a schematic process cross-sectional view of this manufacturing method, reference numeral 200A is a semiconductor chip, 201 is a semiconductor chip body, 202 is a bump formed on the lower surface of the semiconductor chip body 201, 301 is a sealing resin, and 300B is It is a semiconductor device.

Next, a method of manufacturing the semiconductor device 300B shown in FIG. 7 will be described step by step.

First, as shown in FIGS. 7A and 7B,
The semiconductor chip 200A is connected to the wiring board 100B. The semiconductor chip 200A is the semiconductor chip body 20.
A bump 202 made of solder, gold, or the like is bonded to an input / output chip electrode pad exposed on the lower surface of the device 1. The bump 202 of the semiconductor chip 200A is aligned with the wiring pattern 104 on the upper surface of the wiring board 100B and placed thereon, and heating and ultrasonic irradiation are performed, so that the bump 202 is moved to the wiring pattern 1.
04. Thus, the semiconductor chip 200A and the wiring board 100B are electrically connected.

Next, as shown in FIG. 7C, a sealing resin 301 is filled between the lower surface and the side surface of the semiconductor chip 200A and the upper surface of the wiring board 100B, and the sealing resin
By solidifying 1, the semiconductor chip 200A and the wiring board 100B are mechanically and firmly connected. Thereby, the connection reliability between the semiconductor chip 200A and the wiring board 100B is ensured to be high. As the sealing resin 301, for example, a sealing resin that is a mixture of an epoxy resin and a filler made of SiO ₂ or the like can be used.

FIG. 8A is a schematic plan view of the semiconductor device 300B manufactured as described above, and FIG. 8B is a side view of a part of the semiconductor device 300B seen from the direction BB 'in FIG. 8A. In the drawing, the end face type external input / output connection electrodes 107 and 108 in a two-tiered arrangement are shown in an emphasized manner.

At the peripheral portion of the semiconductor device 300B, that is, at the peripheral portion of the insulator laminate, a large number of external input / output connection electrodes 107 and 108 of a two-stage arrangement are arranged in a matrix in a state of being exposed on the end surface. It is formed in a dense state.

In the semiconductor device 300B of the second embodiment, the external input / output connection electrodes 107, 1 of the end face type are used.
08 is a two-tiered matrix,
The number of external input / output connection electrodes can be doubled as compared with the case of the one-dimensional development of the first embodiment, which is a one-stage arrangement of end face type external input / output connection electrodes 107 only. . That is, it is possible to cope with the increase in the number of pins of the semiconductor chip 200A.

Note that the number of end face type external input / output connection electrodes need not necessarily be limited to two, but may be three or more.

Next, a connection structure between semiconductor devices for assembling a plurality of semiconductor devices on a mother substrate will be described. In FIG. 9 showing a schematic cross-sectional view of the connection structure between semiconductor devices, reference numeral 401 denotes a mother board, 402 denotes electrode terminals formed on the mother board 401, 403 denotes solder,
4,405 is a direct joining part.

A connection structure between semiconductor devices as shown in FIG. 9 is constructed as follows.

First, two semiconductor devices 300B and 300B
B. Solder is pre-coated on the upper and lower external input / output connection electrodes 107, 107 and the lower external input / output connection electrodes 108, 108 of the end face type to be connected to each other. This pre-coated solder will directly become the joints 404 and 405 later.

Next, the electrode terminals 40 on the mother substrate 401
Print cream solder on 2.

Next, the two semiconductor devices 300B and 300
In B, the upper-level external input / output connection electrodes 107, 107 are aligned with each other and the lower-level external input / output connection electrodes 108, 108 are aligned with each other, and the alignment state is maintained. The semiconductor devices 300B and 300B are placed on the motherboard 401 while keeping the state. This mounting is performed by the mother substrate 40.
1, the two semiconductor devices 300B,
This is performed in a state where the electrode pads of the wiring pattern 105 on the lower surface of the 300B are aligned.

Next, solder reflow is performed. Thereby, the electrode pads of the wiring pattern 105 of the two semiconductor devices 300B and 300B and the electrode terminals 4 of the motherboard 401 are formed.
02 and the two semiconductor devices 300B and 300B.
Solder connection between the upper and lower external input / output connection electrodes 107 and 107 and solder connection between the lower external input / output connection electrodes 108 and 108 between the end surfaces of 00B are performed simultaneously. The solder connection portion of the upper external input / output connection electrodes 107, 107 directly serves as a bonding portion 404, and the lower external input / output connection electrodes 108, 107
The solder connection portion 108 becomes the direct bonding portion 405.

As described above, this connection structure between semiconductor devices has an external input / output connection electrode 107 of an end surface type.
The two semiconductor devices 300B having the above structure are connected directly to each other by connecting the upper and lower external input / output connection electrodes 107 and 107 and the lower external input / output connection electrodes 108 and 108 directly to each other. It has a structure in which it is mounted adjacently on 401. In the drawing, the lower external input / output connection electrodes 108 and 108 and the semiconductor chip 200
A and 200A do not appear to be connected, but they are actually connected outside the paper.

The semiconductor chips 200A, 200A,
In connection between 200A, mother board 401
The connection distance is not shown in FIG.
Compared with the case of the related art in which connection is made via the mother substrate shown in FIG. 1A, the wiring length on the mother substrate is reduced and the wiring length of two vias in the semiconductor carrier is reduced. The number of connections has been reduced, and connection with shorter wiring is possible.

Further, the connection distance can be reduced as in the case of the multi-chip module. In addition, since each of the semiconductor chips 200A is packaged in each of the semiconductor devices 300B, it is possible to perform inspection, burn-in, and the like of such a package alone, and as a result, the versatility of the semiconductor device to be connected may be impaired. Absent.

In addition, since the end face type external input / output connection electrodes are arranged in a two-stage matrix, the number of input / output terminals of the semiconductor device is increased as compared with the case of the first embodiment having only one stage. That is, it is possible to effectively cope with the increase in the number of pins.

(Embodiment 3) FIG. 10 is a process sectional view showing an outline of a method of manufacturing a wiring board used for a semiconductor device according to Embodiment 3 of the present invention, and FIG. 11 (a) is an outline of a connection structure between semiconductor devices. FIG.

In FIG. 10, reference numeral 100C denotes a wiring board, 501 denotes an insulator, 502 denotes a wiring pattern formed on the surface of the insulator 501, 503 denotes a support base, 504 denotes an adhesive layer, and 505 denotes a V-shape. Grooves, 506 are wiring patterns, 5
Reference numeral 07 denotes a connection electrode for external input / output of the inclined end surface type, and 550.
Is a dicing blade.

First, as shown in FIG. 10A, an insulator 501 is bonded to a supporting base material 503 via an adhesive layer 504.

In this case, an insulator 501 whose cut surface is flattened by dicing is used. Suitable materials include, for example, alumina and glass ceramic. Insulators made of alumina or glass ceramic have excellent characteristics for high frequencies, but have high hardness, but it is difficult to form through holes. Therefore, the third embodiment is applied.

As the adhesive layer 504, a wax, a foamable sheet, or the like, which loses adhesiveness when heated, is used.

Next, as shown in FIG. 10B, a V-shaped groove 505 is formed by using a dicing blade 550 at a position where the external input / output connection electrode 507 of the inclined surface type is formed. . At this time, depth control is performed so that the deepest part of the V-shaped groove 505 also cuts the adhesive layer 504 and reaches the surface of the support base material 503. This is because the wiring pattern 502 is connected to the wiring pattern 506 formed on the V-shaped groove 505 at the stage of FIG. In addition, as the dicing blade 550, it is preferable to use a blade having an angle of 45 degrees or more with respect to the tip surface in the tip shape.

Next, as shown in FIG. 10C, the surface of the insulator 501 is plated, a mask is formed, and etching is performed to form a wiring pattern 506. At this time, the wiring pattern 50 is also formed on the surface of the V-shaped groove 505.
6 is formed.

Next, as shown in FIG. 10D, the adhesive layer 504 and the supporting substrate 503 are released by heating. In this mold release, separation into two, that is, separation into individual pieces, occurs at the same time due to the presence of the V-shaped groove 505.

As a result, as shown in FIG. 10 (e), the connecting surface connecting the upper surface and the lower surface of the insulator 501 is the inclined end surface 501a.
The wiring substrate 100C in which the external input / output connection electrodes 507 are formed on a is manufactured.

Note the following about the method of illustration. 10 (a) to 10 (d) are different from FIG. 10 (e), but this is done for convenience of expression. 10 (a) to 10 (d) mainly show a rational method of forming the external input / output connection electrode 507 of the inclined end surface type, and thus the V-shaped groove 505 is drawn at the center of the drawing. . However, at each of the right end and the left end, there is a portion extending further outward, and the illustration of that portion is omitted. FIG.
The wiring board 100C shown in FIG. 10E shows the whole of the left piece of the two pieces separated in FIG. 10D.

Next, a connection structure between semiconductor devices in which a plurality of semiconductor devices are mounted on a motherboard will be described. In FIG. 9 showing a schematic cross-sectional view of the connection structure between semiconductor devices, reference numerals 401 indicate a mother substrate, and 402 indicates a mother substrate 4.
01, electrode terminal 403, solder 403,
Is a direct joint.

A connection structure between semiconductor devices as shown in FIG. 11 is constructed as follows.

On the other hand, the left semiconductor device 300C has an inclined end surface 50 of an insulator 501 on its wiring board 100C.
1a has spread downward. In the semiconductor device 300C on the other right side, the inclined end face 501a of the insulator 501 in the wiring board 100C is widened upward. That is, the inclined direction of the external input / output connection electrode 507 in one semiconductor device 300C and the inclined input surface external input / output connection electrode 508 in the other semiconductor device 300C are opposite to each other, and the inclination angles are equal. Has become.

First, two semiconductor devices 300C, 300
C, the externally input / output connection electrode 507 of the downwardly sloping end surface type to be connected to each other and the externally input / output connection electrode 508 of the upwardly sloping end surface type,
Pre-coat the solder. This pre-coated solder will directly become the joint later.

Next, the electrode terminals 40 on the motherboard 401
Print cream solder on 2.

Next, the two semiconductor devices 300C and 300C
In C, the external input / output connection electrodes 507 and 508 of the inclined end surface type having been solder pre-coated are aligned with each other, and both semiconductor devices 300C and 300C are mounted on the mother substrate 401 while maintaining this alignment state. . This mounting is performed on the electrode terminals 4 on the motherboard 401.
02 is performed in a state where the electrode pads of the wiring pattern 105 on the lower surfaces of the semiconductor devices 300C and 300C are aligned.

External input / output connection electrode 5 of inclined end surface type
07 and 508 are compared with the vertical end face type external input / output connection electrode 107 in the first embodiment.
Its area is larger. Therefore,
External input / output connection electrodes 507 and 508 of the inclined end surface type
The bonding area of the direct bonding part between the two is large, and stronger bonding is possible.

In FIG. 11B, for the sake of convenience, the external input / output connection electrode 50 of the inclined end surface type is used.
Although it is drawn so that there is a gap between 7,508, it is of course closely adhered, and it is a direct joint.

The semiconductor chips 200A, 300C of the adjacent semiconductor devices 300C, 300C according to the third embodiment
Even in the connection between 200A, the mother board 401
, As in the first embodiment,
The semiconductor chips 200A, 200A can be connected by short wiring. Further, since each of the semiconductor chips 200A is packaged in each of the semiconductor devices 300C, the inspection, the burn-in and the like of such a single package can be performed.

Further, since the external input / output connection electrodes to be connected to the end surfaces of the semiconductor devices 300C and 300C are inclined end surface type external input / output connection electrodes 507 and 508 whose inclination directions are reversed to each other, both are connected. Has been expanded, and stronger bonding has become possible. That is, a connection structure between semiconductor devices having high connection reliability can be constructed.

(Embodiment 4) Next, a wiring board according to Embodiment 4 of the present invention will be described. FIG. 12 is a process cross-sectional view schematically showing a method of manufacturing a wiring board used for a semiconductor device according to the fourth embodiment.

First, as shown in FIG. 12A, an insulator 601 is prepared, and a support base 602 on which a wiring layer 603 is formed in a predetermined pattern is prepared. As the insulator 601, an insulator having excellent dimensional stability and high heat resistance is used. For example, there is a glass woven fabric impregnated with a thermosetting resin. A preferred example of the thermosetting resin is an epoxy resin, which is a glass epoxy prepreg. Further, a preferable example of the supporting base material 602 is an aluminum foil, and a preferable example of the wiring layer 603 is a copper foil. It is advantageous to use a composite material in which an aluminum foil and a copper foil are bonded in advance.

The insulator 601 is positioned with respect to the wiring layer 603 on the supporting base material 602. In this case, alignment is performed so that both end surfaces 601a of the insulator 601 are located at intermediate positions of the respective wiring layers 603.

Next, as shown in FIG. 12B, the support base 602 and the insulator 601 are pushed into a molding die 650 having a recess 650a in a state of being overlapped. At this time, both ends of the support base material 602 are pushed in while a tensile stress is applied. The size of the recess 650 a of the molding die 650 is larger than the insulator 601 and smaller than the wiring layer 603. By this pushing, the supporting base material 602 is
03 is bent substantially at a right angle, and the wiring layer 603 is pressed against the end face 601a of the insulator 601.

Next, as shown in FIG. 12C, the protruding portion of the support base material 602 is further bent at a right angle by heating and pressing in a vacuum press state using a holding die 651, and the support base is bent. The material 602 and the wiring layer 603 are strongly pressed while being attached to the insulator 601. As a result, the wiring layer 603 moves from the surface of the insulator 601 to the end face 60.
1a, and further, to the back surface, to be pressed and transferred.

Next, as shown in FIG.
After releasing from 50 and 651, the supporting base material 602 is removed. The supporting base material 602 is made of aluminum foil, and the wiring layer 603 is used.
Is a copper foil, the aluminum foil and the supporting base material 602 can be dissolved and removed by selective etching of the aluminum foil and the copper foil. When the support base material 602 is removed by dissolving and removing in this manner, a destructive phenomenon that may occur when the support base material 602 is removed by applying a stress can be reliably suppressed, and a double-sided wiring type having a high shape accuracy and a good surface accuracy can be used. The wiring board 100D can be manufactured. In addition, the support base material 602 can be removed in an integrated line, so that productivity can be improved.

As a selective etching solution in the selective etching of the aluminum foil and the copper foil in the above case, ammonium persulfate or the like can be used. A similar method can be used to form the wiring layer 603 in a predetermined pattern.

The glass epoxy prepreg constituting the insulator 601 is obtained by impregnating a glass woven fabric with an epoxy resin. At the time of the impregnation, the epoxy resin layers are naturally formed on and under the glass woven fabric. Is done. At the time of thermocompression bonding in the case of FIG. 12C, the insulator 601 undergoes compression in the thickness direction and extension in the plane direction at the same time. With the extension in the plane direction, the impregnated epoxy resin flows in the plane direction, and the outer dimensions slightly increase.

As the molding die 650, a die slightly larger than the outer shape of the insulator 601 is used, and the dimensions of the die are determined by the compression ratio in the thickness direction at the time of pressure bonding. With such a contrivance, the wiring layer 6 is formed on the end face 601a of the insulator 601.
It is possible to form the external input / output connection electrode 604 of the end face type made of copper foil formed in a state connected to 03 without deformation such as bending.

(Embodiment 5) FIG. 13 is a cross-sectional view schematically showing a connection structure between semiconductor devices according to a fifth embodiment.

In FIG. 13, reference numeral 100E is a wiring board, 101 is an insulator, 104 and 105 are wiring patterns formed on upper and lower surfaces of the insulator 101, and 106 is filled in a through hole formed in the insulator 101. Vias resulting from sintering conductive paste, 200A semiconductor chip, 201
Is a semiconductor chip body, 202 is a semiconductor chip body 201
Formed on the lower surface of the substrate, 301 is a sealing resin, 300
D is a semiconductor device, 401 is a mother substrate, 402 is an electrode terminal formed on the mother substrate 401, 403 is solder,
Reference numeral 700 denotes a connection wiring board.

For connection between the semiconductor chips 200A, 200A in the two semiconductor devices 300D, 300D, a connection wiring board 700 is used.

In the wiring board 100E of the semiconductor device 300D, the insulator 101 extends beyond the underfill region of the sealing resin 301, and accordingly, the wiring pattern 104 on the insulator 101 also moves outward. Has been extended to. Then, the extension portion 104a of the wiring pattern 104
Is connected to the connection wiring substrate 700.

In this connection wiring board 700, a wiring pattern 702 is formed in a predetermined pattern on a connection base material 701. 703 are joined.

As the connection base material 701, a material having flexibility, excellent dimensional stability, and high heat resistance is used, and preferable examples thereof include polyimide.

The wiring pattern 702 formed on the connection base material 701 is based on a copper foil bonded to polyimide as the connection base material 701, and a mask is formed on the copper foil. Then, a wiring pattern 702 is formed by an etching method or a lift-off method.

A connection structure between semiconductor devices as shown in FIG. 13 is constructed as follows.

First, two semiconductor devices 300D, 300
D: Wiring pattern extension 1 to be connected to each other
The connection conductors 703 and 703 of the connection base material 701 are electrically joined to the substrates 04a and 104a by heating and pressing.

According to the fifth embodiment, the semiconductor chips 200A,
In connection between 200A, mother board 401
The connection distance is not shown in FIG.
Compared with the case of the related art in which connection is made via the mother substrate shown in FIG. 1A, the wiring length on the mother substrate is reduced and the wiring length of two vias in the semiconductor carrier is reduced. The number of connections has been reduced, and connection with shorter wiring is possible.

Therefore, the connection distance can be reduced as in the case of the multi-chip module. Moreover, in each semiconductor device 300D, the semiconductor chip 200
Since each of A is packaged, it is possible to perform inspection, burn-in, and the like using such a package alone, and as a result, there is no loss of versatility of the semiconductor device to be connected.

In the first embodiment, the vias are cut to form the end face type external input / output connection electrodes 107. In the fifth embodiment, however, such cutting is unnecessary, and the connection is not performed. Since the wiring pattern extending portions 104a, 104a on the surfaces of the semiconductor devices 300D, 300D can be connected to each other via the wiring substrate 700, the semiconductor device can be easily manufactured.

(Sixth Embodiment) FIG. 14 is a plan view showing a connection structure between semiconductor devices according to a sixth embodiment.

Two Semiconductor Devices 30 to be Arranged Adjacently
Reference numerals 0E and 300E indicate that the semiconductor chips 200A and 200A are mounted on the wiring boards 100F and 100F.
Each of the wiring boards 100F, 100F has an irregular shape with respect to the rectangle. That is, the wiring boards 100F, 10F
0F indicates that the sides facing each other are steps 1
10,110. The step side portion 110 of each wiring board 100F is a combination of one concave side portion 110a and one projecting side portion 110b. Recessed edge 11
0a and the protruding side portion 110b are connected by a vertical side portion 110c perpendicular to both. The length of the concave side 110a and the length of the protruding side 110b are equal. That is, the concave side 110a of one wiring board 100F is made to correspond to the protruding side 110b of the other wiring board 100F,
At the same time, the projecting side 110b of one wiring board 100F is made to correspond to the recessed side 110a of the other wiring board 100F. In such a relationship, the two semiconductor devices 30
When the wiring boards 100F and 100F of the OE 0300E face each other, the concave side 110a and the protruding side 110b
Corresponding to the above, the distance between the step sides 110, 110 is constant over the entire length. Center vertical side 110
c and 110c come into contact with each other to perform horizontal positioning. The vertical sides 110c, 110
The “vertical” of c does not necessarily need to be considered, and may be an inclined side. in short,
The two wiring boards 100F, 100F may be rotationally symmetric. In order to make such a form, when cutting the wiring boards 100F, 100F from a large original plate into individual pieces using a laser, the steps are not straight in one side but have the steps as described above. This can be realized by scanning the laser with a hook.

In both wiring boards 100F, 100F, semiconductor chips 200A, 200A are mounted in a face-down manner, and wiring patterns 104, 104 are formed toward step sides 110, 110, and step sides 11A are formed.
The external input / output connection electrodes 117, 117 of the end face type are formed on the end faces of 0, 110 in an exposed state, and they are also rotationally symmetric in relation to each other. In particular, the external input / output connection electrode 117 facing the recessed side 110a of one wiring board 100F.
The external input / output connection electrode 117 facing the protruding side 110b of the other wiring board 100F has the same position in the horizontal direction, and similarly, the outside facing the protruding side 110b of the one wiring board 100F. The position of the input / output connection electrode 117 and the position of the external input / output connection electrode 117 facing the recessed side 110a of the other wiring board 100F are the same in the horizontal direction.

Then, the two wiring boards 100F, 100F
As shown in FIG.
The external input / output connection electrodes 117, 117 which face each other in a state where they are engaged with each other and correspond to each other.
All of them are electrically connected via connection conductors 800 such as pre-coated solder or applied conductive adhesive. In the case of precoat solder, reflow may be performed.

Although the shape of the step sides 110, 110 has been described above as being rotationally symmetric, it is not necessary to be limited to that, and they are in a form of engagement with each other and when facing each other. Any configuration may be employed as long as the interval is constant over the entire length of the side. This can be easily realized if the condition that one is a concave side and the other is a protruding side is satisfied.

According to the sixth embodiment, the semiconductor chips 200A,
The connection between the 200A devices does not pass through a mother board (not shown), and the connection distance is determined by a conventional technique in which connection is made via a mother board shown in FIG. Compared with the case of the above, the wiring length on the mother substrate is reduced, and the wiring length of the two vias in the semiconductor carrier is reduced, so that connection with shorter wiring is possible.

Therefore, the connection distance can be reduced as in the case of the multi-chip module. Moreover, in each semiconductor device 300E, the semiconductor chip 200
Since each of A is packaged, inspection, burn-in, and the like of such a package alone are also possible, and as a result, the versatility of the semiconductor device to be connected is not impaired.

In addition, two semiconductor devices 3 arranged adjacent to each other
The wiring boards 100F, 100F of the first and second substrates 100E, 300E are connected to the stepped side portions 110, 1
10, the positioning can be performed extremely easily, and the external input / output connection electrodes 117, 117 of both end surfaces can be electrically connected with high precision and goodness. it can.

(Embodiment 7) Embodiment 7 of the present invention
Is equivalent to a modification of the first embodiment, and is different in the form of bonding between the end face type external input / output connection electrodes.

FIG. 15 is a process sectional view schematically showing a method of manufacturing a wiring board used in the semiconductor device of the seventh embodiment.
1 is a sectional view schematically showing a connection structure between semiconductor devices.

First, a method for manufacturing a wiring board used for a semiconductor device will be described. FIG. 1 schematically shows the manufacturing method.
5, reference numeral 100G denotes a wiring board, 901 denotes an insulator, 902 denotes a copper foil formed on both sides of the insulator 901, 903 denotes a through hole formed in the insulator 901, 904.
Is a cylindrical conductor formed in the through hole 902 by plating, 905 and 906 are wiring patterns formed on the upper and lower surfaces of the insulator 901, 907 is located on an end face of the conductor 904 and is exposed by cutting. It is an external input / output connection electrode of the end face type.

Next, a method of manufacturing the wiring board 100G shown in FIG. 15 will be described step by step.

First, as shown in FIG. 15A, copper foil 902 is thermocompression-bonded to both upper and lower surfaces of insulator 901 in a vacuum, and then vertically penetrated to a required position of insulator 901. Is formed using a tool such as a drill. As the insulator 901, for example, a ceramic green sheet is used.

Next, as shown in FIG. 15B, a cylindrical conductor 904 is formed on the inner peripheral wall surface of the through hole 903 by plating or the like.

Next, as shown in FIG. 15C, the wiring patterns 905 and 505 are formed on both upper and lower surfaces of the insulator 901.
906 is formed. This is performed by forming resist on the copper foils 902 and 902 on both upper and lower surfaces of the insulator 901 and etching. The formed wiring patterns 905 and 906 are connected to the conductor 904 integrally and in series.

Next, as shown in FIG. 15D, the cylindrical conductor 904 in the through hole 903 at a position corresponding to the rectangular peripheral portion of the wiring board 100G to be cut out from the insulator 901 is substantially centered. And cut vertically. As a result, an end face type external input / output connection electrode 907 is formed. Note that the above-described cutting is so-called dicing, and a plurality of wiring boards 100
G will be divided into individual pieces. That is, the division of the individual pieces and the formation of the external input / output connection electrodes 907 are performed simultaneously.

As described above, the wiring board 100G having the end face type external input / output connection electrode 907 is manufactured.

In FIG. 16 and FIG.
0A is a semiconductor chip, 201 is a semiconductor chip body, 20
Reference numeral 2 denotes a bump formed on the lower surface of the semiconductor chip body 201; 301, a sealing resin; 300G, a semiconductor device;
Is a mother board, 402 is an electrode terminal formed on the mother board 401, 403 is solder, 950 is a connector, 96
0 is a positioning member.

Note that items that have been described in the first embodiment and that are not described again in the seventh embodiment also apply to the seventh embodiment as they are, and a detailed description thereof will be omitted. The configuration of the seventh embodiment differs from that of the first embodiment in the following.

Next, a method for manufacturing the semiconductor device 300G will be described. The semiconductor chip 200A is mounted on the wiring board 100G by a face-down method. At this time,
The bumps 202 on the lower surface of the semiconductor chip body 201 are aligned with the wiring patterns 905 on the upper surface of the wiring substrate 100G and mounted, and the bumps 202 are bonded to the wiring patterns 905 by performing heating, ultrasonic irradiation, and the like. Thereby, the semiconductor chip 200A and the wiring board 10
0G is electrically connected.

A characteristic feature of this semiconductor device 300G is that, as shown in the plan view of FIG. 17A, a plurality of end face type recessed in a semi-cylindrical shape on one side of the wiring board 100G. This means that the external input / output connection electrodes 907 are arranged in a state of being electrically connected to the wiring pattern 905. Further, on the opposite side, there is no connection with the wiring pattern 905, but a plurality of concave portions 910 having a similar semi-cylindrical shape are arranged.

An external input / output connection electrode 907 of an end face type and a recess 91
A connector 950 and a positioning member 960 are provided in a state corresponding to position 0.

The connector 950 includes a support portion 951 firmly formed on the mother board 401 and a metal conductive pin 952 which is connected to the support portion 951 in an upright state. The conductor pins 952 have their surfaces plated with nickel or gold. Positioning member 96
0 is the same as the connector 950, but does not play the role of electrical connection. Such connectors 950 and positioning members 960 are attached to the motherboard 401 in a state of being arranged in a row.

The conductor pins 952 # of the row of connectors 950 on the mother board 401
Are connected to the external input / output connection electrodes 907, 907,... Of the two semiconductor devices 300G, 300G. And the two semiconductor devices 3 with respect to the mother board 401.
00G and 300G are placed. With such placement,
The external input / output connection electrodes 907 and 907 of the end face type are mechanically and electrically connected to each other via the conductor pins 952. That is, the semiconductor chips 200A, 200A in the semiconductor devices 300G, 300G are electrically connected to each other via the wiring patterns 905, 905, the end face type external input / output connection electrodes 907, 907, and the conductor pins 952.

Thereafter, solder reflow is performed to connect the electrode terminals 402 # on the mother substrate 401 and the semiconductor devices 300 with each other.
The wiring patterns 906 and 906 on the lower surfaces of the G and 300G are electrically connected via a hunter 403.

According to the seventh embodiment, the same advantage as that of the first embodiment can be obtained, that is, connection can be made without passing through the mother board. Also has the advantage that connection can be made with short wiring.

In addition, since electrical connection and mechanical alignment between the end face type external input / output connection electrodes 907 and 907 can be simultaneously performed via the connector 950, alignment control during mounting is extremely easy. It can be something.

In some cases, electrical connection between the mother substrate 401 and the wiring pattern 906 on the lower surface is not required.
In such a case, the solder reflow need not be performed. However, solder reflow may be performed to fix the position. When solder reflow is not performed, repair becomes easy.

Embodiment 8 Next, Embodiment 8 of the present invention will be described with reference to FIG. FIG. 18 is a plan view schematically showing a connection structure between semiconductor devices according to the eighth embodiment.

The wiring board 100H as a module is
This is a wiring board on which the semiconductor chip 200A is mounted.
The wiring boards 100K and 100M as modules are wiring boards on which the semiconductor chip 200A is not mounted.
In the illustrated example, two of the wiring boards 100H on which the semiconductor chip 200A is mounted, and two of the wiring boards 100K for corner connection on which the semiconductor chip 200A is not mounted.
And a total of six wiring boards, two of the relay connection wiring boards 100M on which the semiconductor chip 200A is not mounted, are arranged in a rectangular shape. The wiring board 100H on which the semiconductor chip is mounted is located at a diagonal corner. However, the arrangement as in the illustrated example is merely an example.

The wiring board 100H on which the semiconductor chip is mounted is
On the insulating base material 001, a wiring pattern 002 to be connected and extended from the semiconductor chip 200A is formed.
An external input / output connection electrode 003 of an end face type electrically connected to the second electrode 2 is formed, and a concave portion 004 is formed on the remaining two sides.

In the wiring board 100K for corner connection, a wiring pattern 012 for communicative connection is formed on an insulating base material 011. Two ends of the wiring board 100K are electrically connected to the wiring pattern 012. An external input / output connection electrode 013 of a connected end face type is formed, and a concave portion 014 is formed on the remaining two sides.

In the wiring substrate 100M for relay connection, a wiring pattern 022 for communicative connection is formed on the insulating base material 211, and the wiring pattern 022 is electrically connected to the end surfaces of three sides of the wiring substrate 100M. The connected end face type external input / output connection electrode 023 is formed, and the remaining one is connected.
A concave portion 024 is formed on the side.

Each of these two wiring boards 100H, 10H
0K and 100M have the same outer shape and outer dimensions.

The wiring board 100H on which the semiconductor chip is mounted, the wiring board 100K for corner connection, and the wiring board 100M for relay connection are arranged adjacent to each other at a right angle, and the external input / output connection electrodes of the wiring board 100H on which the semiconductor chip is mounted. 003 and the external input / output connection electrode 013 of the corner-connecting wiring board 100K are electrically connected to each other via a connector 050 press-fitted between them, and the wiring board 100H on which the semiconductor chip is mounted. The external input / output connection electrode 003 and the external input / output connection electrode 023 of the relay connection wiring board 100M are electrically connected to each other via a connector 050 which is a conductor pin press-fitted therebetween. I have.

Also, a wiring board 100K for corner connection is provided.
The external input / output connection electrode 013 and the external input / output connection electrode 023 of the relay connection wiring board 100M are also electrically connected via the connector 050. Further, wiring substrates 100M, 100M for relay connection facing in the center.
Are also electrically connected via a connector 050.

Then, the wiring board 10 on which the semiconductor chip is mounted
0H, the recessed portions 004, 014, and 024 corresponding to the outer peripheral regions of the wiring board 100K for corner connection and the wiring board 100M for relay connection, respectively.
The positioning member 060 is engaged to perform overall positioning. The positioning member 060 is the same as the connector 050.

Wiring boards 100H, 100K, 100M
Regardless of whether the semiconductor chip 200A is mounted or not, and whether the semiconductor chip 200A comes at a corner or in the middle, the shape and dimensions of each outer shape are standardized. External input / output connection electrode 00 of cylindrical end face type
The pitches of 3,013,023 and the recesses 004,014,024 are all equal. Further, the pitches of the connector 050 and the positioning member 060 provided on the mother board are all equal.

The connection between the semiconductor chips can be variously made by combining the wiring boards.

A plurality of types of wiring boards 100H, 100K,
By modularizing 100M as described above, various developments can be freely performed by combining these modules, and a plurality of semiconductor chips 20
It is possible to greatly improve the degree of freedom of the connection between 0A ‥.

According to the eighth embodiment, as in the first embodiment, semiconductor chips in a plurality of semiconductor devices are connected to each other via a wiring pattern on the surface of the semiconductor device and to an end of the wiring pattern. It can be connected directly through the end face type external input / output connection electrode and connector without going through the motherboard, compared to the conventional technology that connects semiconductor chips via wiring on the motherboard. Connection with short wiring.

[0200] In addition, positioning control at the time of mounting is easy, and wiring can be freely performed by exchanging a wiring board, so that versatility can be extremely enhanced.

[0201]

According to the present invention, in a wiring board having a wiring pattern formed on a surface of an insulator for connecting a semiconductor chip, an end face of the insulator is connected to the wiring pattern. Alternatively, since the external input / output connection electrode is formed in the extension part, it is possible to cope with high density, high integration, high speed operation, etc. of the semiconductor device. The wiring length of the connection between the two semiconductor chips can be shortened by not passing through the mother board, and the requirement for reducing the signal delay due to the large wiring length can be satisfied. Package, and various tests such as burn-in with such a package alone and repair (repair) can be easily realized. It is possible to ensure versatility.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view schematically illustrating a method for manufacturing a wiring substrate used for a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a plan view and a side view schematically showing a configuration of a semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a cross-sectional view and a plan view schematically showing a connection structure between semiconductor devices according to the first embodiment of the present invention.

FIG. 5 is a plan view schematically showing the relationship between the electrode pads of the semiconductor chip and the arrangement order of the external input / output connection electrodes of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a process cross-sectional view schematically showing a method of manufacturing a wiring board used for a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a process cross-sectional view schematically showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a plan view and a side view schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 9 is a sectional view schematically showing a connection structure between semiconductor devices according to a second embodiment of the present invention;

FIG. 10 is a process cross-sectional view schematically showing a method of manufacturing a wiring board used for a semiconductor device in Embodiment 3 of the present invention.

FIG. 11 is a plan view schematically showing a configuration of a semiconductor device according to a third embodiment of the present invention, and a cross-sectional view schematically showing a connection structure between semiconductor devices.

FIG. 12 is a process cross-sectional view schematically illustrating a method of manufacturing a wiring board used for a semiconductor device according to a fourth embodiment of the present invention.

FIG. 13 is a sectional view schematically showing a connection structure between semiconductor devices according to a fifth embodiment of the present invention;

FIG. 14 is a plan view schematically showing a connection structure between semiconductor devices according to a sixth embodiment of the present invention.

FIG. 15 is a process cross-sectional view schematically showing a method of manufacturing a wiring board used for a semiconductor device according to a seventh embodiment of the present invention.

FIG. 16 is a sectional view schematically showing a connection structure between semiconductor devices according to a seventh embodiment of the present invention;

FIG. 17 is a plan view schematically showing a semiconductor device and a plan view schematically showing a connection structure between semiconductor devices in a seventh embodiment of the present invention.

FIG. 18 is a plan view schematically showing a connection structure between semiconductor devices according to an eighth embodiment of the present invention.

FIG. 19 is a cross-sectional view of a face-down type semiconductor device and a cross-sectional view of a multichip module according to the related art.

[Explanation of symbols]

100A, 100B, 100C, 100D, 100E,
100F, 100G: Wiring board 100H, 100K, 100M: Wiring board as module 101: Insulator 102: Through hole 103: Conductive paste 104, 105: Wiring pattern 104a: Extending part 106: Via 107 (upper row) End face type external input / output connection electrode 108... Lower end face type external input / output connection electrode 110... Step side 110 a... Recessed side 110 b... Protruding side 110 c... Vertical side 117. Output connection electrode 200A: semiconductor chip 201: semiconductor chip body 202: bump 203: chip electrode pad 300A, 300B, 300C, 300D, 300E,
300G semiconductor device 301 sealing resin 401 mother substrate 402 electrode terminal 403 solder 404 direct bonding portion 501 insulator 501a inclined end surface 502 wiring pattern 503 support base material 504 adhesive layer 505 V D-shaped groove 506... Wiring patterns 507 and 508... Slant end face type external input / output connection electrodes 550. Dicing blade 601. Insulator 601 a. End face 602. Mold 700: Connection wiring board 701: Connection base 702: Connection pattern 703: Connection conductor 800: Connection conductor 901: Insulator 902: Copper foil 903: Through hole 904: Cylindrical conductor 905, 906: Wiring pattern 907 ... End face type external input / output connection electrode 910 ... Recessed part 950 ... Connector 9 52 Conductor pin 960 Positioning member 001,011,021 Insulating base material 002,012,022 Wiring pattern 003,013,023 End-face type external input / output connection electrode 004,014,024 ... Recess 050 Connector 060: Positioning member

Continued on the front page (72) Inventor Yutaka Taguchi 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F term (reference) 5F067 AA01 AA02 AB04 AB08 CB02

Claims (26)

[Claims] 1. An external input / output connection electrode is formed on an end face of an insulator in a state of being connected to a wiring pattern formed on the surface of the insulator for connecting a semiconductor chip. Wiring board for mounting semiconductor chips. 2. The external input / output connection electrode on the insulator end face is formed by cutting a via provided in a through hole formed in the insulator in a state of being connected to the wiring pattern on the insulator surface. The wiring board for mounting a semiconductor chip according to claim 1, wherein the wiring board is mounted. 3. An external input / output connection electrode on the insulator end face is a cylindrical conductor plated on an inner peripheral wall surface of a through hole formed in the insulator in a state of being connected to the wiring pattern on the insulator surface. 2. The wiring board for mounting a semiconductor chip according to claim 1, wherein the wiring board is formed by cutting. 4. The semiconductor chip mounting device according to claim 1, wherein said external input / output connection electrodes are arranged in a matrix on an end face of said insulator. Wiring board. 5. The wiring board for mounting a semiconductor chip according to claim 1, wherein an end face of the insulator on which the external input / output connection electrode is formed is an inclined end face. 6. A wiring pattern formed on one surface of an insulator for connecting a semiconductor chip, a wiring pattern formed on the other surface of the insulator for mounting on a motherboard, and An external input / output connection electrode formed on an end face of the insulator in a state of being connected to both of the wiring patterns, wherein the two wiring patterns and the external input / output connection electrode are connected to the insulator. A wiring board for mounting a semiconductor chip, wherein the wiring board is formed by transfer of a wiring layer attached to the insulator with pressure bonding to the insulator. 7. The semiconductor chip mounting device according to claim 1, wherein at least one side of the outer shape of the insulator is formed on a step side portion for positioning. Wiring board. 8. The external input / output connection electrodes are arranged in the order of arrangement of connection lands to chip electrode pads of the semiconductor chip on the inner end side of the wiring pattern formed on the surface of the insulator for connecting the semiconductor chip. The wiring board for mounting a semiconductor chip according to any one of claims 1 to 7, wherein the wiring board has the same relationship or a mirror image relationship as the arrangement order. 9. A wiring pattern formed on a surface of the insulator for connecting a semiconductor chip extends beyond an underfill region of the sealing resin to an edge or a vicinity of the edge of the insulator, A wiring board for mounting a semiconductor chip, wherein the extended portion is configured as an external input / output connection electrode. 10. An external input / output connection electrode formed on an end face of the insulator for connection to a semiconductor chip is formed in a recessed shape, and the recessed shape is formed on another side of the insulator. 5. The wiring board for mounting a semiconductor chip according to claim 1, wherein recesses for positioning having substantially the same size and the same arrangement as the connection electrodes for external input / output are formed. . 11. A wiring board for relay connection arranged in parallel with the wiring board according to claim 10, wherein a wiring pattern for relay connection formed on a surface of the insulator is formed. 11. An external input / output connection electrode according to claim 10, which is substantially the same size as the external input / output connection electrode on at least two end faces of the insulator in a state of being connected to the relay connection wiring pattern. A wiring board for relay connection, wherein a recessed portion is formed. 12. A wiring board for mounting a semiconductor chip according to any one of claims 1 to 10, wherein a semiconductor chip is mounted on said wiring board while being connected to said wiring pattern on said wiring board. A semiconductor device characterized by being mounted. 13. A structure in which a plurality of semiconductor devices each having a semiconductor chip mounted on an insulator are mounted on a mother board, and the semiconductor chips in each of the semiconductor devices are connected to each other. A semiconductor device having an external input / output connection electrode formed on an end face of the insulator in a state of being connected to a wiring pattern formed on the surface of the insulator to connect the semiconductor chip. Wherein the external input / output connection electrodes of adjacent semiconductor devices are directly joined to each other. 14. The semiconductor device according to claim 2, wherein the wiring substrate according to claim 2 or 4 to 8 is used as a wiring substrate. 14. The connection structure between semiconductor devices according to claim 13. 15. A structure in which a plurality of semiconductor devices each having a semiconductor chip mounted on an insulator are mounted on a mother board, and the semiconductor chips in each of the semiconductor devices are connected to each other. As a wiring pattern formed on the surface of the insulator to connect the semiconductor chip is extended to the edge or near the edge of the insulator beyond the underfill region of the sealing resin,
A semiconductor device having an extended portion configured as an external input / output connection electrode is used, and the external input / output connection electrodes of adjacent semiconductor devices are connected to each other via a connection wiring board. Connection structure between semiconductor devices. 16. The connection structure between semiconductor devices according to claim 15, wherein each of the semiconductor devices uses the wiring substrate according to claim 9 as a wiring substrate thereof. 17. A structure in which a plurality of semiconductor devices each having a semiconductor chip mounted on an insulator are mounted on a motherboard and the semiconductor chips in each of the semiconductor devices are connected to each other, wherein each of the semiconductor devices is A semiconductor device having an external input / output connection electrode formed on an end face of the insulator in a state of being connected to a wiring pattern formed on the surface of the insulator to connect the semiconductor chip. A semiconductor device, wherein the external input / output connection electrodes of adjacent semiconductor devices are connected to each other via a connector which is in common contact with these external input / output connection electrodes and performs positioning at the same time. Device connection structure. 18. The connection structure between semiconductor devices according to claim 17, wherein each of the semiconductor devices uses the wiring substrate according to claim 3 as a wiring substrate thereof. 19. The connection structure between semiconductor devices according to claim 17, wherein the connector is erected from the mother substrate. 20. The connection structure between semiconductor devices according to claim 17, wherein the connector is separated from the mother board. 21. A structure in which a plurality of semiconductor devices each having a semiconductor chip mounted on an insulator are mounted on a motherboard and the semiconductor chips in each of the semiconductor devices are connected to each other. An external input / output connection electrode formed on an end face of the insulator for connecting the semiconductor chip is formed in a concave shape, and the concave external input electrode is formed on another side of the insulator. A semiconductor device having a positioning recess having substantially the same size and the same arrangement as the output connection electrode is used, and a wiring board for relay connection between the plurality of semiconductor devices is provided on the surface of the insulator. The formed wiring pattern for relay connection is formed, and the semiconductive material is connected to at least two end faces of the insulator in a state of being connected to the wiring pattern for relay connection. A relay connection wiring board having substantially the same size and the same arrangement of recesses for positioning as the external input / output connection electrodes in the body device; and using the external input / output connection electrodes in the semiconductor device and the relay The semiconductor device according to claim 1, wherein the external input / output connection electrodes on the connection wiring board are connected to each other via a connector that makes common contact with the external input / output connection electrodes and performs positioning at the same time. Connection structure. 22. A step of forming a through hole in an insulator, a step of filling the through hole with a conductive paste, and forming a wiring pattern on both upper and lower surfaces of the insulator in a state of being connected to the conductive paste. And sintering the conductive paste to form vias, and dicing in a state of passing through a group of vias located at a position corresponding to the outer peripheral portion to form cut end surfaces of the vias as exposed external input / output connection electrodes. And a method for manufacturing a wiring board. 23. A step of forming a through hole in an insulator, a step of filling the through hole with a conductive paste, and forming a wiring pattern on both upper and lower surfaces of the insulator so as to be continuous with the conductive paste. And a step of firing the conductive paste to form vias, a step of laminating a plurality of wiring boards obtained as a result of the respective steps, and a step of passing through via groups arranged in a matrix at locations corresponding to the outer peripheral portion. Dicing in a state to form a cut end face of the via in an exposed state to form a matrix-like external input / output connection electrode. 24. A step of forming a conductor foil on both upper and lower surfaces of an insulator, a step of forming a through hole in the insulator and the conductor foil, and forming a tubular conductor on an inner peripheral wall surface of the through hole. A step of forming a wiring pattern by patterning both conductor foils on the insulator surface, and a step of forming a wiring pattern by connecting both conductor foils on the insulator surface, and performing dicing in a state of passing through a cylindrical conductor group located at a position corresponding to an outer peripheral portion. Forming a cut end surface of the cylindrical conductor as an external input / output connection electrode in an exposed state. 25. A step of laminating an insulator on a support base on which a wiring layer of a predetermined pattern is formed, and a step of: contacting the support base with the insulator and an end face of the insulator. Simultaneously transferring the wiring layer by pressing, forming the wiring pattern on the surface of the insulator by removing the supporting substrate while leaving the wiring layer, and applying external input / output to the end face of the insulator. Exposing the connection electrode. 26. A step of laminating and bonding an insulator and a supporting substrate, a step of forming a V-shaped groove in the insulator and forming an end face of the insulator as an inclined surface, Forming a wiring pattern on a surface and an inclined surface; and removing the support base material and dividing the insulator to form an external input / output connection electrode on the inclined surface of the insulator. A method for manufacturing a wiring board, which is characterized by the following.