JP2001284456A - Method for placement and routing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for placement and routing by which an arrangement of spare cells for a vacant regions after placement and routing of standard cells is efficiently set. SOLUTION: In a method for placement and routing for designing the arrangement and the wiring of standard cells in a placement and routing region corresponding to a circuit forming region on a semiconductor chip, dummy cells whose dimension is defined and which lack in the definition of the circuit to be arranged in the dummy cells and a column of spare cells wherein the circuit to be arranged in the dummy cells is defined are prepared, a plurality of standard cells satisfying a given function as a whole are arranged in the placement and routing region, the dummy cells are arranged in each space area that has the dimension equal to or greater than that of the dummy cells among the space regions after arranging a plurality of standard cells in the placement and routing region, and the dummy cells arranged are replace with the column of spare cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an arrangement and wiring method for designing arrangement and wiring of standard cells in an arrangement and wiring area corresponding to a circuit formation area on a semiconductor chip.

[0002]

2. Description of the Related Art Conventionally, as a cell used for forming a circuit on a semiconductor chip, a cell in which a circuit having a predetermined function optimized as a whole as a whole, such as a standard cell, is defined. . This cell is formed by wiring a metal on a base on which a plurality of semiconductor elements are formed, and has a different base for each type of cell.
Specific functions are realized for each type of cell.

When a circuit is modified to make a simple logical change, a cell is often required. In the case of a standard cell, once the base of the chip is formed, it is practically difficult to correct the circuit using the same base. However, the arrangement and wiring of the standard cell in the circuit forming area are difficult. In the free space that is not used by
If the bases of a plurality of cells (spare cells) other than these standard cells are prepared, the circuit can be corrected by simply applying metal wiring to the bases of the standard cells and the spare cells prepared in advance. it can.

[0004]

However, such a spare cell is composed of NAND, NOR, FF (Flip-Fl).
In the case of a polycell capable of realizing a plurality of basic logics such as (op), various types of spare cells exist and have various dimensions depending on the types. It is necessary to make detailed settings of the combination of spare cells (type, number, and position of each spare cell) arranged according to the space. If this setting is not performed efficiently, TAT (Turn Around Time), which is the time required for layout design, will increase.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a placement and routing method for efficiently setting the placement of a spare cell in an empty area after placement and routing of standard cells.

[0006]

According to the present invention, there is provided an arrangement and wiring method for designing and arranging standard cells in an arrangement and wiring area corresponding to a circuit forming area on a semiconductor chip. A dummy cell having a defined dimension and lacking a definition of a circuit to be arranged therein and a spare cell column in which a circuit to be arranged in the dummy cell is defined are prepared.
A plurality of standard cells satisfying a predetermined function as a whole are arranged, and an empty area having a size equal to or larger than the size of the dummy cell in the empty area after the plurality of standard cells is arranged in the arrangement wiring area In each case, the dummy cell is arranged, and the arranged dummy cell is
It is characterized in that it is replaced with the spare cell column.

Here, the spare cell column means an array of a plurality of spare cells in which circuits are defined.

In the placement and routing method of the present invention, since dummy cells are employed, when arranging spare cells in a vacant area, the size and size of the spare cells are different from those in the conventional method of arranging spare cells one by one in a vacant area. It is not necessary to consider the magnitude relationship between the number and the size of the free area one by one, but only the size of the dummy cell and the size of the free area. In the placement and routing method according to the present invention, the dummy cells arranged in consideration of the dimensions are replaced with the spare cell columns corresponding to the dummy cells, so that the spare cells can be simply and efficiently arranged in the empty area.

In the placement and routing method of the present invention, it is preferable to prepare dummy cells having a plurality of dimensions and a plurality of types of spare cell columns in which circuits to be arranged in the respective dummy cells are defined.

In this arrangement / wiring method, the entire empty area can be completely filled with dummy cells by appropriately combining dummy cells of a plurality of dimensions, and the entire empty area can be replaced by replacing the dummy cells with spare cell columns. It can be filled with spare cells.

In the arrangement / wiring method for preparing dummy cells having a plurality of dimensions, it is preferable that dummy cells having a plurality of dimensions are arranged in the empty area in order from a dummy cell having a large dimension.

According to this arrangement / wiring method, a dummy cell having a large size is arranged in the empty area while effectively utilizing the space of the empty area. When a large-sized dummy cell is arranged in the empty area in this way, the large-sized dummy cell can be replaced with a large-sized spare cell row having a function optimized as a whole.

[0013]

Embodiments of the present invention will be described below.

First, before describing the layout and wiring method of this embodiment, the layout of the above-described standard cells in a circuit formation region on a semiconductor chip will be briefly described.

FIG. 1 is a schematic configuration diagram of a circuit formation region on a semiconductor chip on which standard cells are arranged.

FIG. 1 shows a large rectangular circuit formation area 100 which extends in the left-right direction from the vicinity of the left end of the circuit formation area 100 to the vicinity of the right end of the same figure. There are a cell column portion 10 represented by four horizontally long rectangles arranged vertically and three wiring channels 20 sandwiched between these cell column portions 10. Each cell column section 10 includes a plurality of standard cells 1
Is arranged. Various wirings, such as wirings for connecting the standard cells 1, not shown in FIG.

Each of the cell rows 10 is not completely filled with the standard cells 1 without any gaps.
In some places, there are empty areas 2 where the standard cells 1 are not arranged. Spare cells prepared in advance other than the standard cells described above are arranged in the empty area 2.

The arrangement and wiring method according to the present embodiment is to arrange and arrange the standard cells 1 and the spare cells in the cell column section 10 in the arrangement and wiring area corresponding to the circuit formation area on the semiconductor chip. This is a method of designing these arrangements and wirings. Hereinafter, the arrangement and wiring method of the present embodiment will be described with reference to the flowchart shown in FIG.

FIG. 2 is a flowchart of the placement and routing method according to this embodiment.

In step S1, similarly to the arrangement of the standard cells shown in FIG. 1, a plurality of standard cells 1 are arranged and wired to the cell column section 10 in the arrangement and wiring area corresponding to the circuit forming area 100. Next, step S2
Proceed to.

In step S2, a dummy cell having a defined size and lacking the definition of a circuit to be arranged therein is arranged in each of the plurality of empty areas 2 in the arrangement and wiring area. However, the dummy cells are arranged only in each of the empty areas 2 having a size larger than the size of the dummy cell. These dummy cells are prepared in advance, for example, those shown in FIG.

FIG. 3 is a diagram showing an example of a dummy cell having a plurality of dimensions.

FIG. 3 shows seven dummy cells d64, d32, d16, d8, d4, d2, and d1 represented by seven rectangles having different horizontal lengths from each other.
Each is shown. These dummy cells d64,
d32, d16, d8, d4, d2, and d1 have lateral dimensions of 64, 32, and 64, respectively, as represented by the numbers assigned to these dummy cells in FIG.
The grid is 16, 8, 4, 2, 1 grid. Here, the vertical dimension of each of these dummy cells is
It is assumed that the dimensions are the same as the vertical dimension of each cell row section 10. The rectangles representing these dummy cells are:
In order to facilitate comparison of the dimensions of these dummy cells, they are greatly extended in the horizontal direction as compared with the standard cell 1 and the rectangle representing the empty area 2 shown in FIG.

Each of the plurality of empty areas 2 described above is
In arranging the plurality of dummy cells, it is preferable to arrange the dummy cells in descending order of size.
By arranging the dummy cells in this order from the largest in size, each space of the empty area 2 is secured as large as possible without being divided. Also,
When a plurality of dummy cells having a plurality of dimensions as shown in FIG. 3 are prepared, the entirety of each empty area can be completely filled with the dummy cells by appropriately combining the plurality of the dummy cells.

Next, the process proceeds to step S3.

In step S3, dummy cell arrangement information indicating where the dummy cells of various dimensions described above are arranged in each free area 2 in the arrangement and wiring area is created. This dummy cell arrangement information has an information amount much smaller than the information amount of the combination of spare cells (type, number, and position of each spare cell) in the conventional arrangement of spare cells.
, It is easy to create dummy cell arrangement information. Next, the process proceeds to step S4.

In step S4, spare cell columns corresponding to the dummy cells having various dimensions are obtained. Spare cell columns corresponding to the respective dummy cells are prepared in advance.

FIG. 4 is a diagram showing an example of the correspondence between dummy cells and spare cell columns.

FIG. 3 shows a dummy cell d64 also shown in FIG.
And an example of a spare cell column corresponding to the dummy cell d64. This spare cell column is connected to an inverter (in
verter) and one spare cell sp1
nd circuit, two spare cells sp2 and n
and seven spare cells sp3 representing an OR circuit. Here, these spare cells sp1, sp2, sp3 have dimensions of 3, 6, 7 grids, respectively.

The internal configuration information of the spare cell column is represented by the following spare_inv (0,0) spare_nand (3) with the point corresponding to the left end of the dummy cell replaced by the spare cell column as a reference origin (0,0). , 0) spare_nand (9, 0) spare_nor (15, 0) ... represented as spare_nor (56, 0). Here, for example, spare_na
nd (3,0) indicates that the left end of the spare cell representing nand is located at (3,0) with respect to the origin.

As in the case of the dummy cell d64 described above, the dummy cells d32, d16, d8, d4, d
A corresponding spare cell column is prepared for each of 2 and d1. Further, a plurality of spare cell columns may correspond to a dummy cell of a certain size. next,
Proceed to step S5.

At step S5, the arrangement information of the dummy cells created at step S3 and the internal configuration information of the spare cell columns corresponding to the dummy cells of various dimensions acquired at step S4 are combined, and 2 are replaced with the respective spare cell columns corresponding to the respective dummy cells.
By the replacement of the dummy cells with the spare cell columns, the placement of the spare cells in the empty area in the placement and wiring space by the placement and routing method of the present embodiment is completed.

As described above, according to the arrangement and wiring method of the present embodiment, when arranging the spare cells in the empty area 2,
Unlike the conventional method of arranging spare cells one by one in a free area, it is not necessary to consider one by one the size relationship between the size and the number of spare cells and the size of the free area. Good. Then, by simply replacing the dummy cells arranged in the empty area 2 in consideration of the dimensions with a predetermined spare cell row, the arrangement of the spare cells in the empty area 2 is easily and efficiently performed.

In other words, in the arrangement of the spare cells in the free area 2, the size of the free area and the size of the spare cell must be considered, and a plurality of spare cells have a predetermined function. like,
It is necessary to determine the arrangement from both sides, such as the side that the plurality of spare cells should be considered as an integrated arrangement. In the arrangement and wiring method of the present embodiment, only the dimensions are defined. By using the dummy cell, the aspect relating to the dimensions and the aspect of arranging the spare cells collectively can be handled separately, so that the arrangement of the spare cells is performed simply and efficiently. Such high efficiency is compared with the information amount of the combination of the spare cells (the type, number, and position of each spare cell) in the arrangement of the spare cells according to the conventional method. It can also be seen from the fact that both the dummy cell arrangement information and the internal configuration information of the spare cell require much less information.

As described above, the dummy cells defined only by the dimensions are placed in all the empty areas without gaps.
Since it is easy to embed 0%, it is also easy to fill each of these empty areas with spare cells.

Further, once the arrangement of the dummy cells in the empty area 2 is determined, the arrangement of the spare cells corresponding to the dummy cells in the empty area 2 is performed collectively without having to consider the dimensions.

Further, by placing dummy cells having larger dimensions in the empty area 2 in consideration of only the dimensions, a plurality of spare cells having a predetermined function as a whole can be replaced when a dummy cell and a spare cell column are replaced later. It becomes easy to arrange them all in one spare cell column. In the case where a plurality of spare cells having a predetermined function as a whole are collectively arranged in one spare cell column, the internal wiring required to realize the predetermined function can be shortened. Spare cells can operate at much higher speeds than gate arrays and at speeds comparable to standard cells.

As described above, according to the layout and wiring method of the present embodiment, the spare cells can be simply and efficiently arranged in the empty area 2.
T is shortened.

[0039]

As described above, according to the present invention,
A placement and routing method for efficiently setting the placement of spare cells in a vacant area after placement and routing of standard cells is provided.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a circuit formation region on a semiconductor chip on which standard cells are arranged.

FIG. 2 is a flowchart of a placement and routing method according to the embodiment.

FIG. 3 is a diagram showing an example of a dummy cell having a plurality of dimensions.

FIG. 4 is a diagram showing an example of correspondence between dummy cells and spare cell columns.

[Explanation of symbols]

 Reference Signs List 1 standard cell 2 free area 10 cell column section 20 wiring channel 100 circuit formation area

Claims (3)

[Claims] In a placement and routing method for designing placement and wiring of standard cells in a placement and routing area corresponding to a circuit formation area on a semiconductor chip, dimensions are defined and a circuit to be placed inside is not defined. A dummy cell and a spare cell column in which circuits to be arranged in the dummy cell are defined are prepared, and a plurality of standard cells satisfying a predetermined function as a whole are arranged in the arrangement and wiring area. Arranging the dummy cell in each of the empty areas having dimensions equal to or larger than the dimensions of the dummy cells among the empty areas after the plurality of standard cells are arranged, and replacing the arranged dummy cells with the spare cell columns. And a wiring method. 2. The layout and wiring according to claim 1, wherein a plurality of types of dummy cells and a plurality of types of spare cell columns in which circuits arranged in each of the dummy cells are defined are prepared. Method. 3. The placement and routing method according to claim 2, wherein when arranging dummy cells of a plurality of dimensions in each of the empty areas, the dummy cells are arranged in order from a dummy cell having a large dimension.