JP2015122398A - Semiconductor integrated circuit device and layout design method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can ensure flexibility to circuit correction after photomask manufacturing without increasing a substrate area and achieve countermeasures against an antenna effect.SOLUTION: A layout design method of a semiconductor integrated circuit device comprises: a step (a) of arranging a plurality of standard cells which form a plurality of function blocks, respectively, in a part of a logic circuit arrangement region; a step (b) of arranging a plurality of general-purpose basic cells each having no wiring layer, in a part of a region in the logic circuit region, where the standard cells are not arranged; and a step (c) of arranging on at least a part of a region in the logic circuit arrangement region, where the standard cells and the basic cells are not arranged, at least one diode cell including first and second diodes which are connected to between a gate electrode of a predetermined transistor and first and second power supply distribution lines, respectively.

Description

  The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device manufactured using a standard cell system. Furthermore, the present invention relates to a layout design method for such a semiconductor integrated circuit device.

  In the layout design of a standard cell type semiconductor integrated circuit device, a circuit element such as a MOS transistor is arranged by arranging and connecting a plurality of types of standard cells constituting a circuit block that realizes a desired function using a computer. Arrangement and wiring are determined. At this time, in order to prevent deterioration of the gate insulating film of the MOS transistor due to the antenna effect, a protective diode is connected between the gate electrode of the predetermined MOS transistor and the power supply wiring.

  The antenna effect is a phenomenon in which a long wiring is charged in an etching process of a metal wiring layer of a semiconductor integrated circuit device. For example, when the metal wiring layer is subjected to plasma etching, if the amount of charge accumulated in the gate electrode connected to the long wiring increases, the insulation of the gate insulating film is destroyed and the gate insulating film deteriorates, resulting in leakage current. It becomes an occurrence factor. Therefore, in the etching process of the metal wiring layer, when a long wiring connected to the gate electrode of the MOS transistor is formed and the wiring is not connected to the source or drain of another MOS transistor, the antenna effect is a problem. It becomes.

  In order to prevent the gate insulating film from being deteriorated due to such an antenna effect, in the layout design of a conventional standard cell type semiconductor integrated circuit device, after arranging a plurality of standard cells, a vacant area is protected. A diode is preferentially arranged.

  As a related technique, Patent Document 1 discloses a semiconductor integrated circuit device that is intended to reliably prevent destruction of a gate oxide film of a transistor due to an antenna effect without increasing the area of an LSI chip. Has been.

  In this semiconductor integrated circuit device, a plurality of standard cells corresponding to a logic function are provided, and a gap is provided between the standard cells. The gap is an unused area where no standard cell is provided. Metal wiring for electrically connecting the cells is provided. In a part of this unused area, an antenna effect protection cell is provided between the power supply line and the ground line, so that the input terminal is connected to the metal wiring and the gate oxide film is destroyed due to the antenna effect. Standard cells are protected from.

JP 2000-332206 A (paragraphs 0015-0017, FIGS. 1 and 2)

  However, in the manufacture of a semiconductor integrated circuit device, it may be necessary to modify a circuit after a photomask used to form a gate electrode, an impurity diffusion region, and a wiring is formed on a semiconductor substrate. Furthermore, it may be necessary to modify the circuit after the gate electrode and the impurity diffusion region are actually formed on the semiconductor substrate. In the layout design of a conventional standard cell type semiconductor integrated circuit device, a measure for correcting the circuit in such a case has not been considered.

  Accordingly, in view of the above points, one object of the present invention is to provide a circuit even when a circuit is modified after a photomask used in the manufacturing process of a semiconductor integrated circuit device is manufactured without increasing the area of the semiconductor substrate. Another object is to provide a semiconductor integrated circuit device capable of ensuring flexibility for correction and realizing countermeasures against antenna effects.

  In order to solve the above-described problems, a layout design method for a semiconductor integrated circuit device according to a first aspect of the present invention includes a plurality of standard cells that respectively configure a plurality of functional blocks that realize a logic function of the semiconductor integrated circuit device. (A) in which a plurality of general-purpose basic cells having no wiring layer are disposed in a part of the area where the standard cells are not disposed in the logic circuit layout area. (B) and a first diode connected between a gate electrode of a predetermined transistor and a first power supply line in at least a part of a region where the standard cell and the basic cell are not arranged in the logic circuit arrangement region And at least one diode cell including a second diode connected between the gate electrode and the second power supply line. Placing includes a step (c).

  A semiconductor integrated circuit device according to a first aspect of the present invention is a semiconductor integrated circuit device including a semiconductor substrate having a logic circuit arrangement region, and is disposed in a part of the logic circuit arrangement region. A plurality of standard cells, each of which constitutes a plurality of functional blocks that realize the logic function, and a plurality of general-purpose basics that are arranged in a part of the logic circuit arrangement area where the standard cells are not arranged and do not have a wiring layer A first diode disposed between at least a part of a region where the standard cell and the basic cell are not disposed in the logic circuit layout region and connected between a gate electrode of a predetermined transistor and a first power supply wiring; And at least one die including a second diode connected between the gate electrode and the second power supply line And a diode cell in a direction orthogonal to the longitudinal direction of the diode cell, an area between two standard cells, an area between the standard cell and the basic cell, or an end of a logic circuit arrangement area It is arranged in at least a part of the area.

  According to the first aspect of the present invention, a general-purpose basic cell and a protective diode cell are arranged in an area where a standard cell is not arranged in a logic circuit arrangement area, and the basic cell functions only by changing a wiring layer. Since it can be used as a block, flexibility in circuit correction can be achieved even when circuit correction is performed after a photomask used in the manufacturing process of a semiconductor integrated circuit device is manufactured without increasing the area of the semiconductor substrate. It is possible to provide a semiconductor integrated circuit device that can ensure the countermeasure against the antenna effect.

  Here, the width of the basic cell may be larger than the width of the diode cell, and the length of the standard cell, the length of the basic cell, and the length of the diode cell may be substantially equal. In that case, the diode cell can be arranged in the non-arranged area after the standard cell and the basic cell are arranged in the logic circuit arrangement area.

  A layout design method for a semiconductor integrated circuit device according to a second aspect of the present invention is the layout design method for a semiconductor integrated circuit device according to the first aspect of the present invention. A step (b1) of disposing a plurality of general-purpose first basic cells having no wiring layer in a part of a region where no cells are disposed; and a standard cell and a first basic cell are disposed in the logic circuit disposition region A step of disposing a plurality of general-purpose second basic cells having a width smaller than the width of the first basic cell and larger than the width of the diode cell and having no wiring layer in a part of the unfinished region ( b2).

  The semiconductor integrated circuit device according to the second aspect of the present invention is the semiconductor integrated circuit device according to the first aspect of the present invention in which a plurality of basic cells are not arranged and standard cells are not arranged in the logic circuit arrangement region. A plurality of general-purpose first basic cells which are arranged in a part of the area and do not have a wiring layer, and are arranged in a part of the area where the standard cell and the first basic cell are not arranged in the logic circuit arrangement area; A plurality of general-purpose second basic cells having a width smaller than the width of the first basic cell and larger than the width of the diode cell and having no wiring layer are included.

  According to the second aspect of the present invention, general-purpose first and second basic cells and protective diode cells are arranged in an area where standard cells are not arranged in the logic circuit arrangement area, and the wiring layer is changed. Since the first and second basic cells can be used as functional blocks alone, the circuit is formed after the photomask used in the manufacturing process of the semiconductor integrated circuit device is manufactured without increasing the area of the semiconductor substrate. A semiconductor integrated circuit device capable of further expanding flexibility for circuit correction even when correction is performed and realizing countermeasures against antenna effects can be provided.

  Here, the width of the first basic cell is approximately three times the width of the diode cell, the width of the second basic cell is approximately twice the width of the diode cell, the length of the standard cell and the first basic cell The length of the cell, the length of the second basic cell, and the length of the diode cell may be substantially equal. In that case, the second basic cell is arranged in the non-arranged region after the standard cell and the first basic cell are arranged in the logic circuit arrangement region, and further, the non-arranged after the second basic cell is arranged. Diode cells can be arranged in the region.

  In the above, the basic cell or the first basic cell has the first P-channel transistor and the first N-channel transistor having the common first gate electrode, and the second P having the common second gate electrode. A channel transistor and a second N-channel transistor may be included. In that case, various functional blocks can be configured by connecting a wiring to one or a plurality of basic cells or one or a plurality of first basic cells.

  The second basic cell may include a third P-channel transistor and a third N-channel transistor having a common third gate electrode. In that case, various functional blocks can be configured by connecting wirings to one or a plurality of first basic cells and second basic cells. Alternatively, an inverter can be configured by connecting a wiring to the second basic cell.

The top view which shows the layout of the semiconductor integrated circuit device which concerns on each embodiment of this invention. FIG. 3 is a plan view of a logic circuit arrangement region of the semiconductor integrated circuit device according to the first embodiment. The top view which shows the example of the layout of the basic cell in FIG. The top view which shows the example of the layout of the NAND circuit comprised using a basic cell. FIG. 5 is a circuit diagram showing a configuration of a NAND circuit shown in FIG. 4. The top view which shows the example of the layout of the diode cell in FIG. Sectional drawing which shows the example of the structure of the diode cell shown in FIG. The circuit diagram which shows the example of a connection of a diode cell and the transistor of protection object. The top view of the logic circuit arrangement | positioning area | region of the semiconductor integrated circuit device which concerns on 2nd Embodiment. FIG. 10 is a plan view showing an example of a layout of a second basic cell in FIG. 9. The top view of the layout of the inverter comprised using a 2nd basic cell. The circuit diagram which shows the structure of the inverter shown in FIG. 5 is a flowchart illustrating a layout design method according to the first embodiment. 9 is a flowchart showing a layout design method according to the second embodiment.

Embodiments of the present invention will be described below in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component, and the overlapping description is abbreviate | omitted.
FIG. 1 is a plan view schematically showing a layout of a semiconductor integrated circuit device according to each embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit device includes a semiconductor substrate 1 formed of a semiconductor material such as silicon. The semiconductor substrate 1 has at least a logic circuit arrangement area 10, and further has at least one of an analog circuit arrangement area 20, a memory arrangement area 30, and an I / O cell arrangement area 40. Also good.

  In the logic circuit arrangement region 10, various cells constituting the logic circuit and diode cells for protecting a predetermined MOS transistor from the antenna effect are arranged. In the analog circuit arrangement area 20, an analog circuit such as an analog IP (functional block) is arranged. A memory such as a memory IP is arranged in the memory arrangement area 30. In the I / O cell arrangement area 40, I / O cells including power supply terminals or input / output terminals and, if necessary, input / output circuits are arranged.

  FIG. 2 is an enlarged plan view showing a part of the logic circuit arrangement region of the semiconductor integrated circuit device according to the first embodiment of the present invention. As shown in FIG. 2, a plurality of standard cells 11, a plurality of basic cells 12, and at least one diode cell 13 are arranged in the logic circuit arrangement region 10.

  The plurality of standard cells 11 are arranged in a part of the logic circuit arrangement region 10 and constitute a plurality of functional blocks that realize the logic function of the semiconductor integrated circuit device. Each standard cell 11 includes a plurality of transistors and intra-cell wiring for connecting the transistors. For example, an inverter, a buffer, an AND circuit, a NAND circuit, an OR circuit, a NOR circuit, or Various functional blocks such as flip-flops are configured. The logical function of the semiconductor integrated circuit device is realized by connecting a plurality of standard cells 11 by inter-cell wiring.

  The basic cell 12 is a general-purpose cell that is arranged in a part of the area where the standard cell 11 is not arranged in the logic circuit arrangement area 10 and does not have a wiring layer. The basic cell 12 includes a plurality of transistors, and after circuit correction after manufacturing a photomask used in the manufacturing process of a semiconductor integrated circuit device, or after actually forming a gate electrode or an impurity diffusion region in a semiconductor substrate. It can be used in the circuit correction. In such a case, it is possible to configure a desired functional block by changing only the wiring layer and connecting the wiring to the basic cell 12.

  The diode cell 13 is arranged in at least a part of a region where the standard cell 11 and the basic cell 12 are not arranged in the logic circuit arrangement region 10 (non-arrangement region in the drawing). The diode cell 13 includes a first diode connected between a gate electrode of a predetermined transistor and a first power supply wiring, and a second diode connected between the gate electrode and the second power supply wiring. Including.

  Among the above cells, the size of the standard cell 11 is not constant, but the basic cell 12 and the diode cell 13 have a constant size. In the present application, the dimension of each cell in the longitudinal direction (Y-axis direction in the figure) of the basic cell 12 and the diode cell 13 is referred to as the “length” of the cell, and the longitudinal direction of the basic cell 12 and the diode cell 13 The dimension of each cell in the orthogonal direction (X-axis direction in the figure) will be referred to as the “width” of the cell.

  The diode cell 13 has the smallest size among the above cells. The size of the standard cell 11 is M times the size of the diode cell 13 (M is an integer of 2 or more), and the size of the basic cell 12 is N times the size of the diode cell 13 (N is 2 or more). Integer).

  In the following, a case where the length of the standard cell 11, the length of the basic cell 12, and the length of the diode cell 13 are substantially equal will be described as an example. In this case, the width of the standard cell 11 is M times the width of the diode cell 13, and the width of the basic cell 12 is N times the width of the diode cell 13. That is, the width of the basic cell 12 is larger than the width of the diode cell 13. Therefore, the diode cell 13 can be arranged in the non-arranged area after the standard cell 11 and the basic cell 12 are arranged in the logic circuit arrangement area 10. For example, the width of the basic cell 12 may be approximately three times the width of the diode cell 13.

  Since the basic cell 12 can be used to configure a functional block necessary for circuit correction, the basic cell 12 is placed in an area where the standard cell 11 is not arranged in the logic circuit arrangement area 10 as much as possible. It is desirable to arrange the basic cell 12. In addition, since it is possible to configure a larger functional block using a plurality of basic cells 12, the width of the area in which the standard cells 11 are not arranged in the X-axis direction shown in FIG. When the width of the cell 12 is twice or more, it is desirable to arrange a plurality of basic cells 12 in succession.

  The diode cell 13 is arranged using an unarranged region where the standard cell 11 and the basic cell 12 cannot be arranged. Therefore, the diode cell 13 has a region between the two standard cells 11, a region between the standard cell 11 and the basic cell 12, in a direction orthogonal to the longitudinal direction of the diode cell 13 (X-axis direction in the figure). Alternatively, it is arranged in at least a part of the end area of the logic circuit arrangement area 10. That is, the diode cell 13 is not disposed in the region between the two basic cells 12.

  FIG. 3 is a plan view showing an example of the layout of the basic cell in FIG. In FIG. 3, in order to clarify the size of the basic cell 12, a grid that is a reference in the layout design of the semiconductor integrated circuit device is shown. In the example shown in FIG. 3, the basic cell 12 has a length of 7 grids and a width of 3 grids.

  The basic cell 12 includes, for example, a P-channel MOS transistor QP1 and an N-channel MOS transistor QN1 having a common gate electrode G1, and a P-channel MOS transistor QP2 and an N-channel MOS transistor QN2 having a common gate electrode G2. .

  P-type impurity diffusion regions 51 to 53 are formed in the N well of the semiconductor substrate or in the N-type semiconductor substrate. The source and drain of the transistor QP1 are constituted by P-type impurity diffusion regions 51 and 52. Further, the source and drain of the transistor QP2 are constituted by P-type impurity diffusion regions 52 and 53.

  On the other hand, N-type impurity diffusion regions 61 to 63 are formed in a P-well or a P-type semiconductor substrate of the semiconductor substrate. The source and drain of the transistor QN1 are constituted by N-type impurity diffusion regions 61 and 62. Further, the source and drain of the transistor QN2 are constituted by N-type impurity diffusion regions 62 and 63.

  A plurality of basic cells 12 are arranged in a part of the area where the standard cells 11 are not arranged in the logic circuit arrangement area 10 shown in FIG. 2, thereby producing a photomask used in the manufacturing process of the semiconductor integrated circuit device. Even when the circuit correction is performed after this, the circuit correction can be flexibly handled only by changing the wiring layer. That is, various functional blocks can be configured by connecting wiring to one or a plurality of basic cells 12.

  For example, it is possible to configure one or two inverters, NAND circuits, or NOR circuits using one basic cell 12. Further, it is possible to configure a 2-input multiplexer (selection circuit) using the four basic cells 12. Furthermore, it is possible to configure a latch circuit with reset using six basic cells 12. In the following, a case where a NAND circuit is configured using one basic cell 12 will be described as an example.

  FIG. 4 is a plan view showing an example of the layout of a NAND circuit configured using the basic cells shown in FIG. In FIG. 4, “x” marks indicate the positions of through holes formed in the interlayer insulating film. A wiring formed on the interlayer insulating film is connected to gate electrodes or impurity diffusion regions of a plurality of transistors included in the basic cell 12 through through holes.

  FIG. 5 is a circuit diagram showing a configuration of the NAND circuit shown in FIG. As shown in FIGS. 4 and 5, in this NAND circuit, the sources of the transistors QP1 and QP2 are connected to the first power supply wiring to which the power supply potential VDD on the high potential side is supplied, and the transistors QP1 and QP2 The drain is integrally formed and connected to the wiring of the output terminal B. The gate of the transistor QP1 is connected to the wiring of the input terminal A1, and the gate of the transistor QP2 is connected to the wiring of the input terminal A2.

  The drain of the transistor QN1 is connected to the wiring of the output terminal B, the source of the transistor QN1 is formed integrally with the drain of the transistor QN2, and the source of the transistor QN2 is the power supply potential on the low potential side. It is connected to the second power supply wiring to which VSS is supplied. The gate of the transistor QN1 is connected to the wiring of the input terminal A1, and the gate of the transistor QN2 is connected to the wiring of the input terminal A2.

  Accordingly, the NAND circuit shown in FIGS. 4 and 5 activates the output signal output from the output terminal B to a low level when a high level input signal is supplied to both the input terminals A1 and A2. In other cases, the output signal output from the output terminal B is deactivated to a high level.

  FIG. 6 is a plan view showing an example of the layout of the diode cell in FIG. In FIG. 6, in order to clarify the size of the diode cell 13, a reference grid in the layout design of the semiconductor integrated circuit device is shown. In the example shown in FIG. 6, the diode cell 13 has a length of 7 grids and a width of 1 grid.

  Further, in FIG. 6, “x” marks indicate the positions of through holes formed in the interlayer insulating film. The wiring formed on the interlayer insulating film is connected to the impurity diffusion regions of the first and second diodes included in the diode cell 13 through through holes.

  FIG. 7 is a cross-sectional view showing an example of the structure of the diode cell shown in FIG. As shown in FIG. 7, an N well 71 and a P well 72 are formed in a P type semiconductor substrate 1. An N-type impurity diffusion region 73 and a P-type impurity diffusion region 74 are formed in the N well 71. On the other hand, an N-type impurity diffusion region 75 and a P-type impurity diffusion region 76 are formed in the P well 72. Note that when an N-type semiconductor substrate is used, the N-well 71 may be omitted, and when a P-type semiconductor substrate is used, the P-well 72 may be omitted.

  An interlayer insulating film 2 is formed on the semiconductor substrate 1. A wiring 77, a first power supply wiring 78 to which a power supply potential VDD is supplied, and a power supply potential VSS are supplied on the interlayer insulating film 2. A second power supply wiring 79 is formed. These wirings are connected to one of the impurity diffusion regions through through holes formed in the interlayer insulating film 2.

  A first power supply wiring 78 is connected to the N-type impurity diffusion region 73, whereby the N well 71 is also electrically connected to the first power supply wiring 78. The P-type impurity diffusion region 74 constitutes the anode of the first diode, and the N well 71 and the N-type impurity diffusion region 73 constitute the cathode of the first diode.

  A second power supply wiring 79 is connected to the P-type impurity diffusion region 76, whereby the P well 72 is also electrically connected to the second power supply wiring 79. The P-type impurity diffusion region 76 and the P-well 72 constitute the anode of the second diode, and the N-type impurity diffusion region 75 constitutes the cathode of the second diode.

  The P-type impurity diffusion region 74 and the N-type impurity diffusion region 75 are connected to a gate electrode of a predetermined transistor via a wiring 77. Here, the predetermined transistor is a transistor to be protected from the antenna effect in the etching process of the metal wiring layer of the semiconductor integrated circuit device.

  Specifically, in one of the metal wiring layer etching steps, a wiring having a predetermined length (for example, 10 μm) connected to the gate electrode of the transistor is formed, and the wiring is the source or drain of another transistor. In the case where the transistor is not connected to an impurity diffusion region, it is necessary to protect the transistor from the antenna effect. In particular, for each transistor having a gate electrode connected to the input terminal via a wiring in each standard cell, the wiring may not be connected to an impurity diffusion region such as a source or drain of another transistor. Is likely.

  FIG. 8 is a circuit diagram showing a connection example between the diode cell shown in FIGS. 6 and 7 and a transistor to be protected. In the example shown in FIG. 8, the P channel MOS transistor QP3 and the N channel MOS transistor QN3 included in any of the standard cells 11 are to be protected. A long wiring formed in the first wiring layer is connected to the gate electrodes of the transistors QP3 and QN3, and the wiring is an impurity diffusion region such as a source or drain of another transistor in the first wiring layer. Not connected to.

  As shown in FIG. 8, the diode cell 13 includes a first diode D1 connected between the gate electrodes of the transistors QP3 and QN3 to be protected and the first power supply wiring 78, and gate electrodes of the transistors QP3 and QN3. And a second diode D2 connected between the second power supply wiring 79 and the second power supply wiring 79. The first power supply wiring 78 is connected to the power supply terminal 81 to which the power supply potential VDD is supplied, and the second power supply wiring 79 is connected to the power supply terminal 82 to which the power supply potential VSS is supplied.

  If positive charges are accumulated in the gate electrodes of the transistors QP3 and QN3 in the first wiring layer etching step, the positive charges are released to the first power supply wiring 78 through the diode D1. Further, when the first power supply wiring 78 is connected to the power supply terminal 81 during etching, positive charges can be discharged to the power supply terminal 81.

  On the other hand, when negative charges are accumulated in the gate electrodes of the transistors QP3 and QN3 in the etching process of the first wiring layer, the negative charges are discharged to the second power supply wiring 79 through the diode D2. In addition, when the second power supply wiring 79 is connected to the power supply terminal 82 during the etching, negative charges can be discharged to the power supply terminal 82.

Next, a semiconductor integrated circuit device according to a second embodiment of the present invention will be described.
FIG. 9 is an enlarged plan view showing a part of the logic circuit arrangement region of the semiconductor integrated circuit device according to the second embodiment of the present invention. In the second embodiment, the first basic cell 12a and the second basic cell 12b shown in FIG. 9 are used as the basic cells. In other respects, the semiconductor integrated circuit device according to the second embodiment is the same as the semiconductor integrated circuit device according to the first embodiment.

  The first basic cell 12a is a general-purpose cell that is arranged in a part of the area where the standard cell 11 is not arranged in the logic circuit arrangement area 10 and does not have a wiring layer. For example, the first basic cell 12a may be the same as the basic cell 12 shown in FIG. The second basic cell 12b is a general-purpose cell that is arranged in a part of the area where the standard cell 11 and the first basic cell 12a are not arranged in the logic circuit arrangement area 10 and has no wiring layer. The second basic cell 12b has a width smaller than the width of the first basic cell 12a and larger than the width of the diode cell 13.

  The diode cell 13 is arranged in at least a part of a region where the standard cell 11, the first basic cell 12a, and the second basic cell 12b are not arranged (non-arranged region in the drawing) in the logic circuit arrangement region 10. . The diode cell 13 includes a first diode connected between a gate electrode of a predetermined transistor and a first power supply wiring, and a second diode connected between the gate electrode and the second power supply wiring. Including.

  The diode cell 13 has the smallest size among the above cells. The size of the standard cell 11 is M times the size of the diode cell 13 (M is an integer of 2 or more), and the size of the first basic cell 12a is N1 times the size of the diode cell 13 (N1 is 3), the size of the second basic cell 12b is N2 times the size of the diode cell 13 (N2 is an integer of 2 or more and smaller than N1).

  In the following, a case where the length of the standard cell 11, the length of the first basic cell 12a, the length of the second basic cell 12b, and the length of the diode cell 13 are substantially equal will be described. In that case, the width of the standard cell 11 is M times the width of the diode cell 13, the width of the first basic cell 12a is N1 times the width of the diode cell 13, and the width of the second basic cell 12b is , N2 times the width of the diode cell 13.

  That is, the width of the second basic cell 12b is smaller than the width of the first basic cell 12a and larger than the width of the diode cell 13. Accordingly, in the logic circuit arrangement area 10, the second basic cell 12b is arranged in the non-arranged area after the standard cell 11 and the first basic cell 12a are arranged, and further, the second basic cell 12b is arranged. The diode cell 13 can be arranged in the non-arranged region. For example, the width of the first basic cell 12a may be approximately three times the width of the diode cell 13, and the width of the second basic cell 12b may be approximately twice the width of the diode cell 13.

  Since the first basic cell 12a can be used to configure a functional block necessary for circuit correction, the first basic cell 12a can be used in an area where the standard cell 11 is not arranged in the logic circuit arrangement area 10. It is desirable to arrange the first basic cell 12a as much as possible. In addition, since it is possible to configure a larger functional block using a plurality of first basic cells 12a, in the X-axis direction shown in FIG. When the width is twice or more the width of the first basic cell 12a, it is desirable to arrange a plurality of first basic cells 12a in succession.

  The second basic cell 12b is arranged using an area where the standard cell 11 and the first basic cell 12a cannot be arranged. Since the second basic cell 12b can also be used to configure a functional block necessary for circuit correction, the standard cell 11 and the first basic cell 12a are included in the logic circuit arrangement region 10. It is desirable to arrange the second basic cell 12b as much as possible in the non-arranged region. In addition, by combining the second basic cell 12b with one or a plurality of first basic cells 12a, it is possible to configure a larger functional block, so in the X-axis direction shown in FIG. It is desirable to arrange the second basic cell 12b continuously with the first basic cell 12a.

  The diode cell 13 is disposed using a non-arranged region where the standard cell 11, the first basic cell 12a, and the second basic cell 12b cannot be disposed. Therefore, the diode cell 13 has a region between the two standard cells 11, the standard cell 11 and the first basic cell 12a or the second cell in the direction orthogonal to the longitudinal direction of the diode cell 13 (X-axis direction in the drawing). Are arranged in at least a part of a region between the basic cell 12 b and the end portion of the logic circuit arrangement region 10. That is, the region between the two first basic cells 12a, the region between the first basic cell 12a and the second basic cell 12b, and the region between the two second basic cells 12b The diode cell 13 is not disposed.

  FIG. 10 is a plan view showing an example of the layout of the second basic cell in FIG. In FIG. 10, in order to clarify the size of the second basic cell 12b, a grid serving as a reference in the layout design of the semiconductor integrated circuit device is shown. In the example shown in FIG. 10, the second basic cell 12b has a length of 7 grids and a width of 2 grids.

  The second basic cell 12b includes, for example, a P channel MOS transistor QP3 and an N channel MOS transistor QN3 having a common gate electrode G3. P-type impurity diffusion regions 54 and 55 are formed in an N well of the semiconductor substrate or an N-type semiconductor substrate. The source and drain of the transistor QP3 are constituted by P-type impurity diffusion regions 54 and 55. On the other hand, N-type impurity diffusion regions 64 and 65 are formed in a P-well of the semiconductor substrate or a P-type semiconductor substrate. The source and drain of the transistor QN3 are constituted by N-type impurity diffusion regions 64 and 65.

  In the logic circuit arrangement area 10 shown in FIG. 9, the second basic cell 12b is arranged in a part of the area where the standard cell 11 and the first basic cell 12a are not arranged, thereby manufacturing the semiconductor integrated circuit device. Even when the circuit correction is performed after the photomask used in the process is manufactured, the circuit correction can be dealt with more flexibly only by changing the wiring layer. That is, various functional blocks are configured by connecting wiring to one or a plurality of first basic cells 12a and second basic cells 12b arranged continuously in the X-axis direction shown in FIG. Is possible. Alternatively, an inverter can be configured by connecting a wiring to the second basic cell 12b.

  FIG. 11 is a plan view showing an example of the layout of an inverter configured using the second basic cell shown in FIG. In FIG. 4, “x” marks indicate the positions of through holes formed in the interlayer insulating film. The wiring formed on the interlayer insulating film is connected to the gate electrodes or impurity diffusion regions of the plurality of transistors included in the second basic cell 12b through through holes.

  FIG. 12 is a circuit diagram showing a configuration of the inverter shown in FIG. As shown in FIGS. 11 and 12, in this inverter, the source of the transistor QP3 is connected to the first power supply wiring to which the power supply potential VDD is supplied, and the drain of the transistor QP3 is connected to the wiring of the output terminal D. The gate of the transistor QP3 is connected to the wiring of the input terminal C.

  The drain of the transistor QN3 is connected to the wiring of the output terminal D, the source of the transistor QN3 is connected to the second power supply wiring to which the power supply potential VSS is supplied, and the gate of the transistor QN3 is connected to the input It is connected to the wiring of terminal C. Thus, the inverter inverts the level of the input signal supplied to the input terminal C, and outputs an output signal having the inverted level from the output terminal D.

  Next, a layout design method for the semiconductor integrated circuit device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 13 is a flowchart showing a layout design method of the semiconductor integrated circuit device according to the first embodiment of the present invention. The layout design method according to each embodiment of the present invention is intended for logic circuit layout design.

  As a pre-stage of layout design, a net list is created by designing a circuit of the semiconductor integrated circuit device. The netlist includes information for specifying a plurality of standard cells that respectively constitute a plurality of functional blocks that realize a logic function of the semiconductor integrated circuit device, and information for specifying a connection relationship between these standard cells.

  The created netlist is input to a computer, and software (automatic placement and routing tool) operating on the computer designs a logic circuit layout based on the netlist. At that time, a library for storing information relating to the layout of the standard cell 11, the basic cell 12, and the diode cell 13 is used.

  In step S <b> 11, the automatic placement and routing tool places a plurality of standard cells 11 that respectively constitute a plurality of functional blocks that realize the logic function of the semiconductor integrated circuit device in a part of the logic circuit placement region 10. Thereby, the positions of the gate electrodes and the sources / drains of the plurality of transistors included in the standard cell 11 are determined, and the wiring in the standard cell 11 is determined.

  In step S12, the automatic placement and routing tool places a plurality of general-purpose basic cells 12 (see FIG. 3) having no wiring layer in a part of the logic circuit placement region 10 where the standard cells 11 are not placed. . As a result, the positions of the gate electrodes and the sources / drains of the plurality of transistors included in the basic cell 12 are determined.

  Since the basic cell 12 can be used to configure a functional block necessary for circuit correction, the basic cell 12 is placed in an area where the standard cell 11 is not arranged in the logic circuit arrangement area 10 as much as possible. It is desirable to arrange the basic cell 12. In addition, since it is possible to configure a larger functional block using a plurality of basic cells 12, the width of the area in which the standard cells 11 are not arranged in the X-axis direction shown in FIG. When the width of the cell 12 is twice or more, it is desirable to arrange a plurality of basic cells 12 in succession.

  In step S13, the automatic placement and routing tool sets wiring between a plurality of cells. At the same time, the automatic placement and routing tool places at least one diode cell 13 (see FIGS. 6 and 7) in at least a part of the area where the standard cell 11 and the basic cell 12 are not placed in the logic circuit placement area 10. To do.

  Thereby, the positions of the anode and the cathode of the first and second diodes included in the diode cell 13 are determined. The first diode is connected between the gate electrode of the transistor to be protected and the first power supply wiring, and the second diode is connected between the gate electrode and the second power supply wiring. (See FIG. 8).

  According to the above procedure, the possibility that a plurality of basic cells 12 can be continuously arranged in preparation for circuit correction after photomask fabrication is increased. For example, when adding a latch circuit with reset in circuit correction, There is an advantage that it is easy to secure an area for continuously arranging the six basic cells 12. In addition, the non-arranged areas after the basic cells 12 are arranged are scattered almost uniformly on the entire surface of the logic circuit arrangement area 10, and the diode cells 13 can be arranged near the transistors to be protected. It is possible to take sufficient antenna effect countermeasures.

  In step S14, it is determined whether or not circuit correction is necessary after a photomask used in the manufacturing process of the semiconductor integrated circuit device is manufactured. If circuit correction is required, the netlist is corrected. Furthermore, a replacement netlist is created in which at least one basic cell 12 is replaced with a functional block based on the corrected netlist. The created replacement netlist is input to a computer, and software (automatic placement and routing tool) operating on the computer corrects the layout of the logic circuit based on the replacement netlist.

  In step S15, the automatic placement and routing tool configures a desired functional block by changing only the wiring layer in the layout designed in steps S11 to S13 and connecting the wiring to at least one basic cell 12. The functional block constituted by the basic cells 12 is used for realizing the logic function of the semiconductor integrated circuit device together with the plurality of standard cells 11 or in place of some standard cells 11.

  According to the first embodiment of the present invention, the general-purpose basic cell 12 and the protection diode cell 13 are arranged in the area where the standard cell 11 is not arranged in the logic circuit arrangement area 10, and only the wiring layer is changed. Thus, the basic cell 12 can be used as a functional block. Therefore, without increasing the area of the semiconductor substrate, it is possible to ensure flexibility in circuit correction even when circuit correction is performed after manufacturing a photomask used in the manufacturing process of a semiconductor integrated circuit device, and to realize countermeasures against the antenna effect. A semiconductor integrated circuit device that can be provided can be provided.

  Next, a layout design method for a semiconductor integrated circuit device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 14 is a flowchart showing a layout design method for a semiconductor integrated circuit device according to the second embodiment of the present invention. In the second embodiment, the first basic cell 12a and the second basic cell 12b shown in FIG. 9 are used as the basic cells. In other respects, the layout design method according to the second embodiment is the same as the layout design method according to the first embodiment.

  In step S <b> 21, the automatic placement and routing tool places a plurality of standard cells 11 that respectively constitute a plurality of functional blocks that realize the logic function of the semiconductor integrated circuit device in a part of the logic circuit placement region 10. Thereby, the positions of the gate electrodes and the sources / drains of the plurality of transistors included in the standard cell 11 are determined, and the wiring in the standard cell 11 is determined.

  In step S22, the automatic placement and routing tool places a plurality of general-purpose first basic cells 12a having no wiring layer in a part of the logic circuit placement area 10 where the standard cells 11 are not placed. The first basic cell 12a may be the same as the basic cell 12 shown in FIG. Thereby, the positions of the gate electrodes and the source / drain of the plurality of transistors included in the first basic cell 12a are determined.

  Since the first basic cell 12a can be used to configure a functional block necessary for circuit correction, the first basic cell 12a can be used in an area where the standard cell 11 is not arranged in the logic circuit arrangement area 10. It is desirable to arrange the first basic cell 12a as much as possible. In addition, since it is possible to configure a larger functional block using a plurality of first basic cells 12a, in the X-axis direction shown in FIG. When the width is twice or more the width of the first basic cell 12a, it is desirable to arrange a plurality of first basic cells 12a in succession.

  In step S23, the automatic placement and routing tool uses a plurality of general-purpose second basics having no wiring layer in a part of the logic circuit placement region 10 where the standard cells 11 and the first basic cells 12a are not placed. The cell 12b is arranged. The second basic cell 12b has a width smaller than the width of the first basic cell 12a and larger than the width of the diode cell 13. As a result, the positions of the gate electrodes and the sources / drains of the plurality of transistors included in the second basic cell 12b are determined.

  The second basic cell 12b is arranged using an area where the standard cell 11 and the first basic cell 12a cannot be arranged. Since the second basic cell 12b can also be used to configure a functional block necessary for circuit correction, the standard cell 11 and the first basic cell 12a are included in the logic circuit arrangement region 10. It is desirable to arrange the second basic cell 12b as much as possible in the non-arranged region. In addition, by combining the second basic cell 12b with one or a plurality of first basic cells 12a, it is possible to configure a larger functional block, so in the X-axis direction shown in FIG. It is desirable to arrange the second basic cell 12b continuously with the first basic cell 12a.

  In step S24, the automatic placement and routing tool sets wiring between a plurality of cells. At the same time, the automatic placement and routing tool includes at least one diode cell 13 in at least a part of a region where the standard cell 11, the first basic cell 12 a, and the second basic cell 12 b are not arranged in the logic circuit placement region 10. (See FIGS. 6 and 7).

  Thereby, the positions of the anode and the cathode of the first and second diodes included in the diode cell 13 are determined. The first diode is connected between the gate electrode of the predetermined transistor and the first power supply wiring, and the second diode is connected between the gate electrode and the second power supply wiring. (See FIG. 8).

  According to the above procedure, there is a high possibility that a plurality of first basic cells 12a can be continuously arranged in preparation for circuit correction after photomask fabrication. For example, a latch circuit with reset is added in circuit correction. In this case, there is an advantage that it becomes easy to secure an area for continuously arranging the six first basic cells 12a. In addition, the non-arranged area after the first basic cell 12a and the second basic cell 12b are arranged is substantially uniformly distributed over the entire surface of the logic circuit arrangement area 10, and the diode cell is located near the transistor to be protected. 13 can be disposed, and sufficient antenna effect measures can be taken.

  In step S25, it is determined whether circuit correction is necessary after a photomask used in the manufacturing process of the semiconductor integrated circuit device is manufactured. If circuit correction is required, the netlist is corrected. Furthermore, based on the modified netlist, a replacement netlist is created in which at least one first basic cell 12a and / or at least one second basic cell 12b is replaced with a functional block. The created replacement netlist is input to a computer, and software (automatic placement and routing tool) operating on the computer corrects the layout of the logic circuit based on the replacement netlist.

  In step S26, the automatic placement and routing tool changes only the wiring layer in the layout designed in steps S21 to S24, and changes to at least one first basic cell 12a and / or at least one second basic cell 12b. A desired functional block is configured by connecting the wiring. The functional block constituted by the first basic cell 12a and / or the second basic cell 12b has the logical function of the semiconductor integrated circuit device together with the plurality of standard cells 11 or in place of some standard cells 11. Used to realize.

  According to the second embodiment of the present invention, a general-purpose first basic cell 12a and second basic cell 12b, and a protective diode in an area where the standard cell 11 is not arranged in the logic circuit arrangement area 10. The cell 13 is arranged, and the first basic cell 12a and the second basic cell 12b can be used as functional blocks only by changing the wiring layer. Accordingly, even when the circuit correction is performed after the photomask used in the manufacturing process of the semiconductor integrated circuit device is manufactured without increasing the area of the semiconductor substrate, the flexibility for the circuit correction is further expanded and the antenna effect countermeasure is taken. A semiconductor integrated circuit device that can be realized can be provided.

  The present invention is not limited to the embodiments described above, and many modifications can be made within the technical idea of the present invention by those having ordinary knowledge in the technical field.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Interlayer insulating film, 10 ... Logic circuit arrangement | positioning area | region, 11 ... Standard cell, 12 ... Basic cell, 12a ... 1st basic cell, 12b ... 2nd basic cell, 13 ... Diode cell, 20 ... Analog circuit arrangement area, 30 ... Memory arrangement area, 40 ... I / O cell arrangement area, 51 to 55, 74, 76 ... P-type impurity diffusion area, 61 to 65, 73, 75 ... N-type impurity diffusion area, 71 ... N well, 72 ... P well, 77 ... wiring, 78 ... first power supply wiring, 79 ... second power supply wiring, 81, 82 ... power supply terminals, QP1 to QP3 ... P channel MOS transistors, QN1 to QN3 ... N Channel MOS transistors, G1 to G3 ... gate electrodes, D1, D2 ... diodes, A1, A2, C ... input terminals, B, D ... output terminals

Claims (8)

A method for designing a layout of a semiconductor integrated circuit device, comprising:
A step (a) of disposing a plurality of standard cells respectively constituting a plurality of functional blocks for realizing a logic function of the semiconductor integrated circuit device in a part of a logic circuit disposition region;
(B) disposing a plurality of general-purpose basic cells having no wiring layer in a part of a region where standard cells are not disposed in the logic circuit disposition region;
A first diode connected between a gate electrode of a predetermined transistor and a first power supply wiring in at least a part of a region where the standard cell and the basic cell are not arranged in the logic circuit arrangement region, and the gate electrode (C) disposing at least one diode cell including a second diode connected between the first power supply wiring and the second power supply wiring;
A layout design method comprising:   The layout design method according to claim 1, wherein a width of the basic cell is larger than a width of the diode cell, and a length of the standard cell, a length of the basic cell, and a length of the diode cell are substantially equal.   Step (b) is a step (b1) in which a plurality of general-purpose first basic cells not having a wiring layer are arranged in a part of a region where standard cells are not arranged in the logic circuit arrangement region, and the logic In a part of the region where the standard cell and the first basic cell are not arranged in the circuit arrangement region, the wiring layer has a width smaller than the width of the first basic cell and larger than the width of the diode cell. The layout design method according to claim 1, further comprising a step (b2) of arranging a plurality of general-purpose second basic cells that are not provided.   The width of the first basic cell is approximately three times the width of the diode cell, the width of the second basic cell is approximately twice the width of the diode cell, and the length of the standard cell and the second 4. The layout design method according to claim 3, wherein a length of one basic cell, a length of the second basic cell, and a length of the diode cell are substantially equal.   The basic cell or the first basic cell has a first P-channel transistor and a first N-channel transistor having a common first gate electrode, and a second P-channel having a common second gate electrode The layout design method according to claim 1, comprising a transistor and a second N-channel transistor.   5. The layout design method according to claim 3, wherein the second basic cell includes a third P-channel transistor and a third N-channel transistor having a common third gate electrode. A semiconductor integrated circuit device including a semiconductor substrate having a logic circuit arrangement region,
A plurality of standard cells that are arranged in a part of the logic circuit arrangement region and respectively constitute a plurality of functional blocks that realize the logic function of the semiconductor integrated circuit device;
A plurality of general-purpose basic cells that are arranged in a part of the area where the standard cells are not arranged in the logic circuit arrangement area and have no wiring layer;
A first diode disposed in at least a part of a region where the standard cell and the basic cell are not disposed in the logic circuit placement region, and connected between a gate electrode of a predetermined transistor and a first power supply wiring; At least one diode cell including a second diode connected between the gate electrode and the second power supply wiring;
The diode cell is in a direction orthogonal to the longitudinal direction of the diode cell, an area between two standard cells, an area between the standard cell and the basic cell, or an edge of the logic circuit arrangement area A semiconductor integrated circuit device disposed in at least part of the region of the part.   The plurality of basic cells are arranged in a part of a region where the standard cell is not arranged in the logic circuit arrangement region, and a plurality of general-purpose first basic cells having no wiring layer are arranged in the logic circuit arrangement region. The standard cell and the first basic cell are arranged in a part of the region where the standard cell and the first basic cell are not arranged, have a width smaller than the width of the first basic cell and larger than the width of the diode cell, and have no wiring layer. The semiconductor integrated circuit device according to claim 7, comprising a plurality of general-purpose second basic cells.

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