JP2000332206A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely prevent breakdown of a gate oxide film of a transistor which is caused by antenna effect, and/or breakdown of a transistor which caused by an electrostatic pulse, without increasing the area of an LSI chip. SOLUTION: A protective circuit 20, protecting a standard cell 32 from breakdown of a gate oxide film which is caused by antenna effect, is formed in a region 33 which is not yet used. The protective circuit 20 is arranged between a power source line VDD and a ground line GND, and an input terminal 39 is connected with a metal wiring layer 35. A protective circuit for protecting the standard cell 32 from breakdown of a transistor which is caused by an electrostatic pulse is scattered and formed in a plurality of region 33 which are not yet used, so that breakdown of a transistor which is to be caused by an electrostatic pulse can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device for preventing a gate oxide film and / or a transistor from being damaged by an electrostatic pulse.

[0002]

2. Description of the Related Art Destruction in a semiconductor integrated circuit device includes destruction in a wafer process and destruction in chip mounting after completion of a wafer.

In the manufacturing process of a semiconductor integrated circuit device, C
With respect to the metal wiring connected to the gate electrode of the MOS transistor, after the formation of the metal wiring, electric charges due to the antenna effect are accumulated when the interlayer insulating film is formed, and the electric charges may destroy the gate oxide film of the transistor (wafer). Destruction in the process). According to the above-described antenna effect, when a metal wiring is long during processing in a wafer state, the gate connected to the metal wiring is accumulated by electric charges at the time of processing, so that the gate is destroyed. In this case, when the other end of the metal wiring whose one end is connected to the gate is open, the antenna effect is increased.

Also, in a process before mounting the semiconductor integrated circuit device on a printed circuit board (hereinafter simply referred to as a substrate), an electrostatic pulse (ESD pulse) generated at an input / output terminal to the outside of the semiconductor integrated circuit device causes In some cases, the internal transistor is destroyed (destruction during chip mounting after completion of the wafer). Even if an electrostatic pulse protection circuit exists around the LSI chip, the internal circuit may be destroyed depending on the timing of applying the electrostatic pulse.

In order to prevent the destruction of the transistor due to the antenna effect, the CA of the semiconductor integrated circuit
Japanese Patent Application Laid-Open No. 6-61440 discloses a technique in which a cell having a known circuit configuration is added in the placement and routing step in the layout step processing by D and the generated charge passes through the substrate.

According to Japanese Patent Application Laid-Open No. 6-61440, a dedicated protection cell in which two protection diodes are connected in series is provided between a power supply line and a ground line in the vicinity of a cell to be protected. ing. The connection point of the protection diode and the gate of the transistor in the cell to be protected are connected to each other by a metal wiring. When an excessive voltage is applied to the metal wiring when the metal wiring has a length equal to or longer than a predetermined length, one of the protection diodes is turned on in accordance with the polarity of the excess voltage. Becomes substantially equal to the potential of the power supply line or the ground line. Thus, application of an excessive voltage to the gate of the transistor in the cell to be protected is prevented, and destruction of the transistor is prevented.

If the electric charge inputted from the outside is not stationary but pulse-like, an electrostatic pulse protection circuit provided in the periphery may operate depending on the change timing of the pulse at the time of input. Before the power supply, the ground line, or the signal line, the semiconductor device enters an internal circuit of the LSI chip, and the transistor of the internal circuit may be destroyed. Therefore, a technique for preventing a transistor from being destroyed by an electrostatic pulse between a signal line, a power supply line and a ground line is disclosed in Japanese Patent Laid-Open No. 6-177.
No. 361.

According to JP-A-6-177361,
A p-channel MOS transistor and an n-channel MOS transistor are used in an unused cell region not involved in a functional logic circuit in a semiconductor integrated circuit.
A channel MOS transistor is formed, the two MOS transistors are connected in series between a power supply line and a ground line, the gate terminal of the p-channel MOS transistor is connected to a power supply line, and the n-channel MOS transistor is connected to a power supply line. A protection circuit for connecting the gate terminal to the ground line is provided. When an electrostatic pulse is applied to the protection circuit, a pulse current flows in the order of a power supply line, a p-channel MOS transistor, an n-channel MOS transistor, and a ground line due to punch-through. It is possible to improve the withstand voltage of the entire semiconductor integrated circuit against electrostatic pulses without affecting the operation.

[0009]

However, the above prior art has the following problems.

That is, according to the prior art disclosed in JP-A-6-61440, a dedicated protection cell including a protection diode is provided in the vicinity of a cell to be protected. It is necessary to secure an area separately. Securing a region for separately arranging the protection cell in this way causes an increase in the area of the LSI chip.

The protection circuit disclosed in Japanese Patent Application Laid-Open No. Hei 6-177361 discloses an electrostatic pulse generated on a power supply line and a ground line around a functional logic circuit to be protected (not at a location separated from the functional logic circuit). , But cannot be protected against electrostatic pulses generated on the power supply line and the ground line at a location away from the functional logic circuit. In this regard, referring to FIG.
This will be described below.

When the power buffers 71 and 73 and the ground buffer 72 are arranged as shown in FIG.
The I chip 70 includes metal wiring 7 for supplying a power supply line and a ground line to a power supply buffer 71, a ground buffer 72, and an external input / output signal buffer (not shown).
Consists of four. The power buffer and the ground buffer
Usually, the above-described protection circuit for the electrostatic pulse is provided, and when an abnormal voltage is generated between the terminals of the adjacent power supply buffer 71 and the ground buffer 72, the protection circuit can pass the electric charge. It is possible.

However, the non-adjacent power supply buffer 73
When an abnormal potential difference is generated between the LSI chip 70 and the ground buffer 72, the arrangement of the standard cells substantially at the center of the LSI chip 70 is performed before the protection circuit provided around the LSI chip 70 operates via the metal wiring 74. An abnormal potential is applied to a transistor (not shown) in the functional logic circuit provided in the region 75 via a power supply line / ground line, and as a result, an abnormal charge is applied to the transistor. The transistor will be destroyed.

That is, when a transistor electrically connected via a power supply line and a ground line in the internal circuit is located at a position distant from the protection circuit, an external electrostatic pulse (abnormal charge) is applied. Depending on the timing at which the protection circuit is applied, the voltage may be applied to the transistor and destroyed without being absorbed by the protection circuit.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to reduce the gate oxide film of a transistor due to an antenna effect and / or reduce the static electricity without increasing the area of an LSI chip. It is an object of the present invention to provide a semiconductor integrated circuit device capable of reliably preventing a transistor from being destroyed due to a pulse.

[0016]

In order to solve the above-mentioned problems, a semiconductor integrated circuit device according to the present invention is provided with a plurality of standard cells corresponding to logic functions, and a gap is provided between the standard cells. The gap is an unused area where standard cells are not provided, and the following measures are taken in a semiconductor integrated circuit device in which metal wiring for electrically connecting standard cells is provided.

That is, in the semiconductor integrated circuit device, a part of the unused area is provided between a power supply line and a ground line, an input terminal is connected to the metal wiring, and a gate caused by an antenna effect. The antenna effect protection cell protects the standard cell from destruction of the oxide film.

According to the above invention, the standard cells corresponding to the logic function are connected to each other via the metal wiring provided in the unused area. Since this unused area is reserved in advance as an area required for metal wiring for electrically connecting the standard cells, no standard cell is provided.

A protection circuit is provided to prevent the gate oxide film of the transistor from being destroyed due to the antenna effect. For this purpose, conventionally, a separately provided area (between the standard cells) is provided near the standard cell to be protected. Area, which is not an unused area), and the area is increased by an amount corresponding to the arrangement area.

Therefore, according to the invention, a part of the unused area reserved for the metal wiring in which the standard cell is not provided protects the standard cell from the destruction of the gate oxide film due to the antenna effect. It is set as an antenna effect protection cell. As described above, since the antenna effect protection cell is provided in an unused area where the standard cell is not provided, it is not necessary to secure a separate area for disposing the antenna effect protection cell, and the semiconductor integrated circuit device is accordingly reduced. Is reliably prevented from increasing.

A metal wiring is connected to an input terminal of the antenna effect protection cell. When an excess potential is applied to the metal wiring, the excess potential is conducted to the antenna effect protection cell via the input terminal. In this case, destruction of the gate oxide film of the transistor due to the antenna effect can be avoided.

In the semiconductor integrated circuit device, in addition to the antenna effect protection cell, a part of the unused area is provided between a power supply line and a ground line to prevent a transistor from being destroyed due to an electrostatic pulse. In addition to providing an electrostatic protection cell for protecting the standard cell, a plurality of electrostatic protection cells are provided scattered in the plurality of unused areas.

In this case, in addition to the above operation, a plurality of electrostatic protection cells are scattered in the plurality of unused areas in an unused area reserved for metal wiring where no standard cell is provided. Therefore, without increasing the area of the semiconductor integrated circuit device, the electrostatic pulse generated on the power supply line and the ground line at a position distant from the functional logic circuit passes through the scattered electrostatic protection cells. As a result, the destruction of the transistor in the internal circuit can be reliably avoided.

As described above, according to the above-mentioned invention, in addition to the antenna effect protection, electrostatic pulse protection can be surely achieved for the standard cell, so that a highly reliable semiconductor integrated circuit having excellent protection coordination. Equipment can be provided.

Another semiconductor integrated circuit device according to the present invention comprises:
In order to solve the above-mentioned problem, a plurality of standard cells corresponding to a logic function are provided, and a gap is provided between the standard cells. The gap is an unused area where no standard cell is provided. The following measures are taken in a semiconductor integrated circuit device provided with a metal wiring for electrically connecting the semiconductor integrated circuit.

That is, in the semiconductor integrated circuit device, a part of the unused area is provided between a power supply line and a ground line to protect the standard cell from destruction of the transistor due to an electrostatic pulse. In addition to the electrostatic protection cells, a plurality of the electrostatic protection cells are scattered in the plurality of unused areas.

According to the above invention, the standard cells corresponding to the logic function are connected to each other via the metal wiring provided in the unused area. Since this unused area is reserved in advance as an area required for metal wiring for electrically connecting the standard cells, no standard cell is provided.

A protection circuit is provided in order to avoid destruction of the transistor due to the electrostatic pulse, but conventionally, the protection circuit is not provided in a scattered manner. For this reason, when a transistor electrically connected via the power supply line and the ground line is located at a position distant from the protection circuit, depending on the timing at which an external electrostatic pulse (abnormal charge) is applied, In the above protection circuit, the voltage is applied to the transistor and destroyed without being absorbed.

Therefore, according to the above invention, a plurality of electrostatic protection cells are scatteredly provided in a plurality of unused areas reserved for metal wiring where no standard cell is provided.
As described above, a plurality of electrostatic protection cells are scatteredly provided in a plurality of unused areas where the standard cells are not provided, so that the area of the semiconductor integrated circuit device does not increase, and furthermore, a portion separated from the functional logic circuit is provided. Since the electrostatic pulses generated in the power supply line and the ground line pass through the scattered electrostatic protection cells, it is possible to reliably avoid the destruction of the transistors in the internal circuit.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

The present invention relates to a standard cell-based semiconductor integrated circuit. In a semiconductor integrated circuit using a CMOS transistor, an unused area is used to increase the chip area without increasing a chip area, and to a gate electrode of a transistor in an internal circuit. To prevent the gate oxide film from being destroyed (antenna effect) due to the accumulation of electric charges and the above-mentioned transistor from being destroyed due to an electrostatic pulse.

A typical standard cell layout is performed as follows. That is, first, circuit design data having a desired logic function for realizing a semiconductor integrated circuit device is input, an arrangement row of standard cells is provided in an internal region of an LSI chip, and the arrangement row corresponds to the logic function. Each standard cell is arranged. In this arrangement, a gap is provided between the standard cells in consideration of the congestion degree of the signal wiring path in order to secure a region necessary for wiring between the input / output terminals of the standard cells in advance. This gap is not used as an area where standard cells are arranged, only metal wiring is formed, and becomes an unused area of standard cells.
By using a part of the unused area, the signal terminals of the standard cells are wired with a metal wiring layer.

A part of the unused area generated in the above layout is used as an antenna effect protection cell, and the remaining unused area is used as an ESD protection cell. A plurality of such ESD protection cells are provided dispersedly (scatteredly provided) so that ESD protection can be performed effectively and reliably.

Then, an input signal line composed of a metal wiring layer connected to the gate electrode of the standard cell and the antenna effect protection cell are wired via the metal wiring layer. As a result, an electric path for passing the charges generated due to the antenna effect is formed.

The protection circuit 20 provided in the antenna effect protection cell has a diode structure composed of a p-diffusion region and an n-diffusion region, and has a known circuit configuration for passing electric charges to a substrate. The protection circuit 20 includes, for example, a p-diffusion region and an n-type diffusion region as shown in the equivalent circuit of FIG.
It is composed of diodes 21 and 22 formed in the diffusion region. The diode 21 has a cathode connected to the power supply line VDD and an anode connected to the diode 22.
Connected to the cathode. The anode of the diode 22 is connected to the ground line GND. A connection point 23 between the anode of the diode 21 and the cathode of the diode 22 is electrically connected to the input signal line of the standard cell via the metal wiring layer.

The operation of the protection circuit 20 provided in the antenna effect protection cell will be described below with reference to FIG.

In the protection circuit 20, as shown in FIG. 2, the power supply line V is connected via the metal wiring layer (signal line).
When a voltage higher than DD is applied to the connection point 23, the diode 21 is biased in the forward direction and becomes conductive, so that the voltage at the connection point 23 becomes substantially equal to the power supply line VDD. On the other hand, when a voltage lower than the ground line GND is applied to the connection point 23 via the metal wiring layer, the diode 22 is biased in the forward direction and becomes conductive, so that the voltage at the connection point 23 becomes It is substantially equal to the ground line GND. As described above, even if an abnormal voltage is applied to the connection point 23 via the metal wiring layer, the connection point 23 is suppressed to the power supply line VDD or the ground line GND, thereby protecting the standard cell from the abnormal voltage. It is possible to do.

Since the diodes 21 and 22 are formed in the diffusion region of the unused region, they are compared with the prior art in which they are separately provided in another region (region other than the unused region) of the semiconductor integrated circuit device. Thus, the area occupied by the diode can be reliably reduced.

The above description is based on the protection circuit 20 shown in FIG.
Describes a case having a configuration including diodes 21 and 22 formed in a p diffusion region and an n diffusion region, but the present invention is not limited to this.
A configuration may be made of any one diode of the p diffusion region and the n diffusion region.

As shown in FIG. 3, the protection circuit 10 provided in the ESD protection cell has a drain electrode connected to the power supply line VDD, a gate electrode connected to the ground line GND using a metal wiring layer, and a source It comprises an n-channel MOS transistor 11 whose electrode is connected to the ground line GND, and a diode 14 whose cathode is connected to the power supply line VDD, whose anode is connected to the ground line GND, and which is provided in the diffusion region.

The operation of the protection circuit 10 provided in the ESD protection cell will be described below with reference to FIG.

When a positive electrostatic pulse is applied between the power supply line VDD and the ground line GND in the protection circuit 10, punch-through causes the power supply line VDD, the n-channel MOS transistor 11, and the ground line GND in this order. A pulse current flows, which makes it possible to improve the withstand voltage of the entire semiconductor integrated circuit with respect to the electrostatic pulse without affecting the operation of the nearby standard cell. When a negative electrostatic pulse is applied between the power supply line VDD and the ground line GND, the diode 1
4 is biased in the forward direction and becomes conductive, so that a pulse current flows in the order of the ground line GND, the diode 14, and the power supply line VDD, thereby not affecting the operation of the standard cell in the vicinity, and It is possible to improve the withstand voltage against the electrostatic pulse.

According to the protection circuit 10, before the semiconductor integrated circuit device is mounted on the substrate, when the terminals are floating, an abnormal potential difference is generated between the power supply line VDD and the ground line GND in a pulsed manner. In this case, a pulse current flows in the order of the power supply line VDD, the n-channel MOS transistor 11, and the ground line GND due to punch-through, thereby preventing the operation of the nearby standard cell from being affected.

Further, since the n-channel MOS transistor 11 and the diode 14 are formed scattered in a plurality of unused areas, a plurality of n-channel MOS transistors 11 and diodes 14 are generated by an electrostatic pulse generated on the power supply line and the ground line at a location away from the functional logic circuit. It becomes possible to protect the standard cell from the destruction of the transistor in the internal circuit. The above n
Channel MOS transistor 11 and diode 14
Are formed in the diffusion region of the unused region, so that the area occupied in the diode formation can be reduced as compared with the related art in which these are separately provided in other regions of the semiconductor integrated circuit device.

Here, the present embodiment will be described below with reference to FIGS. 1, 4 and 5.

FIG. 4 shows an example of a typical layout of a semiconductor integrated circuit device. The standard cell arrangement region 30 is composed of arrangement columns 31 in which standard cells 32 are to be arranged, and standard cells 32 for realizing a logical function are arranged in each arrangement column 31. In the arrangement column 31, there are unused areas 33 in which the standard cells 32 are not arranged, and a part thereof is used for wiring. In the wiring step, the multilayer metal wiring layers 35 and 36 are formed.
Thus, connection is made to the input terminal 39 and the output terminal 38 of the standard cell 32. At this time, if the metal wiring layer 35 formed first in the manufacturing process among the multiple metal wiring layers is connected to the gate electrode which is the input terminal of the standard cell, the length of the metal wiring layer 35 is long. An antenna effect occurs on the metal wiring layer 35, and electric charges are accumulated in the metal wiring layer 35. The charge thus accumulated does not have an electric path to the drain or source electrode connected to the substrate region, and thus causes the gate oxide film of the transistor which is the input of the standard cell to be destroyed.

Therefore, the semiconductor integrated circuit device according to the present embodiment has a layout as shown in FIG.
According to the layout of FIG. 1, similarly to FIG. 4, the standard cell arrangement region 30 is composed of arrangement columns 31 in which standard cells 32 are to be arranged. Cells 32 and unused areas 33 where the standard cells 32 are not provided.
Exists. In this unused area 33, an antenna effect protection cell having the protection circuit 20 of FIG. 2 is arranged so as to be in the vicinity of the standard cell to be protected, and the metal wiring layer 35 is connected to the gate electrode in the wiring step. The input terminal 39 of the cell 32 and the neighboring antenna effect protection cell are connected by the metal wiring layer 35. The connected antenna effect protection cell is, as shown in FIG.
DD and the ground line GND. Therefore, the operation of the internal circuit is not logically affected to achieve a desired logical function.

As described above, when the protection circuit 20 is formed in the antenna effect protection cell, the protection circuit 10 is formed in the ESD protection cell as follows. This will be described below with reference to FIG.

Basically, the protection circuits 10 are scattered over unused areas other than the antenna effect protection cells provided with the protection circuits 20 and dispersed so that effective and reliable ESD protection can be performed. Provided (scattered). As described above, since the plurality of the protection circuits 10 are formed dispersedly (scattered) in a plurality of unused areas, the protection circuits 10 are caused by electrostatic pulses generated in the power supply line and the ground line at a location apart from the functional logic circuit. The standard cell 32 can be protected from the destruction of the transistor in the internal circuit. Further, since the n-channel MOS transistor 11 and the diode 14 are formed in the diffusion region of the unused region, the area occupied by the diode can be reliably reduced.

As shown in FIG. 5, in a large unused area, both an antenna effect protection cell and an ESD protection cell may be provided in one unused area.
That is, both the protection circuit 10 and the protection circuit 20 may be provided in one unused area.

According to the semiconductor integrated circuit device of the present invention, the LS
It is premised that the ESD protection circuit is provided around the I chip. As described above, not only the area around the LSI chip but also the area where the logic circuits and the like inside the LSI chip are provided (configured with a standard cell column). ), A protection circuit (an antenna effect protection cell and a protection circuit provided in an ESD protection cell different from the above-mentioned ESD protection circuit around the LSI chip) are separately provided.

The antenna effect protection cell is used to prevent a charge from being accumulated in the metal wiring connected to the gate of the transistor in the wafer process, thereby preventing the gate from being destroyed. When the ESD protection circuit around the LSI chip operates, for example, when static electricity is applied in a pulsed manner from the outside at the time of mounting the chip, the static electricity is applied to the signal line, the power supply line, and the like.
In order to prevent the internal transistors and the like from being destroyed by being transmitted to the internal circuit through the ground line and the like, the internal protection is provided for each of them.

Each of the above protection circuits is provided in a gap (unused area) in the standard cell row inside the LSI chip. As described above, since the unused area which has not been used conventionally is used, desired effects can be respectively obtained without increasing the area of the LSI chip. In particular, the ESD protection cells are dispersed and provided so as to provide effective and reliable ESD protection in a scattered manner, so that the electrostatic pulse generated on the power supply line and the ground line at a position away from the functional logic circuit can be obtained. Pass through the ESD protection cell, it is possible to protect the transistor of the internal circuit from destruction.

As described above, according to the semiconductor integrated circuit device described above, the gate oxide film is broken during the formation of the metal wiring in the manufacturing process, and the power supply line (power supply terminal) and the ground line (ground) are generated during the mounting process. Destruction of a transistor due to an electrostatic pulse between the
It is possible to reliably avoid the problem without increasing the chip area.

[0055]

As described above, in the semiconductor integrated circuit device according to the present invention, a part of the unused area is provided between the power supply line and the ground line, and the input terminal is connected to the metal wiring. In addition, the antenna effect protection cell protects the standard cell from destruction of the gate oxide film caused by the antenna effect.

Therefore, an antenna effect protection cell for protecting the standard cell from the destruction of the gate oxide film due to the antenna effect is provided in the unused area reserved for the metal wiring where no standard cell is provided. Therefore, it is not necessary to separately secure an area for disposing the antenna effect protection cell, and it is possible to reliably avoid an increase in the area of the semiconductor integrated circuit device.

Moreover, a metal wiring is connected to the input terminal of the antenna effect protection cell, and when an excess potential is applied to this metal wiring, the excess potential is applied to the antenna effect protection cell via the input terminal. This leads to the effect that the gate oxide film of the transistor due to the antenna effect can be avoided beforehand.

In the semiconductor integrated circuit device, in addition to the antenna effect protection cell, a part of the unused area is provided between a power supply line and a ground line to prevent the transistor from being destroyed due to an electrostatic pulse. It is preferable that the standard cell is used as an electrostatic protection cell for protecting the standard cell, and a plurality of the electrostatic protection cells are scattered in the plurality of unused areas.

Therefore, in addition to the above-described effects, a plurality of electrostatic protection cells are scattered in the plurality of unused areas and provided in the unused area reserved for the metal wiring where no standard cell is provided. Therefore, without increasing the area of the semiconductor integrated circuit device, the electrostatic pulses generated on the power supply line and the ground line at a position distant from the functional logic circuit cause the electrostatic protection cells provided in a scattered manner. Since it passes through, the destruction of the transistor in the internal circuit can be reliably avoided.

In addition, since electrostatic pulse protection can be reliably achieved in addition to antenna effect protection for standard cells, a highly reliable semiconductor integrated circuit device having excellent protection coordination can be provided. Play.

Another semiconductor integrated circuit device according to the present invention comprises:
As described above, a plurality of standard cells corresponding to the logic function are provided, a gap is provided between the standard cells, and the gap is an unused area where the standard cells are not provided. In a semiconductor integrated circuit device provided with a metal wiring connected to a power supply line, a part of an unused area is provided between a power supply line and a ground line to protect a standard cell from destruction of a transistor caused by an electrostatic pulse. In addition to the electrostatic protection cells, a plurality of the electrostatic protection cells are scattered in the plurality of unused areas.

Therefore, since a plurality of electrostatic protection cells are scattered and provided in a plurality of unused areas reserved for metal wiring where no standard cell is provided, the area of the semiconductor integrated circuit device increases. In addition, since the electrostatic pulses generated on the power supply line and the ground line at a position distant from the functional logic circuit pass through the scattered electrostatic protection cells, the transistor in the internal circuit is surely destroyed. In addition, it is possible to avoid the problem.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a protection circuit provided in an antenna effect protection cell of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is an equivalent circuit diagram of the protection circuit.

FIG. 3 is an equivalent circuit diagram of a protection circuit provided in the ESD protection cell of the semiconductor integrated circuit device according to the present invention.

FIG. 4 is an explanatory diagram illustrating a layout of a typical semiconductor integrated circuit device.

FIG. 5 is an explanatory diagram illustrating a layout of the protection circuit provided in the antenna effect protection cell and the protection circuit provided in the ESD protection cell.

FIG. 6 is an explanatory diagram for explaining a conventional problem.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 protection circuit 11 n-channel MOS transistor 14 diode 20 protection circuit 23 connection point 30 standard cell arrangement area 31 arrangement row 32 standard cell 33 unused area 35 metal wiring layer 36 metal wiring layer 38 output terminal 39 input terminal

Claims (3)

[Claims] A plurality of standard cells corresponding to a logic function are provided, and a gap is provided between the standard cells. The gap is an unused area where no standard cell is provided. A part of the unused area is provided between a power supply line and a ground line, an input terminal is connected to the metal wiring, and a part of the unused area is caused by an antenna effect. A semiconductor integrated circuit device comprising an antenna effect protection cell for protecting the standard cell from destruction of the gate oxide film. 2. A method according to claim 1, wherein a plurality of standard cells corresponding to the logic function are provided, and a gap is provided between the standard cells. The gap is an unused area where the standard cells are not provided. A part of the unused area is provided between a power supply line and a ground line to protect the standard cell from destruction of a transistor due to an electrostatic pulse. And a plurality of said electrostatic protection cells are scatteredly provided in said plurality of unused areas. 3. An electrostatic protection cell provided between a power supply line and a ground line to protect the standard cell from destruction of a transistor caused by an electrostatic pulse. 2. A plurality of said electrostatic protection cells are scattered in said plurality of unused areas.
3. The semiconductor integrated circuit device according to 1.