JP3932896B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device provided with an electrostatic discharge protection circuit that prevents internal circuits from being destroyed by electrostatic discharge, and a semiconductor device having a plurality of different types of power supply systems.
[0002]
[Prior art]
FIG. 5 is a schematic block diagram showing an example of a conventional semiconductor device provided with an electrostatic discharge protection circuit.
In FIG. 5, reference numeral 1 indicates a pad, reference numeral Qn indicates an n-type MOS transistor, reference numeral Qp indicates a p-type MOS transistor, reference numeral R indicates a protective resistor, and reference numeral 2 indicates an internal circuit.
[0003]
The signal wiring of the internal circuit 2 is connected to the pad 1 through the protective resistor R. When the pad 1 is electrically connected to a pin exposed outside the package, the signal wiring of the internal circuit 2 is drawn out of the apparatus. The connection line between the pad 1 and the protection resistor R is connected to the reference potential Vss via the drain-source terminal of the n-type MOS transistor Qn and to the power supply Vdd via the drain-source terminal of the p-type MOS transistor Qp. Connected.
[0004]
According to the semiconductor device shown in FIG. 5, when the potential of the pad 1 becomes higher than the power supply Vdd by the threshold voltage of the p-type MOS transistor Qp due to electrostatic discharge, the p-type MOS transistor Qp becomes conductive. The increase in potential is suppressed. Further, when the potential of the pad 1 becomes lower than the reference potential Vss by the threshold voltage of the n-type MOS transistor Qn due to electrostatic discharge, the n-type MOS transistor Qn becomes conductive, so that the potential drop of the pad 1 is suppressed. . Since the voltage fluctuation range of the pad 1 is limited in this way, the internal circuit 2 is prevented from being destroyed by electrostatic discharge.
[0005]
FIG. 6 is a diagram showing an example of a conventional layout of the semiconductor device shown in FIG.
In FIG. 6, reference numeral 11 denotes a semiconductor substrate, reference numeral 12 denotes a p-type impurity region, reference numeral 13 denotes an n-type impurity region, reference numeral 14 denotes an n-type or p-type impurity region, and reference numeral 15 denotes a polycrystalline silicon film. Reference numeral 21 denotes a second layer wiring, reference numeral 31 denotes a third layer wiring, and reference numeral 41 denotes a fourth layer wiring.
FIG. 7 is a cross-sectional view of the semiconductor device taken along the dotted line A-A ′ in FIG. 6 as viewed from the direction of the arrow a.
7 and 6 indicate the same components. In FIG. 7, reference numeral 16 denotes a gate electrode, reference numeral 17 denotes an n-type impurity region, reference numeral 18 denotes a p-type impurity region, reference numeral 50 denotes an interlayer insulating film, and reference numeral 60 denotes a via.
[0006]
As shown in FIGS. 6 and 7, the pad 1 is in the region A1, the n-type MOS transistor Qn is in the region A2, the p-type MOS transistor Qp is in the region A3, the resistor R is in the region A4, and the region A5 is The internal circuits 2 are formed respectively.
[0007]
In the region A1, rectangular electrodes 41 are formed on the second wiring layer and the fourth wiring layer, and the third layer wiring 31 extending from the regions A3 and A2 and these electrodes 41 are connected by a via 60. The
[0008]
In the region A <b> 2, the fourth layer wiring 42 that is a wiring of the reference potential Vss is formed extending in a direction perpendicular to the third layer wiring 31. A p-type impurity region 12 extending in the same direction as the fourth layer wiring 42 is formed on the semiconductor substrate 11 facing the fourth layer wiring 42.
[0009]
A gate electrode 16 is formed on the p-type impurity region 12 via a gate insulating film, and an n-type serving as a source or drain of the n-type MOS transistor Qn with a channel formation region facing the gate electrode 16 interposed therebetween. Impurity region 17 is formed.
The n-type impurity region 17 serving as a source is connected to the second layer wiring 21 through the via 60, and this second layer wiring 21 is further connected to the third layer wiring 31 through the via 60.
The n-type impurity region 17 and the gate electrode 16 serving as the drain are connected to the same second layer wiring 21 via the via 60, and the second layer wiring 21 is further connected to the third layer wiring and the via 60 (not shown). Thus, it is connected to the fourth layer wiring 42 which is a wiring of the reference potential Vss. In the example of FIG. 7, the p-type impurity region 18 formed in the p-type impurity region 12 and the gate electrode 16 are connected to the common second layer wiring 21. Thereby, the potential of the p-type impurity region 12 is fixed to the reference potential Vss.
[0010]
In the region A3, the fourth layer wiring 43 that is the wiring of the power supply Vdd is formed to extend in a direction parallel to the fourth layer wiring. On the semiconductor substrate 11 facing the fourth layer wiring 43, an n-type impurity region 13 extending in the same direction as the fourth layer wiring 43 is formed.
[0011]
A gate electrode 16 is formed on the n-type impurity region 13 via a gate insulating film, and a p-type serving as a source or drain of the p-type MOS transistor Qp with a channel formation region facing the gate electrode 16 interposed therebetween. Impurity region 18 is formed. The p-type impurity region 18 serving as a source is connected to the second layer wiring 21 via the via 60, and this second layer wiring 21 is further connected to the third layer wiring 31 via the via 60.
[0012]
The p-type impurity region 18 serving as the drain and the gate electrode 16 are connected to the same second layer wiring 21 through a via 60, and the second layer wiring 21 is further connected to a third layer wiring and a via 60 (not shown). Then, it is connected to the fourth layer wiring 43 which is the wiring of the power supply Vdd. In the example of FIG. 7, the n-type impurity region 17 formed in the n-type impurity region 13 and the gate electrode 16 are connected to the common second layer wiring 21. As a result, the potential of the n-type impurity region 13 is fixed to the power supply Vdd.
[0013]
In the region A4, one end of the resistor R formed by the polycrystalline silicon film 15 formed on the semiconductor substrate 11 and the third layer wiring 31 are connected via the via 60 and the second layer wiring 21. The other end of polycrystalline silicon film 15 is connected to a wiring extending from internal circuit 2 in region A5.
[0014]
Next, a conventional semiconductor device having a plurality of different types of power supply systems will be described.
FIG. 8 is a diagram showing an example of a layout in the vicinity of a pad in a conventional semiconductor device having two power supply systems.
8 and 5 indicate the same components. In FIG. 8, reference numeral 24 denotes a second layer wiring of the reference potential Vss1, reference numeral 26 denotes a second layer wiring of the reference potential Vss2, and reference numeral 27 denotes a second layer wiring of the power source Vdd2. Connected directly to internal circuitry.
Reference numeral 44 denotes a fourth layer wiring of the reference potential Vss1, reference numeral 45 denotes a fourth layer wiring of the power supply Vdd1, reference numeral 46 denotes a fourth layer wiring of the reference potential Vss2, and reference numeral 47 denotes a fourth layer wiring of the power supply Vdd2. The pads are formed by these wirings.
[0015]
In the layout example of FIG. 8, a power supply Vdd1-related pad is formed in region A6 and region A10, and a power supply Vdd2-related pad is formed in region A8 between region A6 and region A10.
[0016]
Further, the pad of the reference potential Vss1 in the region A6 and the pad of the reference potential Vss2 in the region A8 are adjacent to each other across the region A7, and these two pads are formed by a bidirectional parallel diode formed in the region A7. Connected to each other.
[0017]
Similarly, the pad of the reference potential Vss1 in the region A10 and the pad of the power supply Vdd2 in the region A8 are adjacent to each other across the region A9, and these two pads are connected to each other by a diode formed in the region A9. . In the example of FIG. 8, the reference potential Vss1 is connected to the anode side of the diode, and the power supply Vdd2 is connected to the cathode side.
[0018]
FIG. 9 is a cross-sectional view of the semiconductor device taken along the dotted line B-B ′ in FIG. 8.
The same reference numerals in FIG. 9, FIG. 7 and FIG. 8 denote the same components. In addition, in FIG. 9, the code | symbol 34 shows the 3rd layer wiring of the reference electric potential Vss1, the code | symbol 36 shows the 3rd layer wiring of the reference electric potential Vss2, and the code | symbol 37 shows the 3rd layer wiring of the power supply Vdd2.
[0019]
As shown in FIG. 9, the electrode of each pad formed in the fourth wiring layer is connected to the second layer wiring or the third layer wiring connected to the internal circuit via the via 60.
In addition, between the pads of different power supply systems, there is an empty area where no circuit is formed because of the area A7 and the area A9 where the diodes connecting these pads are formed.
[0020]
In general, a sensitive signal processing circuit that causes malfunctions due to noise generated in the main logic circuit that operates with a high-speed clock signal is different from the common power supply that is supplied to the main circuit that generates the noise. A power supply may be used. In this case, such a small independent power supply system has a smaller capacitance component between the power supply and the reference potential than a large common power supply system, and has fewer electrostatic discharge protection circuits than the common power supply system. When this occurs, the circuit voltage tends to be larger than that of the common power supply system. That is, a small-scale independent power supply system circuit has a small electrostatic resistance and is easily destroyed as compared with a large-scale common power supply system circuit.
[0021]
In order to solve such a problem, for example, a bidirectional parallel diode is inserted between reference potentials or power supply potentials of different power supply systems as in the semiconductor device shown in FIGS. A diode may be inserted between the reference potential of the system and the power supply potential of the other power supply system.
[0022]
If the voltage of the noise component is smaller than the forward voltage of the diode, the diode has a high impedance with respect to the noise component, so that noise mixing between different power supply systems is prevented.
[0023]
On the other hand, when electrostatic discharge occurs, the diode is turned on by the large voltage, so that the reference potential or the power supply potential connected by the bidirectional parallel diode is electrically connected to each other. Thereby, since the electrostatic discharge protection circuit of both power supply systems is shared, the electrostatic tolerance of the independent power supply system and the common power supply system can be made comparable.
In addition, because of the diode connected between the reference potential of one power supply system and the power supply potential of the other power supply system, part of the surge current of electrostatic discharge flowing from the pad of the independent power supply system also flows to the common power supply system. The voltage rise in the independent power supply circuit can be suppressed.
[0024]
[Problems to be solved by the invention]
By the way, in each of the conventional semiconductor devices described above, an electrostatic discharge protection circuit and a diode are added as countermeasures against electrostatic discharge, so that an extra area is required to form these additional circuits, and the circuit area is enlarged. There is a problem that becomes.
[0025]
For example, in the conventional layout example shown in FIG. 6, since an area corresponding to two transistors is required for one pad, if these pads are formed on each side of the semiconductor chip, the vertical direction Further, an extra area for four transistors is required for each of the lateral directions.
[0026]
Further, as can be seen from the cross-sectional view of FIG. 9, in the conventional layout example shown in FIG. 8, since a diode region to be inserted between different power supply systems is provided, a circuit like the region A7 or the region A9 is not formed. A wasted area is born between the pads. The number of input / output pins tends to increase year by year as ICs become more sophisticated, and the existence of such a useless region between pads increases the circuit area or restricts the number of pins. There's a problem.
[0027]
The present invention has been made in view of such circumstances, and a first object of the present invention is to provide a semiconductor device capable of reducing the area of a circuit as compared with the prior art.
A second object is to provide a semiconductor device capable of reducing a useless region where a circuit is not formed and improving the degree of circuit integration.
[0028]
[Means for Solving the Problems]
  To achieve the above objectives,The semiconductor device according to the present invention includes a first pad for drawing out a first power supply line or a reference potential line corresponding to the first power supply line to the outside of the device, a second power supply line or the second power supply line. A second pad for drawing out a reference potential line corresponding to the power supply line to the outside of the device and at least a part thereof are formed on the first pad or the semiconductor substrate immediately below the second pad, and the first pad And at least one diode connected between the second pad and the second pad.
[0032]
  Main departureClearlyAccording to the semiconductor device, the first pad or the second padDirectly underAt least one diode connecting the first pad and the second pad is formed on the semiconductor substrate. The diode is in a high impedance state with respect to noise lower than the threshold voltage of the diode, and noise propagation between the first power supply system and the second power supply system is suppressed. When a large voltage is generated due to electrostatic discharge, the diode is turned on, and a surge current flowing into one power supply system also flows into the other power supply system, thereby suppressing an increase in circuit voltage due to the surge current. In addition, since it is not necessary to provide a region for forming the diode between the first pad and the second pad, a useless region where a circuit is not formed between the pads is reduced.
[0033]
  The diode is a parallel diode in which a plurality of diodes are connected in parallel in opposite directions, and the first pad connected to the first power supply line and the second pad connected to the second power supply line. And parallel diode to connectWhenAt least one of the parallel diodes connecting the first pad connected to the reference potential line corresponding to the first power supply line and the second pad connected to the reference potential line corresponding to the second power supply line EitherButgood.
  The diode connects the first pad connected to the first power supply line and the second pad connected to the reference potential line corresponding to the second power supply line.When, At least one of the diodes connecting the first pad connected to the reference potential line corresponding to the first power supply line and the second pad connected to the second power supply lineButgood.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, the present inventionReference formas well asFirst embodimentWill be described with reference to the drawings.
<Reference form>
  FIG. 1 illustrates the present invention.Reference form2 is a schematic diagram illustrating an example of a circuit configuration and a layout of a semiconductor device according to FIG. 1 and 6 indicate the same components.
  FIG. 2 is a cross-sectional view of the cross section of the semiconductor device taken along the dotted line C-C ′ in FIG. 2 and 7 indicate the same components.
[0035]
As shown in FIGS. 1 and 2, pad 1 and n-type MOS transistor Qn are provided in region A11, p-type MOS transistor Qp is provided in region A12, resistance R is provided in region A13, and internal circuit 2 is provided in region A14. Are formed respectively.
[0036]
In the region A11, a pad is formed on the fourth wiring layer by a rectangular electrode 41, and the third layer wiring 31 extending from the region A12 and the electrode 41 are connected via a via 60.
[0037]
A p-type impurity region 12 of the n-type MOS transistor Qn is formed on the semiconductor substrate 11 facing the electrode 41 forming the pad and adjacent to the region A12. A gate electrode 16 is formed on the p-type impurity region 12 via a gate insulating film, and n serving as a source or drain of the n-type MOS transistor Qn across the channel formation region facing the gate electrode 16. A type impurity region 17 is formed.
[0038]
The n-type impurity region 17 serving as the source of the n-type MOS transistor Qn is connected to the second layer wiring 23 formed facing the electrode 41 forming the pad through a via 60. Further, the second layer wiring 23 is connected to a third layer wiring 31 extending below the electrode 41 forming the pad via a via 60.
[0039]
The n-type impurity region 17 and the gate electrode 16 serving as the drain of the n-type MOS transistor Qn face the electrode 41 forming the pad, and are connected to the second-layer wiring 22 formed adjacent to the second-layer wiring 23, and the vias. 60 is connected. Further, the second layer wiring 22 is connected to a fourth layer wiring 42 which is a wiring of the reference potential Vss through a third layer wiring and via 60 (not shown). The fourth layer wiring 42 is formed adjacent to the electrode 41 forming the pad and extending in a direction perpendicular to the third layer wiring 31.
[0040]
In the example of FIG. 2, the p-type impurity region 18 formed in the p-type impurity region 12 and the gate electrode 16 are connected to the common second layer wiring 22. Thereby, the potential of the p-type impurity region 12 is fixed to the reference potential Vss.
[0041]
In region A12, n-type impurity region 13 of p-type MOS transistor Qp is formed on the semiconductor substrate adjacent to p-type impurity region 12.
A gate electrode 16 is formed on the n-type impurity region 13 via a gate insulating film, and a p-type MOS transistor Qp serving as the source or drain of the p-type MOS transistor Qp is sandwiched by a channel formation region facing the gate electrode 16. A type impurity region 18 is formed.
[0042]
The p-type impurity region 18 serving as the source of the p-type MOS transistor Qp is connected to the second layer wiring 21 via the via 60, and this second layer wiring 21 is further connected to the third layer wiring 31 via the via 60. Is done.
[0043]
The p-type impurity region 18 and the gate electrode 16 serving as the drain of the p-type MOS transistor Qp are connected to the same second layer wiring 21 via the via 60, and this second layer wiring 21 is further connected to a third layer (not shown). The wiring and via 60 are connected to the fourth layer wiring 43 which is the wiring of the power supply Vdd. The fourth layer wiring 43 is formed adjacent to the fourth layer wiring 42 and extending in the same direction.
[0044]
In the example of FIG. 7, the n-type impurity region 17 formed in the n-type impurity region 13 and the gate electrode 16 are connected to the common second layer wiring 21. As a result, the potential of the n-type impurity region 13 is fixed to the power supply Vdd.
[0045]
In the region A <b> 13, one end of the resistor R formed by the polycrystalline silicon film 15 formed on the semiconductor substrate 11 and the third layer wiring 31 are connected via the via 60 and the second layer wiring 21. The other end of polycrystalline silicon film 15 is connected to a wiring extending from internal circuit 2 in region A14.
[0046]
According to the semiconductor device of FIG. 1 described above, even if the potential of the pad 1 fluctuates due to electrostatic discharge, the p-type MOS transistor Qp or the n-type MOS transistor Qn becomes conductive and the surge current is supplied to the power supply Vdd or the reference potential Vss. Since the voltage fluctuation range of the pad 1 is limited, destruction of the internal circuit 2 due to electrostatic discharge is prevented.
[0047]
Further, as can be seen from comparison with the conventional layout example shown in FIGS. 6 and 7, in the conventional example, the region A2 where the n-type MOS transistor Qn is formed and the region A1 where the pad is formed are shown in FIG. And in the layout example of FIG. Therefore, according to the above layout example, an area corresponding to about one transistor can be reduced as compared with the conventional example.
[0048]
If the pad area compared to the transistor area is larger than the layout example of FIGS. 1 and 2, the p-type MOS transistor Qp in addition to the n-type MOS transistor Qn may be formed below the pad. it can. If there is more space, the protective resistor R can be formed below the pad.
As described above, the circuit area can be reduced by forming the electrostatic discharge protection circuit in the region under the pad that has not been conventionally used.
[0049]
In addition, since the electrostatic discharge protection circuit is formed closer to the pad than in the prior art, surge current can be more effectively passed to the electrostatic discharge protection circuit, and resistance to electrostatic discharge can be improved.
[0050]
<First 1 Embodiment of>
  Next, the present inventionFirst 1 Embodiment ofWill be described.
  FIG. 3 illustrates the present invention.First 1 Embodiment ofIt is a schematic diagram showing an example of the layout of the semiconductor device according to the. The same reference numerals in FIG. 3, FIG. 8 and FIG. 9 denote the same components.
[0051]
In the region A15 and the region A19, a rectangular electrode 41 is formed on the fourth wiring layer as a signal pad of the power supply Vdd1 system, and a third layer wiring 31 connecting the electrode 41 and the internal circuit is formed. A polycrystalline silicon film 15 is formed on the semiconductor substrate 11 as a protective resistor inserted in series on the connection line between the signal pad and the internal circuit. In the upper layer of the third layer wiring 31, a fourth layer wiring 45 connected to the power source Vdd1 and a fourth layer wiring 44 connected to the reference potential Vss1 of the power source Vdd1 system extend in a direction perpendicular to the third layer wiring 31. It is formed.
[0052]
Similarly, in the region A17, a rectangular electrode 41 is formed in the fourth wiring layer as a signal pad for the power supply Vdd2 system, and a third layer wiring 31 that connects the electrode 41 and the internal circuit is formed. A polycrystalline silicon film 15 is formed on the semiconductor substrate 11 as a protective resistor inserted in series on the connection line between the signal pad and the internal circuit. Above the third layer wiring 31, a fourth layer wiring 47 connected to the power supply Vdd2 and a fourth layer wiring 46 connected to the reference potential Vss2 of the power supply Vdd2 system extend in a direction perpendicular to the third layer wiring 31. It is formed.
[0053]
Note that an internal circuit is protected from electrostatic discharge below the third-layer wiring 31 connecting the electrode 41 and the polycrystalline silicon film 15 as in, for example, the n-type MOS transistor and the p-type MOS transistor Qp in FIG. A circuit may be formed. Further, as shown in the example of FIG. 2, at least a part of the electrostatic discharge protection circuit may be formed under the electrode 41.
[0054]
In the region A16 sandwiched between the region A15 and the region A17, a power supply pad of the reference potential Vss1 is formed on the fourth layer wiring 44 adjacent to the region A15, and adjacent to the region A17. A power pad is formed on the fourth layer wiring 46. In the example of FIG. 3, the interval between the two pads is approximately the same as the pad interval in the same power supply system.
In the example of FIG. 3, the fourth layer wiring 44 formed with the power supply pad of the reference potential Vss1 is connected to the internal circuit via the second layer wiring 24. The fourth layer wiring 46 on which the power supply pad of the reference potential Vss2 is formed is connected to the internal circuit via the third layer wiring 36.
[0055]
In addition, parallel diodes connected in parallel in opposite directions are formed below the two pads in the region A16. The pad of the reference potential Vss1 and the pad of the reference potential Vss2 are connected to each other through this parallel diode.
[0056]
In a region A18 sandwiched between the region A17 and the region A19, a power supply pad for the power supply Vdd2 is formed on the fourth layer wiring 47 adjacent to the region A17, and a power supply pad for the reference potential Vss1 is adjacent to the region A19. Is formed on the fourth-layer wiring 44. In the example of FIG. 3, the interval between the two pads is also the same as the pad interval in the same power supply system.
In the example of FIG. 3, the fourth layer wiring 47 in which the power supply pad for the power supply Vdd <b> 2 is formed is connected to the internal circuit via the third layer wiring 37. The fourth layer wiring 44 on which the power supply pad of the reference potential Vss1 is formed is connected to the internal circuit through the second layer wiring 24.
[0057]
In addition, a diode connected to the two pads is formed in the forward direction from the reference potential Vss1 to the power source Vdd2 below the two pads in the region A18.
[0058]
4 is a cross-sectional view of the cross section of the semiconductor device taken along the dotted line D-D ′ in FIG. 3 from the direction of the arrow d, and the same reference numerals in FIGS. 4 and 7 to 9 indicate the same components.
In the region A15, the region A17, and the region A19, the third layer wiring 31 and the second layer wiring 21 are formed in the lower layer of the electrode 41 forming the signal pad, and each is connected through the via 60. In the example of FIG. 4, the second layer wiring 31 is connected to an internal circuit.
[0059]
In the region A16, an n-type impurity region is formed on the semiconductor substrate 11 facing the electrode 44 that forms the power supply pad of the reference potential Vss1 and on the semiconductor substrate 11 facing the electrode 46 that forms the power supply pad of the reference potential Vss2. 13 is formed.
[0060]
In the region A <b> 16, the electrode 44 is connected to the third layer wiring 34 through the via 60 and further connected to the second layer wiring 24 through the via 60.
The second layer wiring 24 is a part of the upper layer region facing the two n-type impurity regions 13 and is formed in a region on the internal circuit side. Vias 60 are respectively formed in the p-type impurity region 18 formed on the n-type impurity region 13 facing the electrode 44 and the n-type impurity region 17 formed on the n-type impurity region 13 facing the electrode 46. Connected through.
In the example of FIGS. 3 and 4, the second layer wiring 24 is formed extending in the direction of the internal circuit, whereby the power supply pad of the reference potential Vss1 and the internal circuit are connected.
[0061]
In the region 16, the electrode 46 is connected to the third layer wiring 36 through the via 60 and further connected to the second layer wiring 26 through the via 60.
The second layer wiring 26 is a part of the upper layer region facing the two n-type impurity regions 13 and is formed adjacent to the above-described second layer wiring 24 in a region on the outer peripheral side of the semiconductor chip. Vias 60 are respectively formed in the n-type impurity region 17 formed on the n-type impurity region 13 facing the electrode 44 and the p-type impurity region 18 formed on the n-type impurity region 13 facing the electrode 46. Connected through.
In the example of FIGS. 3 and 4, the third layer wiring 36 is formed extending in the direction of the internal circuit, whereby the power supply pad of the reference potential Vss2 and the internal circuit are connected.
[0062]
In the region A18, the n-type impurity regions 13 are respectively formed on the semiconductor substrate 11 facing the electrode 44 forming the power supply pad of the reference potential Vss1 and on the semiconductor substrate 11 facing the electrode 47 forming the power supply pad of the power supply Vdd2. Is formed.
[0063]
In the region A 18, the electrode 44 is connected to the third layer wiring 34 through the via 60 and further connected to the second layer wiring 24 through the via 60.
The second layer wiring 24 is a part of the upper layer region facing the two n-type impurity regions 13 and is formed in a region on the internal circuit side. Vias 60 are respectively formed on the p-type impurity region 18 formed on the n-type impurity region 13 facing the electrode 44 and the p-type impurity region 18 formed on the n-type impurity region 13 facing the electrode 47. Connected through.
In the example of FIGS. 3 and 4, the second layer wiring 24 is formed extending in the direction of the internal circuit, whereby the power supply pad of the reference potential Vss1 and the internal circuit are connected.
[0064]
In the region 18, the electrode 47 is connected to the third layer wiring 37 through the via 60 and further connected to the second layer wiring 27 through the via 60.
The second layer wiring 27 is a part of the upper layer region facing the two n-type impurity regions 13 and is formed adjacent to the above-described second layer wiring 24 in a region on the outer peripheral side of the semiconductor chip. Vias 60 are respectively formed in the n-type impurity region 17 formed on the n-type impurity region 13 facing the electrode 44 and the n-type impurity region 17 formed on the n-type impurity region 13 facing the electrode 47. Connected through.
In the example of FIGS. 3 and 4, the third layer wiring 37 is formed extending in the direction of the internal circuit, whereby the power supply pad of the power supply Vdd2 and the internal circuit are connected.
[0065]
According to the semiconductor device shown in FIGS. 3 and 4 described above, on the n-type impurity region 13 formed to face the electrode 44 in the region A16, the anode is connected to the electrode 44, and the cathode is connected to the electrode 46. A junction diode is formed. A pn junction diode having an anode connected to the electrode 46 and a cathode connected to the electrode 44 is formed on the n-type impurity region 13 formed facing the electrode 46 in the region A16. That is, parallel diodes connected in parallel in opposite directions are formed, thereby connecting the power supply pads of the reference potential Vss1 and the reference potential Vss2.
[0066]
A pn junction diode having an anode connected to the electrode 44 and a cathode connected to the electrode 47 is formed on the n-type impurity region 13 formed facing the electrode 44 in the region A18. A pn junction diode having an anode connected to the electrode 44 and a cathode connected to the electrode 47 is also formed on the n-type impurity region 13 formed facing the electrode 47 in the region A18. That is, parallel diodes connected in parallel in the same direction are formed, thereby connecting the power supply Vdd2 and the power supply pad of the reference potential Vss1.
[0067]
If the voltage of the noise component generated in the power supply Vdd1 system is smaller than the forward voltage of the diode, the diode has a high impedance with respect to the noise component, so that noise mixing from the power supply Vdd1 system to the power supply Vdd2 system is prevented. The
[0068]
When electrostatic discharge occurs to the power supply pad of the power supply Vdd2 system, the bidirectional parallel diode in the region A16 is turned on by the large voltage, and the reference potential Vss1 and the reference potential Vss2 are electrically connected. Thereby, since the electrostatic discharge protection circuit of both power supply systems is shared, the electrostatic withstand capability of the power supply Vdd2 system that is vulnerable to electrostatic discharge can be made comparable to that of the power supply Vdd1 system.
In addition, the forward parallel diode in the region A18 becomes conductive due to electrostatic discharge, and a part of the electrostatic discharge surge current flowing from the power supply pad of the power supply Vdd2 system also flows to the power supply Vdd1 system, thereby suppressing the voltage increase of the power supply Vdd2 system. can do.
[0069]
Further, as can be seen from comparison with the above-described conventional layout example, in the example of FIGS. 3 and 4, a diode for connecting the pads is provided on a semiconductor substrate facing an adjacent pad of a different power supply system. Since it is formed, there is no useless area where no circuit is formed between pads of different power supply systems, such as the area A7 and the area A8 in FIGS.
Therefore, according to the above-described layout example, it is possible to reduce a useless area where a circuit is not formed as compared with the conventional example, and it is possible to reduce the circuit area, improve the degree of integration, and increase the number of pins.
[0070]
  In addition, the above-mentioned with reference to FIGS.Reference form and number 1 Embodiment ofAre merely examples for explaining the present invention, and the present invention is not limited to these examples.
  For example, the electrostatic discharge protection circuit including the p-type MOS transistor Qp, the n-type MOS transistor Qn, and the resistor R in FIG. 1 is merely an example, and a semiconductor in which some or all of other various electrostatic discharge circuits face the pad. The present invention can also be realized by forming on a substrate.
[0071]
The number of wiring layers formed on the semiconductor substrate is arbitrary. Moreover, the shape of the wiring shown in FIGS. 1 to 4 is an example, and may be any shape. Selection of the wiring layer used for connection of each circuit is also arbitrary, and any wiring layer may be used.
[0072]
The conductivity type of the semiconductor substrate and the conductivity type of each impurity region are not limited to the examples shown in FIGS. 1 to 4 and can be arbitrarily set.
In the example of FIGS. 1 and 2, a MOS transistor is used as an example, but the type of the transistor is arbitrary, and for example, a bipolar transistor may be used. Similarly, the type of resistor is arbitrary, and the resistor may be formed using, for example, an impurity region.
[0073]
In the example of FIG. 4, a pn junction diode is formed as a diode connecting the pads, but the present invention can be implemented even if another diode is formed.
The number of diodes connected in parallel or in series is also arbitrary. For example, when the noise voltage is large, the number of diodes in series may be increased.
[0074]
3 and 4 show an example in which reference potentials of different power supply systems are connected by a bidirectional parallel diode, but different power supply potentials may be connected by a bidirectional parallel diode.
In the example of FIGS. 3 and 4, a diode that connects the reference potential Vss1 and the power supply Vdd2 is formed, but a diode that connects the power supply Vdd1 and the reference potential Vss2 may be formed. The direction of the diode can be set arbitrarily.
In the example of FIGS. 3 and 4, the bidirectional parallel diode and the forward parallel diode are formed together, but only one of them may be formed.
[0075]
【The invention's effect】
According to the semiconductor device of the present invention, firstly, the circuit area can be reduced as compared with the prior art.
Second, it is possible to reduce a useless area where a circuit is not formed and improve the degree of circuit integration.
[Brief description of the drawings]
FIG. 1 of the present inventionReference form2 is a schematic diagram illustrating an example of a circuit configuration and a layout of a semiconductor device according to FIG.
2 is a cross-sectional view of the semiconductor device shown in FIG.
FIG. 3 of the present inventionFirst embodimentIt is a schematic diagram showing an example of the layout of the semiconductor device according to the.
4 is a cross-sectional view of the semiconductor device shown in FIG. 3;
FIG. 5 is a schematic block diagram showing an example of a conventional semiconductor device provided with an electrostatic discharge protection circuit.
6 is a diagram showing an example of a conventional layout of the semiconductor device shown in FIG. 5;
7 is a cross-sectional view of the semiconductor device shown in FIG. 6;
FIG. 8 is a diagram illustrating an example of a layout near a pad in a conventional semiconductor device having two power supply systems.
9 is a cross-sectional view of the semiconductor device shown in FIG.
[Explanation of symbols]
  DESCRIPTION OF SYMBOLS 1 ... Pad, 2 ... Internal circuit, Qn ... P-type MOS transistor, Qp ... P-type MOS transistor, 11 ... Semiconductor substrate, 12, 18 ... P-type impurity region, 13, 17 ... N-type impurity region, 14 ... N-type Or p-type impurity region, 15 ... polycrystalline silicon film, 16 ... gate electrode, 21 to 27 ... second layer wiring, 31 to 37 ... third layer wiring, 41 to 47 ... fourth layer wiring, 50 ... interlayer insulation Membrane, 60 ... beer.

Claims (3)

A first pad for drawing out the first power supply line or a reference potential line corresponding to the first power supply line to the outside of the device;
A second pad for drawing out the second power supply line or a reference potential line corresponding to the second power supply line to the outside of the device;
At least a part is formed on the semiconductor substrate immediately below the first pad or the second pad , and has at least one diode connected between the first pad and the second pad. Semiconductor device. The diode is a parallel diode in which a plurality of diodes are connected in parallel in opposite directions,
A parallel diode for connecting the said first pad connected to the first power supply line and a said second pad connected to the second power supply line,
At least one of a parallel diode that connects the first pad connected to the reference potential line corresponding to the first power supply line and the second pad connected to the reference potential line corresponding to the second power supply line Meanwhile semiconductor device according to claim 1 which is a. The diode is
A diode connected with the first pad connected to the first power supply line, and a the said second pad connected to a reference potential line corresponding to the second power supply line,
And said first pad connected to a reference potential line corresponding to the first power supply line, to claim 1, wherein at least either one of a diode for connecting the second pad connected to the second power supply line The semiconductor device described.

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