JP2007305822A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a shortage of a connection pad for a power supply to a core region, to eliminate a necessity for decreasing a cell width of an IO cell, and to be able to apply an identical connection method to the all connection pads. <P>SOLUTION: A line of connection pads 41a to 41c and a line of connection pads 42a to 42d are arranged on IO cells 31a to 31g in an IO region 30 in a shifted manner, connection pads 43a to 43d are arranged on a core power wiring 21 among a side of a core region 20, and three connection pads per two IO cells are arranged with the relation between the respective pad pitch P of the connection pads 41a to 41c, 42a to 42d, 43a to 43d; the cell pitch S in the IO cells defined as P=2S; and the pad pitch of all connection pads 41a to 41c, 42a to 42d, 43a to 43d defined as P/3 (=2S/3). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit in which the arrangement of connection pads for performing wire bonding or the like is improved.

  In recent years, the number of circuit elements that can be mounted on a semiconductor integrated circuit has been greatly increased due to miniaturization of processes, and accordingly, for example, in ASIC (LSI for special applications), the number of pins is increasing. As a result, many connection pads are required to perform wire bonding, etc., but the pad pitch is limited due to restrictions of the wire bonding apparatus in package mounting, etc. A technique of dividing into a plurality of columns is widely used.

  FIG. 6 is a diagram showing a schematic plan view of a conventional semiconductor integrated circuit (LSI chip) 10. Reference numeral 20 denotes a core region, in which a main circuit is configured, and a core power supply wiring 21 and a core ground wiring 22 are arranged in a mesh shape. Reference numeral 30 denotes an IO region, in which a plurality of IO cells 31 are arranged, and connection pads 40 corresponding to the respective IO cells 31 are arranged. The connection pad 40 is connected to, for example, an input buffer, an output buffer, or an input / output buffer in the IO cell 31 via a wiring 51 (see FIG. 7), and is used as an input pad, an output pad, or an input / output pad, respectively. Is done. The connection pad 40 is also connected to an IO region high potential power supply wiring or ground power supply wiring (not shown) provided in the IO region 30, and the IO region 30 high potential voltage (VDDO) or low potential voltage (GNDO). Also used to supply. A part of the IO cell 31 is used to supply a high potential voltage (VDD) to the core power wiring 21 in the core region 20 and a low potential voltage (GND) to the core ground wiring 22. Used as the core grounding cell 33. In this case, the connection pads 40 arranged corresponding to the core power supply cell 32 and the core grounding cell 33 are used to supply VDD and GND, respectively. Reference numeral 34 denotes a core power supply wiring on the core power supply cell 32, and reference numeral 35 denotes a core ground wiring on the core grounding cell 33.

  FIG. 7 is an enlarged view of a portion X in FIG. In FIG. 7, the connection pads 40 are arranged in two rows in a staggered manner, so that the pad pitch P of the connection pads 40 in each row is maintained at twice the cell pitch S (= 2S), while the connection pads in the upper and lower rows are connected. Is reduced to the cell pitch S (= P / 2) to increase the pad density (see, for example, Patent Document 1). 52 is a wiring and 61 is a via.

  By the way, in order to further expand the method of arranging the connection pads as described above in two rows and realize a multi-pin configuration, the connection pads are arranged without changing the pad pitch P of the connection pads in each row. Can be increased to three or more rows. In FIG. 8 in which the arrangement of the connection pads 40 is increased to four rows, the pad pitch P of the connection pads 40 in each row is four times the cell pitch S (= 4S), and the total pad pitch of the four rows of connection pads 40 is the cell pitch S. (= P / 4).

  On the other hand, Non-Patent Document 1 proposes a method for reducing the chip area by arranging connection pads on the IO region 30. FIG. 9 shows an example in which this method is applied to the portion shown in FIG. In the example of FIG. 7, the connection pads 40 corresponding to the respective IO cells 31 are arranged in two rows outside the plurality of IO cells 31. On the other hand, in FIG. 9, the chip area necessary for arranging the IO region 30 is reduced by arranging the connection pads 40 on the respective IO cells 31.

By the way, in order to increase the density of the external electrode terminals while reducing the fine pitch of the external electrode terminals, a second external electrode terminal is disposed on the periphery of the semiconductor integrated circuit, and the external electrode terminals are relatively disposed on the semiconductor integrated circuit. It has been proposed to arrange a first external electrode terminal having a large size, a stud pad electrode in the former, and a solder bump electrode in the latter (see Patent Document 2). According to this, the voltage drop can be reduced by using the first external electrode terminal having a large size for the power source.
Japanese Patent Laid-Open No. 11-087399 JP 2002-270643 A Ohba Hisayoshi, “FUJITSU.55”, 3, p. 210-214, (May 2004)

  However, although the method shown in FIG. 8 can double the pad density as compared with FIGS. 7 and 9, the pad pitch P in each row in FIG. 8 is equal to the pad pitch in each row in FIGS. If it is the same as the pitch P, the cell width of the IO cell 31 is reduced to half the cell width of the IO cell 31 of FIGS. 7 and 9 by reducing the pad pitch of the entire pad. Further, since the adjacent boundary region 36 is required between the IO cells 31, the effective cell width of the IO cell 31 in FIG. 8 is further reduced. For this reason, layout arrangement of IO circuits, ESD protection elements, and the like required for the IO cells 31 becomes difficult.

  In recent years, it has become common to separate the power supply between the IO region 30 and the core region 20, and a large number of connection pads are required to supply independent power to the core region 20. For this reason, the connection pads for supplying power to the core region 20 may be insufficient if only the connection pads corresponding to the IO cells 31 are provided.

  Furthermore, in the technique shown in Patent Document 2, the types of connection pads are different between the first external electrode terminal and the second external electrode terminal, and different connection methods must be applied for external connection. There is a risk of increasing the assembly cost.

  An object of the present invention is to prevent a shortage of connection pads for supplying power to the core region, eliminate the need to reduce the cell width of the IO cells, and further allow the same connection method to be applied to all connection pads. It is to provide an integrated circuit.

In order to achieve the above object, according to the first aspect of the present invention, there is provided a core region in which a plurality of circuit elements are arranged, and a plurality of IO cells arranged along one side of the core region outside the core region. And an IO region in which a first connection pad corresponding to each of the plurality of IO cells is disposed, and a plurality of second connections are provided in the core region along the one side of the core region. A pad is arranged, and the same external connection means is connected to the first and second connection pads.
According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the external connection means is a bonding wire.
According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, the plurality of IO cells are arranged at a first pitch along the one side of the core region, and the plurality of second cells are arranged. The connection pads are arranged at a pitch that is a positive integer multiple of the first pitch along the one side of the core region.
According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to any one of the first to third aspects, the first and second connection pads are external dimensions in a direction along the one side of the core region. Are the same.
A fifth aspect of the present invention is the semiconductor integrated circuit according to any one of the first to fourth aspects, wherein the core region is disposed along the one side of the core region. And at least a part of the plurality of second connection pads is used to supply a power supply voltage to the power supply wiring.
According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the fifth aspect, the power wiring includes a high potential power wiring and a low potential power wiring, and at least a part of the plurality of second connection pads includes: It includes a first group of connection pads arranged along the high potential power supply wiring and a second group of connection pads arranged along the low potential power supply wiring.

  According to the present invention, the second connection pads arranged in the core region are mainly used for power supply to the core region, so that a shortage of pads occurs for power supply to the core region. Can be prevented. In addition, since connection pads can be arranged in the IO region as in the conventional case, it is not necessary to reduce the cell width of the IO region. Since the same external connection means is connected to the first connection pad and the second connection pad, the cost can be reduced. In particular, the cost can be reduced by connecting with bonding wires as described in claim 2. Further, as described in claim 3, by arranging the second connection pads to be a positive integer multiple of the arrangement pitch of the IO cells, the connection to both the first and second connection pads can be facilitated. Become. Further, as in the invention described in claim 4, by making the outer dimensions of the connection pads in the direction along one side of the core region the same, the arrangement density of the second connection pads can be increased.

[First embodiment]
FIG. 1 is an explanatory diagram of a part of an IO region and a part of a core region of the semiconductor integrated circuit according to the first embodiment of the present invention. Lower row connection pads 41a-41c are arranged on IO cells 31b, 31d, 31f, middle row connection pads 42a-42d are arranged on IO cells 31a, 31c, 31e, 31g, and upper row connection pads 43a-43c. 43 d is arranged on the core power supply wiring 21 (or the core ground wiring 22) in the core region 20. Each IO cell 31 lays out elements constituting an IO circuit such as an input / output buffer, ESD protection elements, etc., and wirings interconnecting these elements in advance in a region indicated by a square in FIG. It is a thing. In designing a semiconductor integrated circuit, a necessary number of IO cells 31 prepared in advance are arranged at a constant pitch along one side or a plurality of sides of the core region 20 and correspond to each IO cell 31. First connection pads (connection pads 41a to 41c and 42a to 42d) are arranged to form the IO region 30 (see FIG. 6).

  Each of the connection pads 41 a to 41 c and 42 a to 42 d is arranged on the corresponding IO cell 31. That is, each connection pad is disposed so that at least a part thereof is located above the element (arranged in the region indicated by the square) constituting the corresponding IO cell 31.

  The core power supply wiring 21 is a high potential power supply wiring that supplies a high potential voltage (VDD) to a plurality of circuit elements arranged in the core region 20, and the core ground wiring 22 is a plurality of circuits arranged in the core region 20. A low-potential power supply wiring for supplying a low-potential voltage (GND) to the element. The core power supply wiring 21 (or the core ground wiring 22) is arranged in the core region 20 along one side of the core region 20 (see FIG. 6). In the example illustrated in FIG. 1, a plurality of second connection pads (connection pads 43 a to 43 d) are arranged on the core power supply wiring 21 (or the core ground wiring 22). That is, the connection pads 43a to 43d are positioned along the core power supply wiring 21 (or the core ground wiring 22) and so that at least a part thereof is located above the core power supply wiring 21 (or the core ground wiring 22). Has been placed.

  Connection pads 41a-41c and 42a-42d arranged on IO cells 31a-31g are mainly connected to input buffers, output buffers, or input / output buffers in corresponding IO cells 31a-31g, respectively. Used as an output pad or input / output pad. The connection pads 41a to 41c and 42a to 42d are also connected to an IO region high potential power supply wiring or ground power supply wiring (not shown) provided in the IO region 30, and a high potential voltage (VDDO) for the IO region 30 or It is also used to supply a low potential voltage (GNDO). For connection between these connection pads and IO cells and power supply wiring, wiring, vias 61 and the like are used.

  The connection pads 43a to 43d arranged on the core power supply wiring 21 (or the core ground wiring 22) are mainly used for supplying power to the core region. Specifically, for example, the core region is connected to the core power supply wiring 21 (or the core ground wiring 22) via vias (not shown) provided directly below or adjacent to these connection pads 43a to 43d. 20 is used to supply a high potential voltage VDD (or low potential voltage GND) to a plurality of circuit elements arranged at 20. Alternatively, it is connected to a core ground wiring 22 (or core power wiring 21) (not shown) arranged adjacent to the core power wiring 21 (or core ground wiring 22) via vias and wirings and arranged in the core region 20. It is used for supplying a low potential voltage GND (or high potential voltage VDD) to a plurality of circuit elements.

  In this embodiment, the pad pitch P of the connection pads 41a to 41c, 42a to 42d, 43a to 43d in each column is twice (= 2S) the cell pitch S of the IO cells 31a to 31g. Further, the pad pitch of the entire connection pads arranged in these three rows is P / 3, and is therefore 2/3 times the cell pitch S (= 2S / 3). That is, the structure is such that three connection pads can be arranged per two IO cells. As a result, the number of connection pads is substantially 1.5 times that of the conventional staggered two-row pad arrangement (one connection pad per IO cell) described with reference to FIGS. It becomes possible. Further, the cell width of the IO cell can be doubled as compared with the 4-row pad arrangement described in FIG. That is, the cell width can be made the same as in the case of the pad arrangement described with reference to FIGS.

  FIG. 2 shows a state in which the connection pads 41a to 41c, 42a to 42d, and 43a to 43d are wire-bonded with wires 70. The first connection pads 41a to 41c and 42a to 42d arranged in two rows are arranged with the arrangement pitch S of the IO cells 31a to 31g in a direction along one side of the core region 20 (lateral direction in FIG. 1). Are arranged at a pitch of a positive integer multiple of (2 in the example of FIG. 1). The connection pads 43a to 43d arranged on the core power supply wiring 21 (or the core ground wiring 22) can be arranged regardless of the arrangement of the IO cells 31a to 31g. However, practically, the connection positions of the connection pads 43a to 43d in the direction along one side of the core region 20 (the horizontal direction in FIG. 1) are the same as the connection positions of the connection pads 41a to 41c and 42a to 42d. It is preferable to maintain a certain simple relationship with respect to. This facilitates the setting of the bonding position when wire bonding is performed using an automatic bonding apparatus, and can prevent the occurrence of bonding failure. Specifically, for example, the connection pads 43a to 43d also have a positive integer multiple (double in the example of FIG. 1) of the arrangement pitch S of the IO cells 31a to 31g in the direction along one side of the core region 20. Is preferably arranged. In particular, when the arrangement pitch of the first connection pads 41a to 41c and 42a to 42d in the direction along one side of the core region 20 is a positive integer multiple of the arrangement pitch S of the IO cells 31a to 31g, the connection pads It is preferable to set the arrangement pitch of 43a to 43d to a positive integer multiple (approximately 1 in the example of FIG. 1) of the arrangement pitch of these connection pads 41a to 41c and 42a to 42d. Further, by arranging the first connection pads 41a to 41c, 42a to 42d and the second connection pads 43a to 43d in a staggered manner, bonding can be further facilitated.

  As described above, the second connection pads 43a to 43d arranged on the core power supply wiring 21 (or the core ground wiring 22) have a larger pitch than the first connection pads 41a to 41c and 42a to 42d. It is also possible to arrange with. In this case, the dimensions of the second connection pads 43a to 43d in the direction along the one side of the core region 20 (lateral direction in FIG. 1) are the same as the dimensions of the first connection pads 41a to 41c and 42a to 42d. It is also possible to make it larger than However, in order to increase the pad arrangement density by making the arrangement pitch of the second connection pads 43a to 43d the same as the arrangement pitch of the first connection pads 41a to 41c or 42a to 42d, the second connection pads 43a to 43d are used. The dimension in the direction along one side of the core region 20 of 43d is also preferably the same or substantially the same as the dimension in the same direction of the first connection pads 41a to 41c and 42a to 42d.

  Note that by connecting bonding wires as external connection means for these connection pads 41a to 41c, 42a to 42d, and 43a to 43d, mounting at a particularly low cost becomes possible. However, the external connection means used in the semiconductor integrated circuit of the present invention is not limited to bonding wires. For example, it is possible to connect gold bumps. Alternatively, it is possible to connect the solder bumps via the rearrangement wiring. In any case, it is possible to reduce the mounting cost by connecting the same external connection means to the first connection pads 41a to 41c and 42a to 42d and the second connection pads 43a to 43d. It is.

[Second embodiment]
FIG. 3 is an explanatory diagram of a part of the IO region and a part of the core region of the semiconductor integrated circuit according to the second embodiment of the present invention. In this embodiment, in the same three-row pad arrangement as in the first embodiment, the connection structures of the connection pads 41a to 41c and 42a to 42d to the IO cells 31a to 31g are the same as those in the first embodiment. The position is slightly off. Thus, the center line of the IO cell 31 and the center line of the connection pad do not necessarily overlap, and the arrangement of the connection pad and the arrangement of the IO cell 31 in the pad row are the same as the connection pad and the IO cell. It is possible to set an arbitrary position as long as connection is possible.

  In both the first and second embodiments, the first connection pads (connection pads 41 a to 41 c and 42 a to 42 d) are arranged on the corresponding IO cells 31. As a result, it is possible to reduce the chip area required for arranging the IO cells and the first connection pads. However, in the semiconductor integrated circuit of the present invention, it is not essential to arrange the connection pads on the corresponding IO cells in this way. When there is a margin in the chip area, for example, as shown in FIG. 7, it is possible to dispose the first connection pads further outside the region where the IO cells are disposed. Further, the second connection pads (connection pads 43a to 43d) are not necessarily arranged on the core power supply wiring 21 (or the core ground wiring 22). However, even if not arranged on the core power supply wiring 21 (or the core ground wiring 22), it is connected to the corresponding core power supply wiring 21 (or the core ground wiring 22) with a short wiring to obtain a high power supply capability. It is preferable to arrange them along the core power supply wiring 21 (or the core ground wiring 22).

[Third embodiment]
FIG. 4 is an explanatory diagram of a part of the IO region and a part of the core region of the semiconductor integrated circuit according to the third embodiment of the present invention, and shows an example in which connection pads are arranged in four rows. Connection pads 41a-41d are arranged on IO cells 31c, 31f, 31i, 31l, connection pads 42a-42e are arranged on IO cells 31a, 31d, 31g, 31j, 31m, and connection pads 43a-43e are IO cells. The connection pads 44a to 44e are arranged on the core power supply wiring 21 (or the core ground wiring 22) in the core region 20 and arranged on 31b, 31e, 31h, 31k, 31n. The pad pitch P of the connection pads 41a to 41d, 42a to 42e, 43a to 43e, and 44a to 44e in each column is three times (= 3S) the cell pitch S of the IO cells 31a to 31n. Further, the pad pitch of the entire connection pads arranged in four rows is P / 4, and therefore, 3/4 times the cell pitch S (= 3S / 4). As a result, four connection pads can be arranged for three IO cells 31.

[Fourth embodiment]
FIG. 5 is an explanatory diagram of a part of the IO region and a part of the core region of the semiconductor integrated circuit according to the fourth embodiment of the present invention. FIG. 5 shows that one of the four rows of connection pads is arranged on the core power supply wiring 21 in the core region 20, and another row is arranged on the core ground wiring 22 in the core region 20. This is an example in the case where these two columns are arranged on the IO cell 31. The connection pads 43 a to 43 d arranged on the core power supply wiring 21 are mainly used for supplying the high potential voltage VDD to a plurality of circuit elements arranged in the core region 20. The connection pads 44 a to 44 d arranged on the core ground wiring 22 are mainly used for supplying the low potential voltage GND to a plurality of circuit elements arranged in the core region 20. The pad pitch P of the connection pads 41a to 41c, 42a to 42d, 43a to 43d, and 44a to 44d in each column is twice the cell pitch S of the IO cells 31a to 31g (= 2S). In addition, the pad pitch of the entire connection pads arranged in four rows is P / 4, and thus is 1/2 times the cell pitch S (= S / 2). As a result, four connection pads can be arranged for every two IO cells 31.

  In this example, the second connection pads are divided into a first group of connection pads 43a to 43d and a second group of connection pads 44a to 44d, and each is arranged so as to form one row. Thus, while maintaining the pad pitch of the connection pads in each column the same as in the first embodiment shown in FIG. 1 (twice the IO cell arrangement pitch S), the number of second connection pads is The number can be doubled in the case of the first embodiment. For this reason, the probability that the pad shortage occurs due to the power supply to the core region can be further reduced as compared with the case of the first embodiment.

It is explanatory drawing of a part of IO area | region and a part of core area | region of the semiconductor integrated circuit of 1st Example of this invention. It is explanatory drawing which performed the wire bonding to the connection pad in the 1st Example. It is explanatory drawing of a part of IO area | region and a part of core area | region of the semiconductor integrated circuit of 2nd Example of this invention. It is explanatory drawing of a part of IO area | region and a part of core area | region of the semiconductor integrated circuit of the 3rd Example of this invention. It is explanatory drawing of a part of IO area | region and a part of core area | region of the semiconductor integrated circuit of the 4th Example of this invention. It is a top view which shows schematic structure of the conventional semiconductor integrated circuit. FIG. 7 is an explanatory diagram of a part of an IO region and a part of a core region of the conventional semiconductor integrated circuit of FIG. 6. It is explanatory drawing of a part of IO area | region of the conventional semiconductor integrated circuit which has arrange | positioned the connection pad in 4 rows. It is explanatory drawing of a part of IO area | region of the conventional semiconductor integrated circuit which has arrange | positioned the connection pad in 2 rows on IO area | region.

Explanation of symbols

10: Semiconductor device 20: Core region, 21: Core power supply wiring, 22: Core ground wiring, 30: IO region, 31, 31a to 31n: IO cell, 32: Core power supply cell, 33: Core grounding cell, 34: Core power wiring, 35: Core ground wiring, 36: Adjacent boundary regions 40, 41a to 41d, 42a to 42e, 43a to 43e, 44a to 44e: Connection pads 51, 52: Wiring 61: Via 70: Bonding wire

Claims (6)

A plurality of IO cells are arranged along one side of the core region, and a first region corresponding to each of the plurality of IO cells is disposed outside the core region in which the plurality of circuit elements are disposed. An IO region in which connection pads are arranged;
A plurality of second connection pads are arranged in the core region along the one side of the core region, and the same external connection means is connected to the first and second connection pads. A semiconductor integrated circuit.   2. The semiconductor integrated circuit according to claim 1, wherein the external connection means is a bonding wire.   The plurality of IO cells are arranged at a first pitch along the one side of the core region, and the plurality of second connection pads are a positive integer of the first pitch along the one side of the core region. 3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is arranged at a double pitch.   4. The semiconductor integrated circuit according to claim 1, wherein the first and second connection pads have the same outer dimensions in a direction along the one side of the core region. 5.   The core region includes a power supply wiring arranged along the one side of the core region for supplying power to the plurality of circuit elements, and at least a part of the plurality of second connection pads is the power supply wiring. 5. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is used to supply a power supply voltage.   The power supply wiring includes a high potential power supply wiring and a low potential power supply wiring, and at least a part of the plurality of second connection pads is arranged along the high potential power supply wiring, 6. The semiconductor integrated circuit according to claim 5, further comprising a second group of connection pads arranged along the low potential power wiring.

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