CN113745212A - Integrated circuit and method for laying out integrated circuit - Google Patents
Integrated circuit and method for laying out integrated circuit Download PDFInfo
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Abstract
本申请实施例提供一种集成电路及其布局方法，该方法包括：从第一标准胞元件库和第二标准胞元件库中分别获取第一标准胞元和第二标准胞元，其中，第一标准胞元和第二标准胞元中的一者具有第一高度、另一者具有不等于第一高度的第二高度；布置第一标准胞元和第二标准胞元以使其在行的方向上彼此邻接或者邻近；从补充胞元件库中获取补充胞元；使补充胞元的横向边界和上述一者的横向边界重叠而形成重叠边界并且补充胞元和上述一者分别位于重叠边界的两侧，从而形成具有第三高度的组合胞元，其中，第二高度相比于第三高度具有倍率关系。本申请实施例的技术方案可以提高电路布局面积的使用率，缩小芯片的面积。
An embodiment of the present application provides an integrated circuit and a layout method thereof, the method includes: obtaining a first standard cell and a second standard cell from a first standard cell element library and a second standard cell element library, respectively, wherein the first standard cell element and the second standard cell element library are obtained. One of a standard cell and a second standard cell has a first height and the other has a second height not equal to the first height; the first standard cell and the second standard cell are arranged so that they are in the row are adjacent to or adjacent to each other in the direction of the complementary cell element; the complementary cell is obtained from the complementary cell element library; the lateral boundary of the complementary cell and the lateral boundary of one of the above are overlapped to form an overlapping boundary, and the complementary cell and one of the above are located at the overlapping boundary, respectively , thereby forming a combined cell with a third height, wherein the second height has a magnification relationship with respect to the third height. The technical solutions of the embodiments of the present application can improve the utilization rate of the circuit layout area and reduce the area of the chip.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to a method of laying out an integrated circuit and a laid out integrated circuit.
Background
One of the trends in integrated circuits is miniaturization, which means that a Standard cell library (also referred to as a Standard cell library or a Standard cell library) with smaller area and less power consumption, but capable of providing more functions at higher speed is expected to be developed to meet the product design requirements.
The standard cell device libraries have different heights, and the combination of the standard cell device libraries with different heights has the problems of low utilization rate of circuit layout area, overlarge chip area and the like.
Disclosure of Invention
The invention solves the technical problems of low utilization rate of circuit layout area, overlarge chip area and the like.
To solve the above technical problem, an embodiment of the present invention provides a method for laying out an integrated circuit, including: a, acquiring a first standard cell and a second standard cell from a first standard cell device library and a second standard cell device library respectively, wherein one of the first standard cell and the second standard cell has a first height, and the other one has a second height which is not equal to the first height; b arranging the first and second standard cells to be adjacent or neighboring to each other in a row direction; c, acquiring supplementary cells from a supplementary cell device library; and d, overlapping the transverse boundary of the supplementary cell and the transverse boundary of the one to form an overlapping boundary, wherein the supplementary cell and the one are respectively positioned at two sides of the overlapping boundary, so as to form a combined cell with a third height, and the second height has a multiplying power relation with the third height.
Optionally, the magnification relationship is a magnification relationship of 1, 1/2, 2/3, 3/4, 3/5, 4/5, or 5/6.
Optionally, step d comprises: net information associated with the power line in the first standard cell, the second standard cell, and/or the supplemental cell is determined, and a power port thereof is coupled to the VDD power rail and a ground port thereof is coupled to the VSS power rail based on the net information.
Optionally, step c includes obtaining N supplementary cells from a supplementary cell device library, where N is a positive integer; and d, sequentially overlapping the N supplementary cells by transverse boundaries to form a first combination, wherein the height of the first combination is the sum of the heights of the N supplementary cells, overlapping the lower boundary of the first combination with the upper boundary of the first combination or overlapping the upper boundary of the first combination with the lower boundary of the first combination to form a first type of overlapping boundary, and the first combination are respectively positioned at two sides of the first type of overlapping boundary, so that a combined cell with a third height is formed.
Optionally, step c includes acquiring a supplementary cell from the supplementary cell device library; step d includes overlapping the lower boundary of one of the supplementary cells with the upper boundary of the one of the supplementary cells or overlapping the upper boundary of one of the supplementary cells with the lower boundary of the one of the supplementary cells to form a first overlapping boundary and one of the supplementary cells and the one of the supplementary cells are respectively located on both sides of the first overlapping boundary to form a combined cell having a third height.
Alternatively, the first height is 9T, the second height is 6T, the height of a complementary cell is 3T, and the multiplying power relationship is 1/2.
Optionally, the first height is 10.5T, the second height is 6T, the height of each complementary cell is 1.5T, and the multiplying power relationship is 1/2.
Optionally, the first height is 7.5T, the second height is 6T, the height of each complementary cell is 1.5T, and the multiplying power relationship is 2/3.
Optionally, step c includes obtaining N supplementary cells from a supplementary cell device library, where N is a positive integer; step d comprises dividing the N supplementary cells into two groups, each group comprising M supplementary cells and N-M supplementary cells, respectively, such that the M supplementary cells sequentially overlap by lateral boundaries to form a second combination, the height of the second combination being the sum of the heights of the M supplementary cells, and the N-M supplementary cells sequentially overlap by lateral boundaries to form a third combination, the height of the third combination being the sum of the heights of the N-M supplementary cells; the second combination and the first combination are respectively positioned at two sides of the second type overlapping boundary or the fourth type overlapping boundary, and the third combination and the first combination are respectively positioned at two sides of the third type overlapping boundary or the fifth type overlapping boundary, so that a combination cell with a third height is formed.
Optionally, step c includes acquiring the first supplementary cell and the second supplementary cell from a supplementary cell device library; the step d includes forming a second overlapping boundary by overlapping the lower boundary of the first supplementary cell and the upper boundary of the one and forming a third overlapping boundary by overlapping the upper boundary of the second supplementary cell and the lower boundary of the one, or forming a fifth overlapping boundary by overlapping the upper boundary of the first supplementary cell and the lower boundary of the one and forming a fourth overlapping boundary by overlapping the upper boundary of the second supplementary cell and the upper boundary of the one, the first supplementary cell and the one being respectively located on both sides of the second overlapping boundary or the fourth overlapping boundary, and the second supplementary cell and the one being respectively located on both sides of the third overlapping boundary or the fifth overlapping boundary, thereby forming a combined cell having a third height.
Optionally, the first supplementary cell and the second supplementary cell have the same or different heights.
Optionally, the first height is 9T, the second height is 6T, the heights of the first supplementary cell and the second supplementary cell are both 1.5T, and the multiplying power relationship is 1/2.
Optionally, the first height is 10.5T, the second height is 6T, the heights of the first supplementary cell and the second supplementary cell are both 0.75T, and the magnification relationship is 1/2.
Optionally, the first height is 7.5T, the second height is 6T, the heights of the first supplementary cell and the second supplementary cell are both 0.75T, and the magnification relationship is 2/3.
An embodiment of the present invention further provides an integrated circuit, including: first and second standard cells adjacent or neighboring each other in a column direction, one of the first and second standard cells having a first height and the other having a second height unequal to the first height; and the supplementary cell, the transverse boundary of the supplementary cell and the transverse boundary of the one are overlapped to form an overlapping boundary, and the supplementary cell and the one are respectively positioned at two sides of the overlapping boundary, so that a combined cell with a third height is formed, wherein the second height has a multiplying power relation with the third height.
Optionally, the magnification relationship is a magnification relationship of 1, 1/2, 2/3, 3/4, 3/5, 4/5, or 5/6.
Optionally, the integrated circuit includes a VDD power rail and a VSS power rail, wherein a power port of the first standard cell, the second standard cell, and/or the supplemental cell is coupled to the VDD power rail and a ground port is coupled to the VSS power rail.
Optionally, the supplementary cell includes N supplementary cells, where N is a positive integer, the N supplementary cells are sequentially overlapped by a lateral boundary to form a first combination, a height of the first combination is a sum of heights of the N supplementary cells, a lower boundary of the first combination overlaps an upper boundary of the one or an upper boundary of the first combination overlaps a lower boundary of the one to form a first type of overlapping boundary, and the first combination and the one are respectively located at two sides of the first type of overlapping boundary, thereby forming a combined cell having a third height.
Optionally, the supplementary cells include a supplementary cell, a lower boundary of the supplementary cell overlaps an upper boundary of the one or an upper boundary of the supplementary cell overlaps a lower boundary of the one to form a first overlapping boundary, and the supplementary cell and the one are respectively located on both sides of the first overlapping boundary, thereby forming a combined cell having a third height.
Alternatively, the first height is 9T, the second height is 6T, the height of a complementary cell is 3T, and the multiplying power relationship is 1/2.
Optionally, the first height is 10.5T, the second height is 6T, the height of each complementary cell is 1.5T, and the multiplying power relationship is 1/2.
Optionally, the first height is 7.5T, the second height is 6T, the height of each complementary cell is 1.5T, and the multiplying power relationship is 2/3.
Optionally, the supplementary cells include N supplementary cells, where N is a positive integer, the N supplementary cells are divided into two groups, each group includes M supplementary cells and N-M supplementary cells, the M supplementary cells sequentially overlap by lateral boundary to form a second combination, the height of the second combination is the sum of the heights of the M supplementary cells, the N-M supplementary cells sequentially overlap by lateral boundary to form a third combination, and the height of the third combination is the sum of the heights of the N-M supplementary cells; the lower boundary of the second combination and the upper boundary of the one overlap to form a second-type overlap boundary, the upper boundary of the third combination and the lower boundary of the one overlap to form a third-type overlap boundary, or the upper boundary of the second combination and the lower boundary of the one overlap to form a fourth-type overlap boundary, the lower boundary of the third combination and the upper boundary of the one overlap to form a fifth-type overlap boundary, the second combination and the one are respectively located on both sides of the second-type overlap boundary or the fourth-type overlap boundary, and the third combination and the one are respectively located on both sides of the third-type overlap boundary or the fifth-type overlap boundary, thereby forming a combination cell having a third height.
Alternatively, the supplementary cells include a first supplementary cell and a second supplementary cell, a lower boundary of the first supplementary cell and an upper boundary of the one overlap to form a second overlapping boundary and an upper boundary of the second supplementary cell and a lower boundary of the one overlap to form a third overlapping boundary, or an upper boundary of the first supplementary cell and a lower boundary of the one overlap to form a fourth overlapping boundary and a lower boundary of the second supplementary cell and an upper boundary of the one overlap to form a fifth overlapping boundary, the first supplementary cell and the one are respectively located at both sides of the second overlapping boundary or the fourth overlapping boundary, and the second supplementary cell and the one are respectively located at both sides of the third overlapping boundary or the fifth overlapping boundary, thereby forming a combined cell having a third height.
Optionally, the first supplementary cell and the second supplementary cell have the same or different heights.
Optionally, the first height is 9T, the second height is 6T, the heights of the first supplementary cell and the second supplementary cell are both 1.5T, and the multiplying power relationship is 1/2.
Optionally, the first height is 10.5T, the second height is 6T, the heights of the first supplementary cell and the second supplementary cell are both 0.75T, and the magnification relationship is 1/2.
Optionally, the first height is 7.5T, the second height is 6T, the heights of the first supplementary cell and the second supplementary cell are both 0.75T, and the magnification relationship is 2/3.
Compared with the prior art, the technical scheme of the embodiment of the invention has the beneficial effect. For example, the complementary cell is combined with one standard cell to form a combined cell, and the height of the other standard cell has a multiplying factor relationship with the height of the combined cell, so that the utilization rate of the circuit layout area is increased, and the area of a chip is reduced.
Drawings
FIG. 1 is a flow chart of a method of laying out an integrated circuit according to an embodiment of the invention;
FIG. 2 is a diagram illustrating a layout structure of an integrated circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a layout structure of another integrated circuit according to an embodiment of the present invention.
Detailed Description
The standard cell device library may be provided by a Foundry chip (Foundry). The standard cell component library comprises a plurality of standard cells, and the standard cells are pre-designed logic units and have universal regular structures and interface implementation; the standard cells are placed in the desired locations by Placement (Placement), and then the standard cells are connected to each other and to other circuits on the chip by Routing (Routing).
The standard cell has a certain height, which may be any integer or fractional multiple of a Track pitch (Track, abbreviated as T), such as 6T, 7T, 7.5T, 8T, 9T, 10T, 10.5T, 11T and 12T, where T represents the sum of the minimum line width of the metal lines and the minimum space width of the metal lines in the cell.
When the integrated circuit is designed, the heights of standard cells obtained from the same or different standard cell component libraries may not be the same, wherein the heights of at least two standard cells do not have a multiplying power relationship; in the embodiment of the present invention, the "magnification relationship" is expressed as a fractional relationship of "m/n", where m and n are both positive integers with the digit of one, and the magnification relationship includes 1, 1/2, 2/3, 3/4, 3/5, 4/5, and 5/6.
Standard cells with two heights that do not have a magnification relationship can be placed in columns. Taking the example of two adjacent rows, the standard cells with two heights not having a multiplying power relationship are placed in the two adjacent rows, for example, the two standard cells are placed in two rows respectively, or both standard cells are placed in two rows. When the standard cells are arranged along the row direction, adjacent standard cells can share a Power rail (Power rail) without a gap, wherein the Power rail includes a VDD Power rail (Power rail coupled to the operating voltage) and a VSS Power rail (Power rail coupled to the ground). However, since the two standard cells have no rate relationship, it is impossible to make two rows have equal height by repeating the placement a small number of times in a limited area of the chip, and thus there is a gap in one or two rows.
The gaps can be filled by Filler cells (Filler cells), and since the Filler cells are only used for verification (DRC) and the like satisfying Design rules and are not related to logic, the utilization rate of layout area in the integrated circuit is reduced and the area of the chip is increased due to the existence of the gaps.
For example, when designing the layout of an integrated circuit, involving a plurality of standard cells having different heights, one of the standard cells has a height of 6T, and the other standard cell has a height of 10.5T, when placing the standard cell having a height of 6T and the standard cell having a height of 10.5T to form two adjacent or adjacent rows, since 6T and 10.5T have no magnification relationship, it is impossible to make the two rows have equal heights by repeating the placement a small number of times, and thus there is a gap in one or both of the rows.
In view of the above technical problem, in the embodiment of the present invention, a supplementary cell device library is introduced, which comprises a plurality of supplementary cells, and the supplementary cells are related to logic, that is, have a circuit for realizing logic function, such as a gate circuit.
The height of the supplementary cell can be flexibly designed based on two standard cells of different heights, i.e. so that the supplementary cell is combined with one standard cell to form a combined cell, while the height of the other standard cell has a multiplying factor relationship with the height of the combined cell.
The Power rail is formed by introducing the supplementary cell and the Power line (Power line) bridging the two standard cells and/or the supplementary cell, so that the area utilization rate can be improved in a limited area of the chip, the arrangement of the Power line is more scientific and reasonable, the overall layout is simpler, and correspondingly, the energy consumption of the chip is lower.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
FIG. 1 is a flow chart of a method of laying out an integrated circuit according to an embodiment of the invention. The method 100 comprises the steps of:
step S110: obtaining a first standard cell and a second standard cell from a first standard cell device library and a second standard cell device library, respectively, wherein one of the first standard cell and the second standard cell has a first height and the other has a second height different from the first height;
step S120: arranging the first standard cell and the second standard cell to be adjacent or neighboring to each other in a row direction;
step S130: acquiring supplementary cells from a supplementary cell device library;
step S140: the lateral boundary of the supplementary cell and the lateral boundary of the one are overlapped to form an overlapping boundary, and the supplementary cell and the one are respectively positioned at both sides of the overlapping boundary, thereby forming a combined cell having a third height, wherein the second height has a multiplying power relationship with respect to the third height.
The integrated circuit of the method 100 may include at least two types of standard cells, such as a first standard cell and a second standard cell, a layout structure formed by repeated placement and routing of the at least two types of standard cells (and supplemental cells), and a chip fabricated by performing masking, tape-out, testing, and the like based on the layout structure.
In step S110, a first standard cell and a second standard cell are acquired from the first standard cell device library and the second standard cell device library, respectively.
The first standard cell device library and the second standard cell device library may be the same standard cell device library or different standard cell device libraries; the one of the first and second standard cells has a first height and the other has a second height different from the first height.
In the execution of step S120, the first standard cell and the second standard cell are arranged so as to be adjacent or neighboring to each other.
As shown in fig. 2 and 3, when the cells (e.g., standard cells, supplementary cells) are arranged on a row and column basis, they have lateral boundaries and longitudinal boundaries extending in the row and column directions, respectively, wherein the lateral boundaries include upper and lower boundaries, the longitudinal boundaries include left and right boundaries, and the upper, lower, left and right boundaries collectively define the area of the cells.
When the cells are placed in the row direction, the first and second standard cells may be adjacent to each other, i.e., the left boundary of the first standard cell may overlap the right boundary of the second standard cell and/or the right boundary of the first standard cell may overlap the left boundary of the second standard cell; the first standard cell and the second standard cell may be adjacent to each other at a certain interval.
In step S130, supplementary cells are obtained from a supplementary cell device library.
The supplemental cell device library is typically provided by foundation or intellectual property module vendor (IP vendor) to fulfill the customer customized requirements. Currently, complementary cell libraries are designed with logic functions based only on specific customization requirements.
N supplementary cells can be obtained from a supplementary cell library, N being a positive integer.
In one embodiment, N is equal to 1, i.e., 1 supplementary cell is acquired from the supplementary cell device library; in another embodiment, N equals 2, i.e., 2 supplemental cells are acquired from the supplemental cell device library.
In step S140, the lateral boundary of the supplementary cell and the lateral boundary of the one are overlapped to form an overlapping boundary, and the supplementary cell and the one are respectively located at both sides of the overlapping boundary, thereby forming a combined cell having a third height, and the second height has a magnification relationship with respect to the third height.
When the cells are placed in the row direction, the lateral boundaries of the supplemental cells and the lateral boundaries of the one may overlap, i.e., the upper boundaries of the supplemental cells overlap the lower boundaries of the one and/or the lower boundaries of the supplemental cells overlap the upper boundaries of the one.
In the embodiment of the present invention, it is considered that, on one hand, standard cells with different heights may have a gap and other problems when placed, and on the other hand, the supplementary cell device library has a geometrical dimension attribute, such as a height attribute, in addition to a logic function attribute; it is also considered that the association can be made in the above two aspects, that is, the height attribute of the supplementary cell is utilized to be combined with one standard cell to form a combined cell, wherein the height of the other standard cell has a multiplying factor relationship with the height of the combined cell, so that the utilization rate of the circuit layout area can be effectively increased, the area of the chip can be reduced, and the like.
Specifically, one of the first and second standard cells has a first height H1 and the other has a second height H2, wherein H1 is not equal to H2. N supplementary cells can be obtained from the supplementary cell device library, and the sum of the heights of the N supplementary cells is H3, where N is a positive integer.
N supplementary cells may be combined with one of the above to form a combined cell, the combined cell having a height H4, wherein H4 is equal to the sum of H1 and H3; and H2 has a magnification relationship R compared to H4 (as described above, R is represented as a fractional relationship of "m/n", m and n being positive integers with a digit of one). Can be expressed by the following formulas (1) and (2):
H4＝H1+H3 (1)
R＝H2/H4 (2)
r may be 1/1, where the sum of the height of one of the first and second standard cells and the height of the N supplemental cells is equal to the height of the other.
R may be 1/2, for example, the sum of the height of one of the first and second standard cells and the height of the N supplemental cells may be 7T and 5T, 7.5T and 4.5T, 8T and 4T, 9T and 3T, 10T and 2T, 10.5T and 1.5T, or 11T and 1T, respectively, with the height of the other being 6T.
R may be 2/3, for example, the sum of the height of one of the first and second standard cells and the height of the N supplemental cells may be 7T and 5T, 7.5T and 4.5T, 8T and 4T, 9T and 3T, 10T and 2T, 10.5T and 1.5T, or 11T and 1T, respectively, with the height of the other being 8T.
R may be 3/4, for example, the sum of the height of one of the first and second standard cells and the height of the N supplemental cells may be 7T and 5T, 7.5T and 4.5T, 8T and 4T, 9T and 3T, 10T and 2T, 10.5T and 1.5T, or 11T and 1T, respectively, with the height of the other being 9T.
R may be 3/5, for example, the sum of the height of one of the first and second standard cells and the height of the N supplemental cells may be 6T and 4T, 7T and 3T, 7.5T and 2.5T, 8T and 2T, or 9T and 1T, respectively, with the height of the other being 6T.
R may be 4/5, for example, the sum of the height of one of the first and second standard cells and the height of the N supplemental cells may be 6T and 4T, 7T and 3T, 7.5T and 2.5T, 8T and 2T, or 9T and 1T, respectively, with the height of the other being 8T.
R may be 5/6, for example, the sum of the height of one of the first and second standard cells and the height of the N supplemental cells may be 7T and 5T, 7.5T and 4.5T, 8T and 4T, 9T and 3T, 10T and 2T, 10.5T and 1.5T, or 11T and 1T, respectively, with the height of the other being 10T.
N supplemental cells may be sequentially overlapped by lateral boundaries to form a first combination having a height that is the sum of the heights of the N supplemental cells; the combination cell may be formed by overlapping the lower boundary of the first combination and the upper boundary of the one or overlapping the upper boundary of the first combination and the lower boundary of the one to form a first type of overlapping boundary, and the first combination and the one are respectively located on both sides of the first type of overlapping boundary.
In some embodiments, N is equal to 1, i.e., one supplemental cell is acquired from the supplemental cell device library; the lower boundary of one supplementary cell and the upper boundary of the one are overlapped or the upper boundary of one supplementary cell and the lower boundary of the one are overlapped to form a first overlapping boundary and one supplementary cell and the one are respectively positioned at both sides of the first overlapping boundary, thereby forming a combined cell.
In one embodiment, H1 is 9T, H2 is 6T, the height of a supplemental cell is 3T, and R is 1/2.
In another embodiment, H1 is 10.5T, H2 is 6T, the height of a supplemental cell is 1.5T, and R is 1/2.
In yet another embodiment, H1 is 7.5T, H2 is 6T, the height of one supplemental cell is 1.5T, and R is 2/3.
Fig. 2 illustrates a layout structure of an integrated circuit, which is formed of a plurality of standard cells a1, standard cells B1, and supplementary cells C1. For one of the standard cell a1, the standard cell B1, and the supplemental cell C1, the lower boundary of the supplemental cell C1 overlaps the upper boundary of the standard cell B1 to form an overlapping boundary, and the supplemental cell C1 and the standard cell B1 are respectively located on both sides of the overlapping boundary to form the combined cell 210 (hatched area in fig. 2). The standard cell a1 and the combinational cell 210 are adjacent to each other, with the supplementary cell D1 disposed therebetween.
The N supplemental cells may be divided into two groups, each group including M and N-M supplemental cells, the M supplemental cells of the first group being sequentially overlapped by a lateral boundary to form a second group having a height that is a sum of heights of the M supplemental cells, the N-M supplemental cells of the second group being sequentially overlapped by a lateral boundary to form a third group having a height that is a sum of heights of the N-M supplemental cells; the combination cell may be formed by overlapping the lower boundary of the second combination and the upper boundary of the one to form a second-type overlapping boundary and overlapping the upper boundary of the third combination and the lower boundary of the one to form a third-type overlapping boundary, or overlapping the upper boundary of the second combination and the lower boundary of the one to form a fourth-type overlapping boundary and overlapping the lower boundary of the third combination and the upper boundary of the one to form a fifth-type overlapping boundary, the second combination and the one being respectively located on both sides of the second-type overlapping boundary or the fourth-type overlapping boundary, and the third combination and the one being respectively located on both sides of the third-type overlapping boundary or the fifth-type overlapping boundary.
In some embodiments, N is equal to 2, i.e., two supplemental cells are acquired from the supplemental cell device library; the lower boundary of the first supplementary cell and the upper boundary of the first supplementary cell are overlapped to form a second overlapped boundary, and the upper boundary of the second supplementary cell and the lower boundary of the first supplementary cell are overlapped to form a third overlapped boundary, or the upper boundary of the first supplementary cell and the lower boundary of the first supplementary cell are overlapped to form a fourth overlapped boundary, and the lower boundary of the second supplementary cell and the upper boundary of the first supplementary cell are overlapped to form a fifth overlapped boundary, the first supplementary cell and the first supplementary cell are respectively positioned at two sides of the second overlapped boundary or the fourth overlapped boundary, and the second supplementary cell and the first supplementary cell are respectively positioned at two sides of the third overlapped boundary or the fifth overlapped boundary, thereby forming a combined cell with a third height.
The first supplementary cell and the second supplementary cell may have the same or different heights.
In one embodiment, H1 is 9T, H2 is 6T, the height of each of the first and second supplemental cells is 1.5T, and R is 1/2.
In another embodiment, H1 is 10.5T, H2 is 6T, the height of each of the first and second supplemental cells is 0.75T, and R is 1/2.
In yet another embodiment, H1 is 7.5T, H2 is 6T, the height of each of the first and second supplemental cells is 0.75T, and R is 2/3.
Fig. 3 illustrates another layout structure of an integrated circuit, which is formed of a number of standard cells a2, standard cells B2, supplemental cells C2, and supplemental cells C3. For one of the standard cell a2, the standard cell B2, the complementary cell C2, and the complementary cell C3, the lower boundary of the complementary cell C2 overlaps the upper boundary of the standard cell B2 to form an overlapping boundary, the upper boundary of the complementary cell C3 overlaps the lower boundary of the standard cell B2 to form another overlapping boundary, the complementary cell C2 and the standard cell B2 are respectively located on both sides of the one overlapping boundary, and the complementary cell C3 and the standard cell B2 are respectively located on both sides of the other overlapping boundary, thereby forming the combined cell 310 (hatched area in fig. 3). The standard cell a2 and the combined cell 310 are adjacent to each other, and a supplementary cell D2 is disposed therebetween.
Net (net) information associated with a power line in the first standard cell, the second standard cell, and/or the supplemental cell may be determined, and a power port thereof may be coupled to the VDD power rail and a ground port thereof may be coupled to the VSS power rail based on the net information.
For example, in fig. 2, net information is determined about the power lines of standard cell a1 and standard cell B1 and supplemental cell C1, with their respective power ports coupled to the VDD power rail and their respective ground ports coupled to the VSS power rail based on the net information (where the VSS power rail coupled to the ground port of supplemental cell C1 is not shown); in fig. 3, net information is determined about the power lines of standard cell a2, standard cell B2, and supplemental cells C2, C3, with their respective power ports coupled to the VDD power rail and their respective ground ports coupled to the VSS power rail based on the net information (where the VSS power rail coupled to the ground port of supplemental cell C2 and the VDD power rail coupled to the power port of supplemental cell C3 are not shown).
The net information can be imported into an Electronic Design Automation tool (EDA for short) in the form of a netlist (netlist) file, and the EDA can determine an optimized bridging scheme of a power line, and connect the cells based on the scheme, so that a desired chip layout can be obtained.
An embodiment of the present invention further provides an integrated circuit, which includes: first and second standard cells adjacent or neighboring each other in a column direction, one of the first and second standard cells having a first height and the other having a second height unequal to the first height; and the supplementary cell, the transverse boundary of the supplementary cell and the transverse boundary of the one are overlapped to form an overlapping boundary, and the supplementary cell and the one are respectively positioned at two sides of the overlapping boundary, so that a combined cell with a third height is formed, wherein the second height has a multiplying power relation with the third height.
As shown in fig. 2, the integrated circuit 200 includes a standard cell a1 and a standard cell B1 adjacent to each other in the column direction, and further includes a supplemental cell C1. Standard cell a1 has a second height, standard cell B1 has a first height, the first height is not equal to the second height; the lateral boundary of the supplementary cell C1 and the lateral boundary of the standard cell B1 overlap to form an overlapping boundary, and the supplementary cell C1 and the standard cell B1 are respectively located at both sides of the overlapping boundary, thereby forming a combined cell 210 having a third height, wherein the second height has a magnification relationship compared to the third height.
As shown in fig. 3, the integrated circuit 300 includes a standard cell a2 and a standard cell B2 adjacent to each other in the column direction, and further includes supplemental cells C2 and C3. Standard cell a2 has a second height, standard cell B2 has a first height, the first height is not equal to the second height; the lower boundary of the supplementary cell C2 overlaps the upper boundary of the standard cell B2 to form an overlapping boundary, the upper boundary of the supplementary cell C3 overlaps the lower boundary of the standard cell B2 to form another overlapping boundary, the supplementary cell C2 and the standard cell B2 are respectively located at both sides of the one overlapping boundary, and the supplementary cell C3 and the standard cell B2 are respectively located at both sides of the other overlapping boundary, thereby forming the combined cell 310 having a third height, wherein the second height has a multiplying factor relationship with respect to the third height.
In a specific implementation, the magnification relationship is a magnification relationship of 1, 1/2, 2/3, 3/4, 3/5, 4/5, or 5/6.
In one embodiment, the integrated circuit includes a VDD power rail and a VSS power rail, and the power port of the first standard cell, the second standard cell, and/or the complementary cell is coupled to the VDD power rail and the ground port is coupled to the VSS power rail.
In one embodiment, the supplementary cells include N supplementary cells, where N is a positive integer, the N supplementary cells are sequentially overlapped by lateral boundaries to form a first combination, the height of the first combination is a sum of the heights of the N supplementary cells, a lower boundary of the first combination overlaps an upper boundary of the one or an upper boundary of the first combination overlaps a lower boundary of the one to form a first type of overlapping boundary, and the first combination and the one are respectively located on both sides of the first type of overlapping boundary, thereby forming a combined cell having a third height.
In embodiments, the supplementary cells include a supplementary cell, a lower boundary of the supplementary cell overlaps an upper boundary of the one or an upper boundary of the supplementary cell overlaps a lower boundary of the one to form a first overlapping boundary, and the supplementary cell and the one are respectively located on both sides of the first overlapping boundary to form a combined cell having a third height.
In one embodiment, the first height is 9T, the second height is 6T, the height of a complementary cell is 3T, and the ratio is 1/2.
In one embodiment, the first height is 10.5T, the second height is 6T, the height of a complementary cell is 1.5T, and the multiplying factor relationship is 1/2.
In one embodiment, the first height is 7.5T, the second height is 6T, and the height of a complementary cell is 1.5T, and the multiplying factor relationship is 2/3.
In an embodiment, the supplementary cells include N supplementary cells, where N is a positive integer, the N supplementary cells are divided into two groups, each group including M supplementary cells and N-M supplementary cells, the M supplementary cells of the first group being sequentially overlapped by a lateral boundary to form a second combination, the height of the second combination being the sum of the heights of the M supplementary cells, the N-M supplementary cells of the second group being sequentially overlapped by a lateral boundary to form a third combination, the height of the third combination being the sum of the heights of the N-M supplementary cells; the lower boundary of the second combination and the upper boundary of the one overlap to form a second-type overlap boundary, the upper boundary of the third combination and the lower boundary of the one overlap to form a third-type overlap boundary, or the upper boundary of the second combination and the lower boundary of the one overlap to form a fourth-type overlap boundary, the lower boundary of the third combination and the upper boundary of the one overlap to form a fifth-type overlap boundary, the second combination and the one are respectively located on both sides of the second-type overlap boundary or the fourth-type overlap boundary, and the third combination and the one are respectively located on both sides of the third-type overlap boundary or the fifth-type overlap boundary, thereby forming a combination cell having a third height.
In one embodiment, the supplementary cells include a first supplementary cell and a second supplementary cell, a lower boundary of the first supplementary cell overlaps an upper boundary of the one to form a second overlapping boundary and an upper boundary of the second supplementary cell overlaps a lower boundary of the one to form a third overlapping boundary, or an upper boundary of the first supplementary cell overlaps a lower boundary of the one to form a fourth overlapping boundary and a lower boundary of the second supplementary cell overlaps an upper boundary of the one to form a fifth overlapping boundary, the first supplementary cell and the one are respectively located at both sides of the second overlapping boundary or the fourth overlapping boundary, and the second supplementary cell and the one are respectively located at both sides of the third overlapping boundary or the fifth overlapping boundary, thereby forming a combined cell having a third height.
In an implementation, the first supplemental cell and the second supplemental cell have the same or different heights.
In one embodiment, the first height is 9T, the second height is 6T, the heights of the first supplementary cell and the second supplementary cell are both 1.5T, and the magnification relationship is 1/2.
In one embodiment, the first height is 10.5T, the second height is 6T, the heights of the first supplementary cell and the second supplementary cell are both 0.75T, and the multiplying power relationship is 1/2.
In one embodiment, the first height is 7.5T, the second height is 6T, the heights of the first supplementary cell and the second supplementary cell are both 0.75T, and the multiplying power relationship is 2/3.
For the specific principle, implementation mode, and the like of the integrated circuit in the embodiment of the present invention, reference may be made to the above description about the method for laying out the integrated circuit in conjunction with fig. 1 to 3, which is not described herein again.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (28)
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Application publication date: 20211203 |