JP2001274364A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure a sufficient read margin concerning an applied voltage in the read operation. SOLUTION: A non-volatile semiconductor memory device 800 is a memory cell M provided with plural word lines WL, a plurality of bit lines MBL and SBL and a plurality of memory cells M which are respectively composed of a source 22a, a drain 22b, a floating gate 24, and a control gate 26. The device has the virtually grounded array structure of connecting the control gates to the word lines, and commonly connecting the sources of the respective memory cells and the drains of the adjacent memory cells connected to the same word line to one bit line. Among the plurality of memory cells, the plural first memory cells connected to one word line are divided into at least two groups, so that the read operation can be performed for the unit of one group, and between two adjacent groups, an isolation means IS is provided for blocking the flow of a current between the memory cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device constituted by floating gate nonvolatile memory cells and having a virtual ground type memory array structure.

[0002]

2. Description of the Related Art A flash memory (nonvolatile memory) having a memory array structure of a virtual ground type in which two memory cells share the same bit line has been proposed for the purpose of achieving high integration. For example, IEDM Technical
Digest, pp 269-270, 1995 "ANew cell Structure for
Subquarter Micron High Density Flash Memory ”,
IEICE Technical Report, ICD 97-21, P 37, 1997 ”
ACT (Asymmetrical Contactless Transisto)
r) type flash memory. The ACT flash memory uses an FN (Fowler-Nordheim) tunnel phenomenon in a program (write) / erase (erase) operation, and is expected to be used as a data storage type.

The configuration of the ACT flash memory 100 will be described with reference to FIGS.

FIG. 1 shows an ACT type flash memory 100.
2 shows a plan configuration. As shown in FIG. 1, the ACT flash memory 100 includes a plurality of word lines WL (WL
, WL31) and a plurality of main bit lines MBL (MBL0, MBL1,..., MBL1).
6) and a plurality of sub-bit lines SBL (SBL0, SBL) provided corresponding to the plurality of main bit lines MBL, respectively.
BL1,..., SBL16) and a plurality of word lines WL.
And a plurality of ACT-type flash memory elements (memory cells) M provided in the vicinity of the intersection with the plurality of main bit lines MBL and arranged in a matrix. The main bit line MBL is formed of a metal layer, and the sub bit line SBL is formed of a diffusion layer. The ACT type flash memory 100 further controls the transistor Tr to thereby control the desired bit lines (MBL and SBL).
BL) for selecting the gates.
Having. A voltage of 6 V is applied to the select gate selection signal line SG, whereby the select transistor Tr having a gate connected to the select gate selection signal line SG is turned on. The memory cell M has a source 22
a, a drain 22 b, a floating gate 24 and a control gate 26.

The main bit line MBL and the sub bit line SB
L is connected to each other by a metal-diffusion contact (indicated by a black square in FIG. 1), and the source 22a and the drain 22b of the memory cell M are connected to the sub-bit line SBL by a diffusion layer (indicated by a black circle in FIG. 1). It is connected. The source 22a of the memory cell M and the drain 22 of the adjacent memory cell M connected to the same word line WL
b are commonly connected to one sub-bit line SBL to form a virtual ground type array structure.

An ACT flash memory 100 utilizing the FN tunnel phenomenon for writing and erasing has two bit lines, a main bit line MBL and a sub bit line SBL, and a sub bit line SBL which is a part of the bit line.
Is formed by a diffusion layer. As a result, the number of contacts is reduced and the array area is significantly reduced, so that high integration is possible.

The sectional structure of the ACT type flash memory 100 will be described with reference to FIG. FIG. 2 is a sectional view taken along line II-II in FIG.

In the ACT type flash memory 100, a diffusion layer 21 forming a sub-bit line SBL is formed in a substrate (p-well) 20, and a part of the diffusion layer 21 serves as a source 22a and a drain 22b of the memory cell M. Constitute. A channel region 22c exists between the source 22a and the drain 22b. Further, a floating gate 24 and a control gate 26 are provided on the substrate 20 via an interlayer insulation layer 23. The control gates 26 are connected to each other by word lines WL. A main bit line MBL is provided above the word line WL via an interlayer insulation layer 23. Note that a common sub-bit line SBL of two adjacent memory cells M provided below an end portion of the adjacent floating gate 24 is
The donor concentration differs between the source 22a side and the drain 22b side.

The write, erase and read operations of the ACT flash memory 100 will be described below.

First, a write operation (program) of the ACT flash memory 100 will be described with reference to FIG. FIG. 3 shows a configuration corresponding to FIG. 1 and shows voltages applied to respective parts at the time of writing. Here, a case where data is written to the memory cells M01 and M04 will be described as an example.

[0011] A voltage of 6 V is applied to the select gate selection signal line SG, and the select transistor Tr having a gate connected to this signal line is turned on. Then, a negative high voltage Vneg (for example, −12 V) is applied to the word line WL0 to which the control gates 26 of the memory cells M01 and M04 to be written are connected. On the other hand, word lines WL1 to WL3 to which the respective control gates of the memory cells to which writing is not performed are connected.
1 is applied with a reference voltage (for example, 0 V). And
Drain 22b (n ⁺ type) of memory cells M01 and M04
To apply a write voltage to the main bit line MB
A positive voltage (for example, 4 V) is applied to L2 and MBL5. The voltage applied to the main bit lines MBL2 and MBL5 is changed from the main bit line to the metal-diffusion interlayer contact, the select transistor Tr, and the sub bit line S.
The voltage is applied to the drains 22b of the memory cells M01 and M04 via BL2 or SBL5. Further, sub bit lines SBL1 and SBL connected to source 22a
4 is open and floating. Further, the drain 22b of the memory cell to which writing is not performed
And the main bit line M to which the source 22a is connected
BL0, MBL1, MBL3, MBL4, MBL6, M
BL7 and MBL8 are also set to the floating state. In addition,
The substrate (p-well) 20 (see FIG. 2) is set to a reference voltage (for example, 0 V).

Under such voltage conditions, the memory cell M
01 and M04 cause an FN tunnel phenomenon at each drain side, and each floating gate 24
2b (n ⁺ type), electrons are extracted and the memory cell M01
And the threshold value of M04 decreases.

In general, writing is performed alternately with writing and verifying for verifying a threshold value of a memory cell by writing, and an operation is performed so that a predetermined value is obtained while verifying a threshold value of a memory cell. I do. When the verify operation confirms that the threshold value of the memory cell has dropped to, for example, about 1 to 2 V, the write operation is completed.
The memory cell to which no writing is performed maintains the threshold value before writing, for example, the threshold value in the erased state.

Next, an erasing operation (erase) will be described with reference to FIG.

Erasing is performed by the ACT type flash memory 100.
Of all memory cells at once or a plurality of memory cells M
May be divided into one or more blocks. FIG. 4 shows a state where the memory cell M is divided into two blocks.
Here, a case where the block 0 selected by the select gate selection signal line SG0 is erased will be described.

0 V is applied to select gate selection signal line SG0.
Is applied, and the select transistor Tr0 having the gate connected to this signal line is turned on.
On the other hand, a voltage of -9 V is applied to the select gate selection signal line SG1 corresponding to the block 1 on which erasing is not performed, and the select transistor Tr1 having a gate connected to this signal line is turned off. The word lines WL0 to WL31 connected to the control gate 26 of the memory cell M0 in the block 0 apply a positive high voltage (for example, 1
2V) and a high negative voltage (eg, -9 V) is applied to the substrate (p-well) 20 (see FIG. 2). Further, a negative high voltage (for example, −9 V) is applied to all the main bit lines MBL0 to MBL8.

In the block 0 in which the select transistor Tr0 is turned on by the application of the voltage, the metal-diffusion interlayer contact, the select transistor Tr0 and the sub-bit line S
Through the BL, a voltage of -9 V is applied to the drain 22b and the source 22a of the memory cell M0. Thereby, the channel region 22c of all the memory cells M0 in the block 0
2 (see FIG. 2), an FN tunnel phenomenon occurs, electrons are injected from each channel region 22c into each floating gate 24, and the threshold value of the memory cell rises.

Normally, the above-mentioned erasing and the verifying for verifying the threshold value of the memory cell are alternately performed, and the operation is performed so that the threshold value of the memory cell becomes a predetermined value while verifying the threshold value. If the verify operation confirms that the threshold value of the memory cell has increased to, for example, about 4 to 6 V, the erase operation is completed.

On the other hand, in the block 1 in which erasing is not performed, since the select transistor Tr1 is turned off, the drain 22b of the memory cell M1 in the block 1 is turned off.
And the source 22a are in a floating state. Further, since a reference voltage (for example, 0 V) is applied to the word lines WL32 to WL63 in the block 1, erasing is not performed.

Finally, a read operation (read) will be described with reference to FIG. FIG. 5 shows a configuration corresponding to FIG. 3 referring to the write operation. Here, a case where data is read from the memory cells M02 and M07 will be described as an example.

A voltage of 3 V is applied to the select gate selection signal line SG, and the select transistor Tr having a gate connected to this signal line is turned on. Then, a positive voltage (for example, 3 V) is applied to the word line WL0 to which the control gates 26 of the memory cells M02 and M07 to be read are connected. On the other hand, a reference voltage (for example, 0 V) is applied to the word lines WL1 to WL31 to which the control gates 26 of the memory cells M to which no reading is performed are connected. The substrate (p-
Well 20 (see FIG. 2) is a reference voltage (for example, 0 V)
To

Connected to the memory cells M00 and M01 on the source 22a side of the memory cell M02 from which reading is performed;
A voltage of 0 V is applied to the three main bit lines MBL0, MBL1, MBL2. Also, it is connected to the memory cells M03 and M04 on the drain 22b side of the memory cell M02.
Regarding the two main bit lines MBL3 and MBL4,
After a voltage of 1 V is precharged, a floating state is set. Then, the next main bit line MBL5 line has
A voltage of 1 V is applied to prevent a sneak current.
Further, the next two adjacent main bit lines MBL6, MBL
BL7, like the main bit lines MBL3 and MBL4, is precharged with a voltage of 1 V and then brought into a floating state.

In the example of FIG. 5, an 8-bit unit (MBL8n
~ MBL8n + 7, n = 0, 1, 2, 3, ...)
The above voltage pattern is applied repeatedly. When the select transistor Tr is turned on, the above-mentioned voltage is applied from the main bit line MBL to the metal-diffusion interlayer contact, the select transistor Tr, and the sub-bit line SBL.
Is applied to the drain 22b and the source 22a of the memory cell M.

By applying such a voltage, the memory cell M
If a potential difference of 1 V is generated between the drain and the source of the memory cell M02 and the threshold voltage of the memory cell M is lower than the word line voltage (for example, 3 V) applied to the word line WL0 (for example, about 1 to 2 V) , The current flows through the memory cell M, and the precharged voltage drops. If the threshold value of the memory cell is higher than 3 V (for example, the threshold value of the memory cell in an erased state of about 4 to 6 V), no current flows through the memory cell, and the precharged voltage drops. Absent. These voltage changes are detected by sense amplifiers (not shown) in which the input stage is connected to the leading ends of the main bit lines MBL3 and MBL7 and whose input stage is in a high impedance state, and are read as data 0 or 1.
Note that reading is not performed because a voltage of 0 V is applied to the word lines WL1 to WL31.

As described above, writing, erasing and reading of the ACT type flash memory having the virtual ground type array configuration are performed.

Since the ACT type flash memory has a virtual ground type array structure, the memory cells connected to the same word line are electrically connected to each other. Therefore, there is a problem that when reading is performed on one memory cell, the reading operation is affected by the state of the peripheral memory cells.

This problem will be described with reference to FIG. In FIG. 6, to simplify the description, the word line WL connected to the control gate 26 of the memory cell M1 to be read and the memory cell M1 connected thereto
Only ~ M8 are shown. The main bit line MBL, select transistor Tr, and the like shown in FIG. 5 are omitted. In FIG. 6, it is assumed that memory cells M1 to M8 are in a write state with a low threshold value (2 V or less).

First, a voltage of, for example, 3 V is applied to the word line WL. A voltage of 0 V is applied to the sub bit line SBL0 connected to the source 22a of the memory cell M1. On the other hand, the sub-bit line SBL1 connected to the drain 22b of the memory cell M1 is brought into a floating state after a voltage of 1 V is applied as a precharge. The sub bit line SBL2 connected to the drain 22b of the adjacent memory cell M2 is also brought into a floating state after a voltage of 1 V is applied as a precharge. Further, in order to prevent a sneak current into the memory cells M4 to M8,
A voltage of 1 V is applied to sub-bit line SBL3. This voltage corresponds to the main bit line MBL described with reference to FIG.
5 corresponds to the voltage applied.

The significance of applying a voltage of 1 V to the sub-bit line SBL3 is as follows. When the memory cell M1 to be read has a high threshold value (4 V or more), the memory cell M1
Consider a case where 2 to M8 have a low threshold value (2 V or less). If a voltage of 1 V is not applied to the sub-bit line SBL3, a current of 0 V is applied to the sub-bit line SBL8 connected to the drain of the memory cell M8.
Flows through the memory cells M2 to M8 having a low threshold value toward the sub-bit line SBL8. For this reason, the sub-bit line SBL1 which should not be reduced in voltage
Causes the voltage to drop, and as a result, the memory cell M1 is erroneously read as a write state. By applying a voltage of 1 V to the sub-bit line SBL3, the threshold states of the memory cells M4 to M8 do not affect the reading of the memory cell M1.

However, the voltage of 1 V applied to the sub-bit line SBL3 causes the memory cell M1 to be read out to be read out.
Is lower (the threshold is a write state of 2 V or less), the precharged sub-bit line S
As the potentials of BL1 and SBL2 decrease, a current flows from the sub-bit line SBL3 to the memory cell M1 via the memory cells M2 and M3 whose threshold values are low and in the written state. This unnecessary sneak current causes array noise, whereby the potential of the sub-bit line formed by the diffusion layer having a high resistance increases, and the voltage of the source 22a of the memory cell M1 becomes higher than 0V. As a result, the decrease in the potential of 1 V precharged to the sub bit line SBL1 connected to the drain 22b of the memory cell M1 is reduced, that is, the source 2 of the memory cell M1 is reduced.
The potential difference between 2a and drain 22b is reduced. As a result, when a current is detected by a sense amplifier (not shown) connected to the sub-bit line SBL1, the threshold value of the memory cell M1 becomes apparently higher.

In the case where binary data (write and erase) is stored in one memory cell as described above, a read margin, that is, a range of 2 V or less in a write state and 4 V or more in an erase state is secured to some extent. Therefore, the apparent change in the threshold value of the memory cell is not a big problem yet.

[0032]

By the way, as one of attempts to achieve higher integration, a multi-valued technology for introducing a threshold value of three or more values into one memory cell has been announced. For example, 1997 ISSCCDig. Tech. Papers, pp 36-37
“A 98mm2 3.3V 64Mb Flash Memory with FN-NORType 4
-level cell "and the method described in Japanese Patent Application Laid-Open No. H6-177397.
Using an N-NOR type flash memory, a drain voltage is changed according to write data, and a write pulse is simultaneously applied to flash memory cells to be written. In recent years, the 1999 ISSCC Dig. Tech. Pa.
pers, pp 110-111 "A 256Mb Multilevel Flash Memory
with2MB / s Program Rate for Mass Storage Applicatio
ns ". This document proposes a multi-valued data reading method and a data rewriting method for each sector.

As described above, as the number of levels of data stored in the memory cells increases, the read margin decreases, and as a result, the possibility of erroneous read increases. This problem will be described in more detail with reference to FIG.

FIG. 7 schematically shows a threshold distribution for each data when multi-valued data, for example, quaternary data is stored in a memory cell. As shown in FIG. 7, the threshold distribution of the memory cell at the time when each data is written is the data “0”.
In the case of "0", for example, 0.6 to 1.0 V, in the case of data "01", for example, 1.6 to 2.0 V, in the case of data "10", for example, 2.6 to 3.0 V, and in the case of data "11", for example, It becomes 3.6 V or more (erased state).

The writing, erasing and reading of these data are performed as follows. For a write operation, a high negative voltage is applied to the word line connected to the control gate of the memory cell to be written, and the voltage applied to the drain of the memory cell to be written is changed by the write voltage depending on the data, or the write time is changed. Is written to the memory cell as multi-value data. At this time, the threshold voltage is set to a desired value while alternately performing writing and verifying for verifying the threshold voltage.

The erasing operation is performed in units of blocks or collectively by the same method as in the case of binary described above.

In the read operation, as shown in FIG. 7, first, a read voltage (for example, 2.3 V) is applied to a word line, and a current flows through a memory cell to be read (the precharged voltage decreases). ) To detect if. If a current flows, it can be determined that the data of the memory cell is "00" or "01". Next, a read voltage (for example, 1.3 V) is applied to the word line, and if a current flows through the memory cell (when the precharged voltage decreases), the data written in the memory cell is reduced. “0
If it is determined as “0” and no current flows through the memory cell (the precharged voltage does not decrease), the data “01”
Will be read.

On the other hand, when the current does not flow at the above read voltage, a read voltage (eg, 3.3 V) is applied to the word line, and the data “10” and the data “11” are applied according to the same principle as described above. "Can be read. Such a reading method is one example, and another method may be used.

In the case of reading as described above, the sneak current described with reference to FIG. 6 causes the threshold value of each data to be shifted to an apparently higher side, and the broken lines (a) and (b) in FIG. As shown in (1), the threshold distribution spreads. Since the memory cell to which data "11" is written is read at the highest read voltage, no current flows to the memory cell to which other data is written, so that no sneak current occurs, and No apparent spread occurs. On the other hand, data “0”
On the other hand, a memory cell in which “0” is written is read by applying the lowest read voltage to the word line, so that no current flows in a memory cell in which other data is written.
Further, in the memory cell in which the data “00” is written, the back gate effect operates and the current hardly flows due to the potential precharged to the bit line existing in the vicinity thereof. The number is much smaller than the memory cells and the memory cell of data “10”. Therefore, the apparent spread of the threshold value of data “00” can be ignored compared to the case of data “01” and data “10”.

As described above, when data "01" or data "10" is read, a sneak current is generated via a memory cell having a lower threshold value in a memory cell array connected to the same word line. The problem of flowing occurs. Under the influence of this unnecessary current, as described above, the potential of the sub-bit line formed by the diffusion layer having a high resistance rises and is precharged to the bit line originally connected to the memory cell from which reading is performed. The decrease in the voltage is reduced, and as a result, as shown in FIG. 7, the threshold distribution apparently spreads toward a higher value.

Therefore, data "01" and data "1"
When the spread of the threshold distribution due to the sneak current occurs, for example, about 0.2 to 0.3 V, the separation width of the 0 "threshold distribution is further reduced by half from the initial narrow separation width of 0.6 V, and the read margin is reduced. When the displacement of the threshold distribution further advances, in the worst case, a read error may occur, and when the read margin decreases, the manufacturing conditions of the nonvolatile semiconductor device become severe, and Requirements for specifications such as temperature, power supply voltage, etc. also become strict, and in such a current situation, it is very difficult to further increase the number of values (more than four values).

The present invention has been made in view of the above circumstances, and it is an object of the present invention to ensure a sufficient read margin in a read operation, particularly in a read operation of multi-valued data. An object of the present invention is to provide a nonvolatile semiconductor memory device.

[0043]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a source region, a drain region, a floating gate, and a control gate. A control gate connected to a word line, and a source region of each memory cell and a drain region of an adjacent memory cell connected to the same word line share one bit line A plurality of memory cells having a virtual ground type array structure connected to a plurality of memory cells, and a plurality of first memory cells connected to one word line among the plurality of memory cells.
Are divided into two or more groups, and the read operation is performed in units of one group.
Isolation means is provided between two adjacent groups to prevent the flow of current between the memory cells, thereby achieving the above object.

In one embodiment, the isolation means is formed of an insulating film. The isolation means is preferably provided in a region corresponding to a channel region of the memory cell.

In one embodiment, the isolation means is constituted by a second memory cell having a higher threshold value than the plurality of first memory cells. A write operation is performed once on the second memory cell before the erase operation is performed.

In one embodiment, a plurality of data are stored in the first memory cell by setting different threshold values by writing.

In one embodiment, when data of a plurality of thresholds having different values is written to the first memory cell, the second memory cell stores the first threshold value among the plurality of threshold values. Since high data or the second highest data is stored, one data is stored using the second memory cell.

In the read operation, for the one group, a source region of a read memory cell to be read is applied with a voltage of 0 V, and a drain region of the read memory cell is brought into a floating state after being precharged with a voltage of 1 V. In the one group, all the bit lines connected to the memory cell on the source region side of the read memory cell are set to a voltage of 0 V, and connected to the memory cell on the drain region side of the read memory cell. All bit lines are set to a floating state after a voltage of 1 V is precharged.

The source and drain regions of the memory cell are connected to each other via a transistor.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of a nonvolatile semiconductor memory device according to the present invention will be described below. FIG. 8 shows a plan configuration of a nonvolatile semiconductor memory device 800 according to the present invention. As shown in FIG. 8, the nonvolatile semiconductor memory device 800 includes a plurality of word lines WL (W
L0, WL1,..., WL31) and a plurality of main bit lines MBL (MBL0, MBL1,.
9) and a plurality of sub-bit lines SBL (SBL0, SBL) provided corresponding to the plurality of main bit lines MBL, respectively.
BL1,..., SBL9) and a plurality of non-volatile semiconductor memory elements (memory cells) provided near intersections of the plurality of word lines WL and the plurality of main bit lines MBL and arranged in a matrix. ) M. The main bit line MBL is formed of a metal layer, and the sub bit line SBL is formed of a diffusion layer. The nonvolatile semiconductor memory device 800 further controls the transistor Tr so that the desired bit lines (MBL and SBL)
Select gate select signal line SG for selecting By applying a signal voltage to the select gate selection signal line SG, the select transistor Tr having a gate connected to this signal line is turned on. The memory cell M includes a source 22a, a drain 22b, a floating gate 24, and a control gate 26.

Main bit line MBL and sub bit line SB
L is connected to each other by a metal-diffusion contact (indicated by a black square in FIG. 8), and the source 22a and the drain 22b of the memory cell M are connected to the sub-bit line SBL by a diffusion layer (indicated by a black circle in FIG. 8). It is connected. The source 22a of the memory cell M and the drain 22 of the adjacent memory cell M connected to the same word line WL
b are commonly connected to one sub-bit line SBL to form a virtual ground type array structure.

Further, in the nonvolatile semiconductor memory device 800, a plurality of memory cells M (first memory cells) connected to one word line WL are divided into two or more groups, and two adjacent groups are divided into two groups. An isolation structure (isolation means) IS for preventing a current flow between the memory cells is provided therebetween. In FIG. 8, the region where the sub-bit line SBL shared by the sources and drains of the adjacent memory cells M07 and M09 is separated is the region of the isolation structure IS.
Here, eight memory cells M connected to the same word line WL constitute one group, an isolation structure is arranged for each group, and this pattern is repeated. In the present invention, the read operation is performed in units of one group. In FIG. 8, eight memory cells M constitute one group. However, it is needless to say that the number of memory cells M in one group is not limited to eight and may be another value. No.

In FIG. 8, the isolation means IS are shown at the same interval in each row and at the same position in the horizontal direction, but the present invention is not limited to this. Not done. The position of the isolation means IS may be different for each word line. This is the same for the following embodiments.

The sectional structure of the nonvolatile semiconductor memory device 800 will be described with reference to FIG. FIG. 9 is a sectional view taken along line IX-IX in FIG.

In the nonvolatile semiconductor memory device 800, a diffusion layer 21 forming a sub-bit line SBL is formed in a substrate (p-well) 20, and a part of the diffusion layer 21 is formed by a source 22a and a drain 22b of the memory cell M. Is configured. A channel region 22c exists between the source 22a and the drain 22b. Further, a floating gate 24 and a control gate 26 are provided on the substrate 20 via an interlayer insulation layer 23. The control gates 26 are connected to each other by word lines WL. A main bit line MBL is provided above the word line WL via an interlayer insulation layer 23. Note that a common sub-bit line SBL of two adjacent memory cells M provided below an end portion of the adjacent floating gate 24 is
The donor concentration differs between the source 22a side and the drain 22b side.

In this embodiment, the isolation structure IS is formed in a region corresponding to the channel region 22c of the memory cell M, that is, a portion which is to be the channel region 22c originally located below the floating gate 24 of the memory cell M. Have been. The formation method can be formed by a known technique such as, for example, removing a region that originally becomes the channel region 22c by etching and performing trench isolation using an insulating film such as an oxide film. It is preferable to form them by ration. In such a configuration, since the floating gate 24 and the like are arranged on the isolation region in the same manner as the original memory cells, the floating gate 24 and the like maintain an isolation structure IS while maintaining a pattern having regular intervals. Can be formed.

Hereinafter, a read operation using the nonvolatile semiconductor memory device 800 of the present invention will be described with reference to FIG. Note that the writing and erasing operations are basically the same as those described in connection with the related art, so that the description thereof will be omitted.

In FIG. 10, for the sake of simplicity, the control gate 26 of the memory cell M2 from which data is to be read is shown.
Are connected, and only the memory cells M1 to M9 connected thereto are shown. FIG.
The main bit line MBL, select transistor Tr, and the like shown in FIG.

In the read operation of the memory cells M connected to one word line, the read operation of one memory cell M is repeated eight times so that all the memory cells M are read. Further, the threshold value of the memory cell M is set to 2 V or less in the writing state and 4 V or more in the erasing state, as in the case of the related art. Here, a case where the memory cell M2 is read will be described as an example.

First, a voltage of, for example, 3 V is applied to the word line WL as a read voltage. Memory cell M
A voltage of 0 V is applied to the sub bit line SBL1 connected to the second source 22a. Further, a voltage of 0 V is applied to the sub bit line SBL0 connected to the source 22a of the memory cell M1 adjacent to the source 22a of the memory cell M2. This is to prevent the potential of the sub-bit line SBL formed of a diffusion layer having a high resistance from rising from 0 V due to a current flowing at the time of reading. Thus, even when the memory cell M1 has a low threshold value (2 V or less) in the written state, no sneak current flows through the memory cell M1.

On the other hand, the bit line SBL2 connected to the drain 22b of the memory cell M2 from which data is to be read is brought into a floating state after applying a voltage of 1 V as precharge. Further, the drain 22b of the memory M2
The sub bit lines SBL3 to SBL8 connected to the drains 22b of the memory cells M3 to M8 on the side are also brought into a floating state after precharging with a voltage of 1V. The voltage application pattern as shown in FIG. 10 is repeated for every eight memory cells (one group).

By applying such a voltage, the memory cell M
Even if 3-M8 has a low threshold value (2 V or less) in the written state, no sneak current flows through memory cells M3-M8 due to the back gate effect. Therefore, the generated current depends on the memory cell M to be read.
2 only. When the memory cell M2 is in a write state, a current flows through the cell, and the drain voltage precharged to a potential of 1 V decreases. on the other hand,
When the memory cell M2 is in the erased state, no current flows through the cell, so that the voltage precharged to 1 V does not decrease. This change in the drain voltage is detected by a sense circuit (not shown) connected to the bit line connected to the drain, and is read as data “1” or data “0”.

By performing this read operation on each memory cell M between the isolation structures IS, it is possible to complete reading of all the memory cells M connected to the same word line. In the present embodiment, by performing the above-described read operation eight times, the read operation of all the memory cells M connected to the same word line can be completed.

According to the present embodiment, since unnecessary sneak current does not occur, apparently a problem in the prior art appears.
There is no spread of the threshold distribution due to detection as a state where the threshold is high, and as a result, the problem that the read margin becomes unnecessarily narrow can be solved.

In the present embodiment, as described above, since the isolation structure IS is provided in the region corresponding to the channel region 22c of the memory cell M, a pattern in which the floating gate 24 and the like have regularity at equal intervals is formed. While maintaining this, the isolation structure IS can be formed. This contributes to the formation of a stable memory cell having uniform characteristics. The shape of the floating gate
Usually, this has a great effect on the characteristics of the memory cell. The precision of the shape depends on the exposure conditions and etching conditions in the manufacturing process, but these conditions are strongly affected by the above-mentioned pattern. According to the present embodiment, it is possible to maintain the pattern of the floating gate that maintains regularity, and the variation in the shape of the floating gate and the like due to the influence of light interference at the time of exposure that occurs when the regularity is lost. A memory cell with uniform characteristics and no generation can be formed.

(Second Embodiment) A nonvolatile semiconductor memory device according to a second embodiment of the present invention will be described below.
The difference between the present embodiment and the first embodiment is that, instead of the isolation structure IS (see FIG. 9 relating to the first embodiment) by trench isolation using an insulating film as an isolation means, another memory is used. The point is that a memory cell having a higher threshold than the cell is used. More specifically, in the present embodiment, for example, a memory cell in an erased state having a high threshold value is used as the isolation means without specially providing the isolation structure IS. The configuration of the nonvolatile semiconductor memory device according to the present embodiment other than the isolation unit is the same as that of the first embodiment.

A read operation using the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.
FIG. 11 basically corresponds to the configuration shown in FIG.
To simplify the description, the memory cell M from
Word line WL to which two control gates 26 are connected, and some memory cells M connected thereto.
Only 1, M2, M3, M4, M5,..., Mn are shown. The main bit line MBL, select transistor Tr, and the like as shown in FIG. 8 are omitted. Note that the writing and erasing operations are basically the same as those described in connection with the prior art, so that the description thereof will be omitted.

In FIG. 11, a memory cell Mn (second memory cell) functions as isolation means.
The memory cell Mn is a memory cell M1,
.. (First memory cell), for example, a threshold value of 4 to 6 V (here, an erased state). By arranging the isolation means formed of the memory cells Mn for every eight memory cells connected to the same word line, for example, the read operation as described in the first embodiment can be performed.

The case where the memory cell M2 is read will be described as an example. The read operation of the memory cell M connected to one word line is performed in the same manner as in the case of FIG.
Is repeated eight times, so that all the memory cells M
Is trying to read. Further, the threshold value of the memory cell M is set to 2 V or less in the writing state and 4 V or more in the erasing state, as in the case of the related art.

First, the memory cell M2 to be read is
Word line W to which the control gate 26 is connected
For example, a voltage of 3 V is applied to L. Then, a voltage of 0 V is applied to the source 22a of the memory cell M2. On the other hand, the sub-bit line SBL2 is brought into a floating state after being precharged to a voltage of 1V. The sub-bit line SB connected to the drain of the memory cell connected to the source 22a of the memory cell M2 (when there is another memory cell between the memory cell Mn and the memory cell M1).
A voltage of 0 V is applied to L. On the other hand, memory cells (M3, M4, M4) connected to the drain 22b side of the memory M2
5,...) Sub-bit lines (SBL3, SBL
4,...) Are precharged to a voltage of 1 V and then set to a floating state.

By applying such a voltage, the memory cell M
Even if 3, M4, M5,... Have a low threshold value (2 V or less) in the written state, a sneak current flows through these memory cells M due to the back gate effect. There is no. Therefore, the generated current is only the current flowing through the memory cell M2 to be read. Memory cell M
When 2 is in the written state, a current flows through the cell, thereby lowering the drain voltage precharged to a potential of 1V. On the other hand, when the memory cell M2 is in the erased state, no current flows through the cell, so that the voltage precharged to 1 V does not decrease. This change in drain voltage is
The data is detected by a sense circuit (not shown) connected to the bit line connected to the drain, and is read as data “1” or data “0”.

By performing this read operation on each memory cell between the memory cells Mn of the isolation means, the read operation of all the memory cells M connected to the same word line can be completed. In the present embodiment, by performing the above-described read operation eight times, the read operation of all the memory cells M connected to the same word line can be completed.

According to this embodiment, since unnecessary sneak current does not occur, apparently a problem in the prior art
There is no spread of the threshold distribution due to detection as a state where the threshold is high, and as a result, the problem that the read margin becomes unnecessarily narrow can be solved.

According to the present embodiment, the regularity of all the layouts of the device can be completely maintained without being disturbed by the formation of the isolation means. Therefore, under the same exposure conditions and etching conditions, a normal memory cell for performing storage / reproduction and a memory cell as an isolation means can be formed. That is, a memory cell having uniform characteristics can be stably manufactured without being affected by isolation formation.

In this embodiment, when erasing is performed with respect to the memory cell Mn for the isolation means together with other memory cells, the memory cell M is used immediately before the erasing voltage is applied.
It is preferable to perform writing by applying a writing voltage to n. That is, once lowering the threshold value of the memory cell Mn for the isolation means, the potential of the floating gate is prevented from rising excessively. By doing so, the memory cell Mn for isolation is used.
However, there is a danger that the potential of the floating gate will increase due to excessive erasing, and that the reliability of the memory cell will be impaired due to the continued application of excessive electric field stress to the insulating film covering the floating gate. can avoid.

Although the above description has been made with respect to a memory cell having a binary threshold value, the present invention is directed to a multi-level memory system in which three or more threshold values are introduced into one memory cell in order to achieve higher integration. It can be applied even when applying value technology. More specifically, the present invention can prevent the spread of the threshold distribution at the time of reading due to unnecessary sneak current, and thus can exhibit its effectiveness in a situation where the read margin is reduced due to multi-valued data. The present invention is effective even when the read margin associated with lowering the voltage is reduced in order to reduce the power consumption of the semiconductor memory device, separately from the multi-valued operation.

In the case where multi-level conversion is introduced, an ECC (Error Correcting Cod) for data correction is utilized by using the memory cell Mn for the isolation means in the second embodiment.
e) Data can be written. in this case,
The memory cell Mn for the isolation means has the highest threshold value (state “11” in FIG. 7) and the threshold value one level lower (“10” in FIG. 7).
State) is written as data,
CC data can be stored.

By adding this ECC data for each fixed data string, even if an error has occurred in the storage of the data string, the error can be detected or further corrected.
This makes it possible to realize a highly integrated semiconductor memory device with high reliability as a memory device. As described above, by using the memory cells Mn in the two threshold states, the isolation means can fulfill its original role of isolation and can be used for data storage. Thereby, the memory cells can be used with high efficiency.

In the first and second embodiments, the case where the isolation means is arranged for every eight (one group) of memory cells connected to the same word line has been described as an example. It is not limited to this. One group may be made up of, for example, 16 memory cells. In short, the isolation means may be appropriately arranged at regular intervals.

In the above description, the erased state is set to a state with a high threshold. However, the erased state and the written state are problems of the definition of the initial state. The present invention is applicable even if the erased state is a state with a low threshold. When the write state is defined as a state with a high threshold value, the memory cell for the isolation means in the second embodiment still uses a memory cell in a state with a high threshold value (write state).

In the above description, the ACT type flash memory is used. However, the present invention is not limited to the ACT type flash memory, and a virtual ground type array structure in which adjacent memory cells share a bit line is used. The same effect can be obtained if the nonvolatile semiconductor memory device has the same function. The present invention is particularly applicable to a nonvolatile semiconductor memory device in which a virtual ground type array structure is formed by using a high-resistance wiring (bit line) such as a diffusion layer or a fine wiring in order to achieve high integration. It is valid.

[0082]

As described above, according to the present invention, for example, a nonvolatile semiconductor memory having a virtual ground array structure in which two memory cells share the same bit line in which ACT type flash memory elements are arranged in an array, for example. In the device,
By inserting isolation means between the non-volatile memory elements at certain intervals, a data read operation without data interference between memory cells can be realized.

Further, by arranging the structure made of the insulating film constituting the isolation means at the place where the channel region of the normal cell is to be formed, the floating gate and the bit line can be formed continuously at a constant interval. Variations in the middle photo process can be suppressed. Further, by forming the isolation means with normal memory cells and using the memory cells as auxiliary memories for data correction, it is possible to minimize the area penalty caused by the isolation means.

[Brief description of the drawings]

FIG. 1 is a diagram showing a planar configuration of an ACT type flash memory according to a conventional example.

FIG. 2 is a sectional view taken along the line II-II in FIG.

FIG. 3 is a diagram showing a plan configuration of a conventional ACT type flash memory showing a voltage applied to each part at the time of writing.

FIG. 4 is a diagram showing a plan configuration of a conventional ACT type flash memory showing voltages applied to respective portions at the time of erasing;

FIG. 5 is a diagram showing a planar configuration of a conventional ACT type flash memory showing voltages applied to respective parts at the time of reading.

FIG. 6 is a partial plan view of the configuration of FIG. 1 showing a problem in a read operation according to a conventional example.

FIG. 7 illustrates a case where four-level data is stored in a memory cell.
The figure which shows the outline of the threshold value distribution about each data.

FIG. 8 is a diagram showing a plan configuration of a nonvolatile semiconductor memory device according to the present invention.

FIG. 9 is a sectional view taken along the line IX-IX in FIG. 8;

FIG. 10 is a partial plan view of the configuration of FIG. 9 showing voltages applied to respective parts at the time of reading according to the first embodiment;

FIG. 11 is a partial plan view of the configuration of FIG. 9 showing voltages applied to respective parts at the time of reading according to the second embodiment.

[Explanation of symbols]

 IS Isolation means M Memory cell MBL Main bit line SBL Sub bit line SG Select gate select signal line Tr Select transistor WL Word line 22a Source 22b Drain 24 Floating gate 26 Control gate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/788 29/792

Claims (9)

[Claims] 1. A plurality of memory cells each including a plurality of word lines, a plurality of bit lines, a source region, a drain region, a floating gate, and a control gate, wherein the control gate is connected to the word line. A source region of each memory cell and a drain region of an adjacent memory cell connected to the same word line have a virtual ground type array structure commonly connected to one bit line; A plurality of memory cells, wherein a plurality of first memory cells connected to one word line are divided into two or more groups, and the plurality of memory cells are read in units of one group. An operation is performed, and a non-volatile semiconductor device is provided between two adjacent groups, provided with an isolation unit for preventing a current flow between the memory cells. Body Symbol billion devices. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said isolation means is formed of an insulating film. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said isolation means is provided in a region corresponding to a channel region of said memory cell. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said isolation means is constituted by a second memory cell having a higher threshold value than said plurality of first memory cells. . 5. The nonvolatile semiconductor memory device according to claim 4, wherein a write operation is performed once on the second memory cell before an erase operation is performed. 6. The nonvolatile memory according to claim 1, wherein a plurality of data are stored in the first memory cell by setting different threshold values by writing. Semiconductor storage device. 7. When the data of a plurality of thresholds having different values are written in the first memory cell, the second memory cell stores the data having the highest value among the plurality of thresholds, 6. The non-volatile semiconductor storage device according to claim 4, wherein one data is stored using the second memory cell by storing the second highest data. 8. In reading, a voltage of 0 V is applied to a source region of a read memory cell from which data is to be read and a drain region of the read memory cell is in a floating state after a voltage of 1 V is precharged. In the one group, all bit lines connected to the memory cells on the source region side of the read memory cells are set to a voltage of 0 V, and connected to the memory cells on the drain region side of the read memory cells. 8. The nonvolatile semiconductor memory device according to claim 1, wherein all the bit lines to be set are brought into a floating state after a voltage of 1 V is precharged. 9. The memory cell, wherein a source region and a drain region are connected to each other via a transistor.
The nonvolatile semiconductor memory device according to claim 1.