JP2008065981A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a reduction in a read margin during reading of the memory is prevented. <P>SOLUTION: When a read operation is performed, a first switch is brought into conduction during a read period to a bit line to which a drain is connected, depending on a selected multilevel memory cell. A second switch is brought into conduction during the read period to a bit line provided on a side opposite to a first non-selected multilevel memory cell and connected to a second non-selected multilevel memory cell adjacent to the first non-selected multilevel memory cell sharing the bit line to which the drain is connected. The first switch is brought into conduction for an initial period and is thereafter brought into non-conduction to a bit line shared by the first non-selected multilevel memory cell and the second non-selected multilevel memory cell. The bit line to which the drain is connected and its adjacent bit line are charged at the same potential even transiently. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device configured by a virtual ground method.

  In recent years, a large-capacity and highly integrated memory is required. In recent years, a nonvolatile semiconductor memory device capable of reducing an effective cell area such as a multi-value method and a virtual ground method has been developed and put into practical use. .

  A virtual ground type semiconductor memory device has a structure in which two memory cells share the same bit line, and can be highly integrated. FIG. 5 is a schematic configuration diagram of a part of a conventional virtual ground nonvolatile semiconductor memory device.

  The semiconductor memory device 30 includes a virtual ground line VRG, a sense amplifier 31, a cascode circuit 32, a precharge circuit 33, and a selection circuit 34, and a plurality of bit lines BL1 to BL6 intersecting the word line WL. The memory cells M1 to M5 are connected in parallel. Each gate of the memory cells M1 to M5 is connected to the word line WL, and its drain and source are connected to any one of the bit lines BL1 to BL6.

  An operation at the time of reading from the memory cell M2 will be described. When reading data from the memory cell M2, first, for example, a voltage of 5V is applied to the word line WL. Then, the memory cells M1 to M5 are turned on. In addition, the virtual ground line VRG is connected to the bit line BL2 connected to the source s1 of the memory cell M2 by the selection circuit 34, and the cascode circuit 32 is connected to the bit line BL3 connected to the drain d1 of the memory cell M2. Are connected to each other. Here, a voltage of 1 V, for example, is applied to the bit line BL3 connected to the drain d1.

  On the other hand, the precharge circuit 33 is connected by the selection circuit 34 to the bit line BL4 on the opposite side of the memory cell M3 which is an adjacent cell sharing the bit line BL3 connected to the drain d1 of the memory cell M2, and the bit line BL3 The bit line BL4 is charged so as to have the same potential as the drain d1 of the memory cell M2 so that the current Ic flowing through the memory cell M3 does not flow into the unselected memory cell M3. The bit lines BL1, BL5, and BL6 connected to the memory cells M1, M4, and M5 are in a floating state that is not connected to either the power supply or the virtual ground.

  Here, the current Ids flowing between the drain d1 and the source s1 of the memory cell M2 does not flow much when the memory cell M2 is “0” in the writing state (hereinafter referred to as PGM state), and is in the erased state (hereinafter referred to as ERASE state). ) Is “1”. In the cascode circuit 32, the current Ic flowing through the bit line BL 3 is converted into a voltage and input to the sense amplifier 31. The sense amplifier 31 is connected to a reference circuit (not shown). By comparing a reference signal input to the sense amplifier 31 based on a reference current flowing therethrough, whether the memory cell M2 is in the PGM state or the ERASE state. Is output as data.

  For example, assume that a reference current of 15 μA flows through a reference circuit (not shown). In the sense amplifier 31, when the current Ic flowing through the bit line BL3 is larger than 15 μA, the storage state of the memory cell M2 is determined as the ERASE state, and when smaller than 15 μA, it is determined as the PGM state.

  Normally, some margin is provided in order to prevent an erroneous determination. For example, assuming that 10 μA flows in the PGM state and 20 μA in the ERASE state, a margin of ± 5 μA can be obtained if the reference current is 15 μA as described above.

  However, the conventional semiconductor memory device 30 has the following problems. FIG. 6 is a schematic configuration diagram of a part of the semiconductor memory device, and shows a combination of memory states having memory cells.

  First, as shown in FIG. 6, an operation at the time of reading when the storage state of the memory cell M2 is the PGM state and the storage states of the memory cells M3, M4, and M5 are all ERASE states will be described.

  When reading the memory cell M2, the memory cell M2 is in the PGM state and does not flow much current, so the potential of the drain d1 becomes slightly higher. At this time, the memory cell M3 which is an adjacent cell on the drain d1 side is in the ERASE state, and the memory cell M4 which is the adjacent cell is in the ERASE state. Since the ERASE state flows a large amount of current, it is the same as the drain d1. The potential of the bit line BL4 connected to the memory cell M3 charged to have a potential is slightly lowered. For this reason, the current Idp flows from the drain d1 to the memory cell M3 side. Since the sense amplifier 31 determines the storage state of the memory cell M2 based on the current Ic flowing through the bit line BL3, when the current Ic flowing through the read bit line BL3 becomes Ids + Idp, the current Ids flowing through the memory cell M2 originally is larger than the current Ids flowing through the memory cell M2. It seems to be flowing a lot.

  Thus, for example, if a reference current flowing through a reference circuit (not shown) to be compared by the sense amplifier 31 is 15 μA and normal Ids is 10 μA in the PGM state and 20 μA in the ERASE state, there is a margin of 5 μA, respectively. When Idp exceeds 5 μA, there is a problem that the sense amplifier 31 determines that the memory cell M2 is in the ERASE state even though the memory cell M2 is in the PGM state.

  FIG. 7 is a schematic configuration diagram of a part of the semiconductor memory device, showing a combination of memory states having memory cells. Here, the operation at the time of reading when the storage state of the memory cells M2 and M3 is the ERASE state and the storage state of the memory cells M4 and M5 are both the PGM state will be described.

  In this case, the memory cell M2 to be read is in the ERASE state, and a large amount of current flows, so the voltage of the drain d1 becomes slightly lower. At this time, since the memory cell M3 which is the adjacent cell on the drain d1 side is in the ERASE state and the memory cell M4 which is the adjacent cell is in the PGM state, the bit line BL4 does not flow much current, and the memory cell The voltage of the bit line BL4 connected to M3 becomes slightly higher. Therefore, the current Idp flows from the bit line BL4 on the memory cell M3 side to the drain d1. Since the sense amplifier 31 determines the storage state of the memory cell M2 based on the current Ic that flows through the bit line BL3, the current Ic that flows through the read bit line BL3 is Ids−Idp, and thus the current Ids that the memory cell M2 originally flows is. It seems to be less than.

  Thus, for example, if a reference current flowing through a reference circuit (not shown) to be compared by the sense amplifier 31 is 15 μA and normal Ids is 10 μA in the PGM state and 20 μA in the ERASE state, there is a margin of 5 μA, respectively. When Idp exceeds 5 μA, there is a problem that the sense amplifier 31 determines that the memory cell M2 is in the PGM state even though the memory cell M2 is in the ERASE state.

  The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor memory device that prevents a reduction in a read margin when reading from a memory.

  In the present invention, in order to solve the above-described problem, in a nonvolatile semiconductor memory device that accesses a multi-level memory cell by a virtual ground method, a plurality of the multi-level memory cells arranged in a matrix and a multi-level in a column direction A plurality of bit lines connected to the source or drain of the memory cell, a plurality of word lines crossing the bit line and connected to the gate of the multi-level memory cell in the row direction, and data in the selected multi-level memory cell A current supply circuit for supplying a read current and a precharge circuit for charging the bit line to a precharge voltage level are provided. Each bit line includes a first switch that connects the bit line and the current supply circuit, and a second switch that connects the bit line and the precharge circuit.

  According to the above structure, during reading, the first switch is turned on during the reading period for the bit line to which the drain is connected in accordance with the selected multi-level memory cell. Bit line opposite to the first non-selected multi-level memory cell connected to the second non-selected multi-level memory cell adjacent to the first non-selected multi-level memory cell sharing the bit line to which the drain is connected In contrast, the second switch conducts during the readout period. For the bit lines shared by the first non-selected multi-level memory cell and the second non-selected multi-level memory cell, the first switch is turned on at the initial stage of the read period and then turned off. Since both the bit line to which the drain is connected and the adjacent bit line are biased by the current supply circuit, they are charged while maintaining the same potential in a transient manner. The current flowing into and out of the drain of the selected memory cell can be reduced not only in the steady state but also in the transient state.

  As described above, in the present invention, at the time of reading, the drain of the memory cell to be read and the bit line in a floating state between the bit lines to be charged are charged only for a predetermined time. Current flow out to other memory cells and current flow into the drains of memory cells read from other memory cells can be prevented, and a reduction in margin at the time of reading can be prevented.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a semiconductor memory device of the present invention.

  The semiconductor memory device 1 has a plurality of memory cells Mmn (m is a natural number of 0 or more and n is a natural number of 1 or more) arranged in a matrix, and a word line WLm (m is connected to the gate of the memory cell Mmn). A memory cell array wired by a bit line BLn (n corresponds to n of the memory cell Mmn) crossing the word line WLm and connected to the source or drain of the memory cell Mmn (corresponding to m of the memory cell Mmn) Have.

  Furthermore, in order to perform writing to the memory cell Mmn or reading data from the memory cell Mmn, the semiconductor memory device 1 includes the following. A cascode circuit 2 having a current source for supplying current to the memory cell Mmn, a sense amplifier 3 for determining the storage state of the selected memory cell Mmn, and a pre-built-in current source for charging the bit line BLm A plurality of selection transistors ST that select which of the charge circuit 4, the cascode circuit 2, the precharge circuit 4, or the virtual ground line VRG is connected to the bit line BLm. For convenience of explanation, FIG. 1 shows only one selection transistor ST for selecting the bit line BL4, the virtual ground line VRG for the bit line BL2, the cascode circuit 2 for the bit line BL3, The precharge circuit 4 is omitted because it is connected to the bit line BL5. Details of this part will be described later.

  Next, the operation of the semiconductor memory device 1 will be described below by taking as an example the case of reading data (“0” or “1”) recorded in the memory cell M02. When reading data from the memory cell M02, first, a voltage (for example, 3 V) is applied to the word line WL0. As a result, the memory cell M02 is turned on. Next, the drain-source current is generated in the memory cell M02 by the virtual ground line VRG connected to the bit line BL2 on the source s1 side of the memory cell M02 and the cascode circuit 2 connected to the bit line BL3 on the drain d1 side. Ids (hereinafter, simply referred to as Ids) flows. Ids has a large threshold value when the memory cell M02 is in a writing state (hereinafter referred to as PGM state), and does not flow so much. Here, the bit lines BL1, BL4, BL6,... Are in a floating state.

  The bit line BL5 is charged by the precharge circuit 4 to prevent current from flowing out from the memory cell M02, and has the same potential as the bit line BL3 connected to the memory cell M02.

  Here, by sandwiching one bit line BL4 in a floating state between the bit line BL3 connected to the drain d1 of the memory cell M02 to be read and the bit line BL5 to be charged, the current between the drain and the precharge is reduced. It is possible to reduce the decrease in the read margin. However, in this case, the floating bit line BL4 between the bit line BL3 and the bit line BL5 is charged via the memory cell M04. There is a problem that the current between the flowing drain and the floating is increased, and the read margin is reduced.

  Therefore, the selection transistor ST connected to the bit line BL4 is turned on only for a predetermined time after the start of reading by an external precharge signal, and the bit line BL4 in the floating state is charged by the precharge circuit 4, The voltage of the line BL3 and the bit line BL4 are set to the same potential.

  On the other hand, in the sense amplifier 3, a reference signal obtained by converting a reference current Iref (hereinafter simply referred to as Iref) flowing in a reference circuit (not shown) into a voltage, and an input signal obtained by converting the current Ic flowing in the bit line BL3 into a voltage in the cascode circuit 2. If Ic <Iref, it is determined as “0” in the PGM state, and if Ic> Iref, it is determined as “1” in the ERASE state. For example, if an Ids of 10 μA in the PGM state and 20 μA in the ERASE state flows, it is possible to determine “0” or “1” with a margin of 5 μA by setting Iref to 15 μA.

  As described above, when reading, the floating bit line BL4 is provided between the drain d1 of the selected memory cell M02 and the bit line BL5 connected to the precharge circuit 4 and charged, and this is precharged. By charging the circuit 4 for a certain time after the start of reading, it is possible to prevent the current from flowing into or out of the memory cell M02, to prevent the reading margin from being reduced, regardless of the storage state of the adjacent memory cell. It can prevent being judged as incorrect data.

  In the above description, the bit line BL4 in the floating state is charged with the current source of the precharge circuit 4. However, the cascode circuit 2 and the selection transistor ST are connected to each other, and the current source of the cascode circuit 2 The bit line BL4 in the floating state may be charged for a certain time from the charge signal.

  Details of the embodiment of the present invention will be described below. FIG. 2 is a configuration diagram of the semiconductor memory device according to the embodiment of the present invention. FIG. 3 is a configuration diagram of a memory unit of the semiconductor memory device.

  Hereinafter, a description will be given with reference to FIGS. The semiconductor memory device 10 includes a voltage supply unit 11, an address input unit 12, a timing circuit 13 that generates a timing signal, a Y-direction decoder 14 and an X-direction decoder 15 that select an address input by the address input unit 12, A memory unit 16 for storing digital data, a cascode circuit 17 having a current source to be supplied to the memory unit 16, a precharge circuit 18 for charging a bit line BLn to be described later at the time of reading, and a memory unit 16 A reference circuit 19 for supplying a reference current for comparison with a flowing current, a sense amplifier 20 for comparing a current flowing in the memory unit 16 with a current flowing in the reference circuit 19, and an output circuit 21 for outputting a comparison result. .

  The memory unit 16 has a plurality of memory cells Mmn (m is a natural number of 0 or more and n is a natural number of 1 or more) arranged in a matrix as shown in FIG. 3, and is a word line connected to the gate of the memory cell Mmn. WLm (m corresponds to m of the memory cell Mmn) and a bit line BLn (n corresponds to n of the memory cell Mmn) crossing the word line WLm and connected to the source or drain of the memory cell Mmn. A memory cell array.

  Further, selection transistors Sna, Snb, Snc (n corresponds to n of the bit line BLn, which selects one of the virtual ground line VRG, the drain line DRL, and the precharge line PRL) are connected to the bit line BLn. Natural number). Furthermore, there are selection lines SLna, SLnb, and SLnc for operating the plurality of selection transistors Sna, Snb, and Snc. The selection lines SLna, SLnb, and SLnc are connected to the Y-direction decoder 14. The word line WLm is connected to the X direction decoder 15. Further, the drain line DRL is connected to the cascode circuit 17, and the precharge line PRL is connected to the precharge circuit 18. The voltage of the virtual ground line VRG is at the ground level (0 V).

  The memory cell Mmn stores bit information by including a MOS (Metal Oxide Semiconductor) type FET (Field-Effect Transistor) having a floating gate and a carrier trap layer such as a nitride film in the gate insulating film instead of the floating gate. This is a non-volatile MOS memory such as a MIS FET capable of storing multiple values in one cell, such as a MISFET.

  Hereinafter, the operation of the semiconductor memory device 10 will be described. First, a write operation to the memory cell Mmn will be described. Here, description will be given taking writing to the memory cell M02 as an example.

  When writing to the memory cell M02 according to the address input from the address input unit 12, the X direction decoder 15 applies a voltage to the word line WL0 and a plurality of memory cells M0n whose gates are connected to the word line WL0. Turns on.

  Further, the Y direction decoder 14 applies a voltage to the selection line SL2a, and the selection transistor S2a is turned on. As a result, the bit line BL2 connected to the memory cell M02 is connected to the virtual ground line VRG and becomes the ground level. Similarly, a voltage is applied to the selection line SL3b by the Y-direction decoder 14, and the selection transistor S3b is turned on. Thus, the bit line BL3 connected to the memory cell M02 is connected to the drain line DRL, and a voltage is applied by the cascode circuit 17. Further, the Y direction decoder 14 turns off the selection transistors S1a, S1b, S1c, S4a, S4b, S4c, S5a, S5b, S5c,..., And the bit lines BL1, BL4, BL5,. It becomes a state.

  At this time, the Y-direction decoder 14 may connect the drain line DRL to the bit line BL2 and the virtual ground line VRG to the bit line BL3. Here, when a floating gate type MOS FET is used as the memory cell Mmn, for example, when the drain voltage is 5 V and the gate voltage is 10 V, electrons are injected into the floating gate of the memory cell M02 by channel hot electron injection or the like. As a result, the threshold value Vth rises and the PGM state is entered.

  In erasing, for example, if the drain voltage is 5 V, the gate voltage is −10 V, and the source is in a floating state, electrons are discharged from the floating gate through the tunnel oxide film, and the threshold Vth is lowered to an ERASE state.

  Next, the operation at the time of reading from the memory cell Mmn will be described. The case of reading the memory cell M02 will be described. Similarly to the case of the above-described writing, a voltage is applied to the word line WL0 to turn on the memory cell M02, the virtual ground line VRG is connected to the bit line BL2, and the bit line A drain line DRL is connected to BL3. However, at this time, the voltage applied to the word line WL0 is 5 V, for example, and the voltage applied to the drain line DRL connected to the bit line BL3 is 1 V, for example.

  Furthermore, in the embodiment of the present invention, unlike the prior art, when reading from the memory cell M02, the bit line BL4 is not connected to the precharge line PRL, and the bit line BL4 is basically in a floating state. Instead, the bit line BL5 is charged. That is, a voltage is applied to the selection line SL5c, the selection transistor S5c is turned on, and the bit line BL5 connected to the memory cell M04 is connected to the precharge line PRL. Here, the bit line BL5 is charged by the current source of the precharge circuit 18, and the bit lines BL3 and BL5 are set to the same potential.

  Further, the bit line BL4 in a floating state is connected to the precharge line PRL only for a predetermined time. That is, a voltage is applied to the selection line SL4c by the Y-direction decoder 14, the selection transistor S4c is turned on, the bit line BL4 is connected to the precharge line PRL, and the bit line BL4 is charged by the current source of the precharge circuit 18. The same potential as BL3 and bit line BL5 is used.

  As a result, regardless of the storage state of the memory cell M02 and the adjacent memory cell M03, the current Ic flows from the bit line BL3 on the drain d1 side of the memory cell M02 to the bit line BL4 and from the bit line BL4 to the bit line BL3. Current inflow can be prevented.

  FIG. 4 is a time chart at the time of reading. As shown in the figure, first, internal address designation of which memory cell Mmn is read is performed, and the memory cell Mmn is selected by the Y direction decoder 14 and the X direction decoder 15. For example, reading is started when the memory cell M02 is selected.

  At this time, the selection transistor S2a is turned on by the selection line SL2a, and the bit line BL2 is connected to the virtual ground line VRG. The selection transistor S3b is turned on by the selection line SL3b, and the bit line BL3 is connected to the drain line DRL. Further, the selection transistor S5c is turned on by the selection line SL5c, and the bit line BL5 is connected to the precharge line PRL.

  In the first part of reading, for example, when the reading is 30 ns as shown in the figure, a precharge signal is sent to the selection line SL4c in the first 10 ns, and the bit line BL4 that has been in a floating state is connected to the precharge line PRL. Charge.

  Here, the current Ic flowing through the bit line BL3 is converted into a voltage by the cascode circuit 17, and compared with the reference signal input from the reference circuit 19 by the sense amplifier 20, the storage state ("0" or not) of the memory cell M02 is compared. “1”).

  At that time, as shown in FIG. 4, the sense amplifier 20 latches for 5 ns, for example, and outputs a determination result (“0” or “1”) to the output circuit 21. As described above, when reading, by charging the bit line BL4 in a floating state between the drain d1 and the charged bit line BL5 for a certain period of time, it is possible to prevent the current from flowing into and out of the memory cell M02. The sense amplifier 20 can read a correct value regardless of the storage state (PGM state or ERASE state) of the memory cell M02 and the adjacent memory cell M03.

  Note that the voltage and current values given above are merely examples, and the present invention is not limited thereto. In the above description, the floating bit line BL4 is charged by the current source of the precharge circuit 18. However, the present invention is not limited to this, and the bit line BL4 may be charged by the current source of the cascode circuit 17. Good. That is, a precharge signal may be input to SL4b for a certain period of time to turn on the select transistor S4b and connect the drain line DRL and the bit line BL4.

1 is a schematic configuration diagram of a semiconductor memory device of the present invention. It is a block diagram of a semiconductor memory device. 3 is a configuration diagram of a memory unit of a semiconductor memory device. FIG. It is a time chart at the time of reading. It is a schematic block diagram of a part of a conventional virtual ground nonvolatile semiconductor memory device. It is a general | schematic block diagram of a part of conventional semiconductor memory device, and shows the combination of a memory state with a memory cell. It is a general | schematic block diagram of a part of conventional semiconductor memory device, and shows the combination of a memory state with a memory cell.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2 Cascode circuit 3 Sense amplifier 4 Precharge circuit VRG Virtual ground line ST Selection transistors WL0, WL1,... Word lines BL1, BL2, BL3, BL4, BL5, BL6,. , M05,... Memory cells M11, M12, M13, M14, M15,.

Claims (8)

In a non-volatile semiconductor memory device that accesses a multilevel memory cell by a virtual ground method,
A plurality of the multi-value memory cells arranged in a matrix;
A plurality of bit lines connected to the source or drain of the multilevel memory cell in the column direction;
A plurality of word lines intersecting the bit lines and connected to the gates of the multilevel memory cells in a row direction;
A current supply circuit for supplying a current for reading data to the selected multi-value memory cell;
A precharge circuit for charging the bit line to a precharge voltage level, and for each bit line,
A first switch connecting the bit line and the current supply circuit;
A second switch for connecting the bit line and the precharge circuit;
When reading, according to the selected multi-level memory cell, for the bit line to which the drain is connected, the first switch is turned on during the reading period, and the bit line to which the drain is connected For the bit line on the opposite side of the first non-selected multi-level memory cell connected to the second non-selected multi-level memory cell adjacent to the first non-selected multi-level memory cell sharing For the bit line shared by the first unselected multi-level memory cell and the second unselected multi-level memory cell, the first switch is turned on during the read period, and the first switch is in the read period. A semiconductor memory device, wherein the semiconductor memory device is turned on at an initial stage and then turned off. 2. The semiconductor memory device according to claim 1, wherein the current supply circuit supplies a current to the selected multi-level memory cell while maintaining the drain at a predetermined potential. 3. The semiconductor memory device according to claim 2, wherein the current supply circuit is a cascode circuit. At the time of reading, the bit line shared by the first non-selected multi-level memory cell and the second non-selected multi-level memory cell is in a floating state after the non-conduction of the first switch. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. When reading, the selected multi-level memory cell, the first non-selected multi-level memory cell, and the second non-selected multi-level memory cell other than the bit line connected to the source or drain The semiconductor memory device according to claim 1, wherein the bit line is maintained in a floating state. 6. The semiconductor memory device according to claim 1, wherein the multi-value memory cell is a MOS FET including a carrier trap layer in a gate insulating film. A plurality of multi-value memory cells arranged in a matrix;
A plurality of bit lines connected to the source or drain of the multilevel memory cell in the column direction;
A plurality of word lines intersecting the bit lines and connected to the gates of the multilevel memory cells in a row direction;
A current supply circuit for supplying a current for reading data to the selected multi-value memory cell;
A precharge circuit for charging the bit line to a precharge voltage level;
A first switch that connects the bit line and the current supply circuit; a second switch that connects the bit line and the precharge circuit; and a third switch that connects the bit line and a virtual ground. A non-volatile semiconductor memory device current control method comprising a switching element to be provided for each bit line and configured by a virtual ground method
A first step of turning on the third switch connected to the bit line on the source side of the selected multi-level memory cell;
A second step of turning on the first switch connected to the bit line on the drain side of the selected multi-level memory cell;
A third step in which a first switch connected to a bit line shared by the first non-selected multi-level memory and the second non-selected multi-level memory is turned on;
A fourth step of turning on a second switch connected to a bit line on the opposite side of the first unselected multi-level memory cell connected to the second unselected multi-level memory cell;
When reading
The potential of the bit line shared by the first non-selected multi-level memory and the second non-selected multi-level memory is the read potential of the bit line connected on the drain side of the selected multi-level memory cell. After the same potential,
A non-volatile semiconductor comprising: a fifth step of turning off the first switch connected to a bit line shared by the first unselected multi-level memory and the second unselected multi-level memory A current control method for a storage device. The current control method for a nonvolatile semiconductor memory device according to claim 7,
By having a sense amplifier connected in series with the current supply circuit and determining the storage state of the multi-level memory cell,
Further, the first switch connected to the bit line on the drain side of the selected multi-level memory cell is turned on, and the first switch connected to the second unselected multi-level memory cell is connected. With the second switch connected to the bit line opposite to the non-selected multi-value memory cell of 1 being turned on,
A current control method for a nonvolatile semiconductor memory device, comprising: a sixth step in which data information stored in the selected multi-level memory is read by the sense amplifier.

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