JP2001084788A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory in which a write state having a limited threshold distribution can be attained. SOLUTION: The nonvolatile semiconductor memory comprises a memory cell array 1 where electrically rewritable nonvolatile memory cells are arranged, a row decoder 6 and a column decoder 8 for selecting a memory cell in the memory cell array 1 according to an address, a sense amplifier/latch circuit 3 for sensing the read data of the memory cell array 1 and latching the write data, a circuit 9 for controlling write and erase of a selected memory cell in the memory cell array 1, and a drive power supply circuit 10 being controlled by the control circuit 9 to generate a write voltage set optimally depending on the writability of each block of the memory cell array 1 at the time of writing. The optimal write voltage for each block can be stored in a part of the memory cell array 1, i.e., a write voltage storage area 1a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM).

[0002]

2. Description of the Related Art An EEPROM is usually constructed using a memory cell having a MOS transistor structure in which a floating gate and a control gate are stacked. Among the EEPROMs, a NAND type EEPROM composed of a plurality of memory cells connected in series to constitute a NAND unit is particularly suitable for high integration.
OM is known. Writing and erasing of data in the EEPROM is performed by injecting electrons from the channel to the floating gate through the tunnel insulating film or discharging electrons from the floating gate to the channel side. A state in which the threshold voltage is increased by electron injection into the floating gate is a write state (eg, “0” state), and a state in which the threshold voltage is reduced by electron emission is an erase state (eg,
("1" state).

[0003] As one of the writing methods of the NAND type EEPROM, there are a verify writing method and a step-up voltage method. The verify write method is a method in which a write voltage is repeatedly set to a pulse voltage, and a verify read for checking a write state is performed each time a pulse voltage is applied, and the write operation is repeated to drive the threshold value of the write memory cell to a desired range. It is. The step-up voltage method is a method in which a pulse voltage at the time of performing a verify write is set to a low start voltage and sequentially stepped up.

FIGS. 8A and 8B show an example of a write pulse having a constant voltage value and an example of a write pulse of a step-up system, respectively. In the memory cell array,
There are memory cells that are easy to write and memory cells that are difficult to write. When a write pulse having a fixed voltage value as shown in FIG. 8A is used, some memory cells are overwritten by a start pulse. For this reason, even if write verification is performed, the threshold distribution of the memory cell after writing becomes large as shown in FIG. On the other hand, when the step-up voltage method is used, overwriting hardly occurs, so that the threshold distribution becomes small as shown in FIG. 9B.

[0005]

However, a problem still remains when the step-up verify write is performed. The start voltage in the step-up method is set so that a memory cell which is difficult to write in the memory cell array is written within a desired time. Then,
Since the start voltage is too high in the easily written memory cells in the block to be written at the same time, the effect of the step-up method of writing from a low voltage cannot be expected, and overwriting occurs at the start voltage. Therefore, as shown in FIG. 9B, overwritten memory cells occur. In this case, the spread of the threshold voltage distribution is small as compared with the fixed voltage method. Therefore, there is a possibility that no problem occurs when performing binary storage. But for example
As shown in FIG. 10, when multi-value storage is performed with a narrow threshold distribution, a slight spread of the threshold distribution causes erroneous writing, which is a problem.

The present invention has been made in consideration of the above circumstances, and has as its object to provide a nonvolatile semiconductor memory device capable of obtaining a write state with a narrow threshold distribution.

[0007]

A nonvolatile semiconductor memory device according to the present invention comprises a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, and a decode circuit for selecting a memory cell in the memory cell array by an address. A sense amplifier / latch circuit for sensing read data of the memory cell array and latching write data, a control circuit for controlling writing and erasing of a selected memory cell of the memory cell array, and control by the control circuit And a drive power supply circuit for generating a write voltage optimally set according to the ease of writing for each block of the memory cell array at the time of writing.

In the EEPROM according to the present invention, by using a write voltage optimally set according to the ease of writing for each block of the memory cell array, it is possible to obtain a write state with less overwriting and therefore a narrow threshold distribution. it can. Specifically, when the step-up voltage method is used as the writing method, the start voltage may be optimally set according to the block. According to the invention,
For example, even when performing multi-value storage such as four-value storage using 2-bit / memory cells, writing without erroneous writing becomes possible.

In the present invention, for example, the drive power supply circuit is configured to generate an optimum write voltage for each block by setting one word line range of the memory cell array as one block, or to determine the arrangement pattern of the memory cell array. It is assumed that an area where the regularity is maintained and an area where the regularity is broken are used as separate blocks, and an optimum write voltage is generated for each block.

Further, in the present invention, in order to maintain a write voltage optimally set for each block in the EEPROM chip, for example, a partial area of the memory cell array is divided into blocks for each block based on a wafer test result. It is used as a write voltage storage area for writing and storing a write voltage. Alternatively, a fuse circuit for writing and storing a write voltage for each block based on a wafer test result may be provided.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit configuration of an EEPROM according to a first embodiment of the present invention. In the memory cell array 1, as shown in FIG. 2, a plurality of memory cells MC are connected in series to form a NAND cell unit.
One end of the NAND cell unit is connected to the bit line BL via the select gate transistor SG1, and the other end is also connected to the common source line S via the select gate transistor SG2.
Connected to S. The control gates of the memory cells MC arranged in the row direction are commonly connected to a word line WL, and the gates of the select gate transistors SG1 and SG2 are also commonly connected to control gate lines SGD and SGS.

A bit line BL of the memory cell array 1 is connected to a sense amplifier / latch circuit 3 via a column gate 2 selectively driven by a column decoder 8. The sense amplifier / latch circuit 3 senses read data and latches write data. The sense amplifier / latch circuit 3 is connected to an input / output terminal via an input / output buffer 4. The word line WL of the memory cell array 1 is selectively driven by the row decoder 6. The row address and the column address are taken into the row address buffer 5 and the column address buffer 7, respectively, and supplied to the row decoder 6 and the column decoder 8, respectively. A drive power supply circuit 10 having a built-in booster circuit is provided to supply a necessary voltage to a word line selected by the row decoder 6 in accordance with writing, erasing, reading, and the like. The control circuit 9 controls the drive power supply circuit 10 based on the control signal to perform write and erase sequence control.

FIG. 3 shows a layout of the memory cell array 1, and FIGS. 4 and 5 show AA 'and B-
It shows a B ′ sectional view. The memory cell array 1 is formed in a p-type well 22 formed in an n-type well 21 of a p-type silicon substrate 20. An element isolation insulating film 23 is formed on the substrate by the STI technique or the like to define an element formation region. A tunnel insulating film 24 is formed on such a substrate.
, A control gate 27 is formed on the floating gate 25 via an insulating film 26, and a source / drain diffusion layer 28 is further formed to constitute a memory cell.

The floating gate 25 is separated in the row direction by slit processing on the element isolation insulating film 23, and is patterned at the same time as the control gate 27 in the column direction. The control gate 27 is continuously patterned in the row direction, and this becomes the word line WL. In the select gate transistor, a gate insulating film 24a thicker than the memory cell is formed. Then, two layers of gates 25a and 27a formed simultaneously with the floating gate 25 and the control gate 27 are short-circuited at appropriate positions and continuously arranged in the row direction, and become select gate lines SGD and SGS. The substrate on which the memory cell array 1 is formed is covered with an interlayer insulating film 29, on which bit lines 30 are provided.

In this embodiment, data writing is performed by applying a boosted write voltage Vpgm to the selected word line from the power supply circuit 10 and injecting electrons from the channel region into the floating gate in the selected memory cell. Will be In the case of this embodiment, the write voltage Vpgm is changed for each appropriate block of the memory cell array.
Different values are used depending on the ease of writing the memory cells therein.

More specifically, in this embodiment, the range of one word line of the memory cell array 1 is taken as one block, and an optimum write voltage Vpgm is used for each word line. Here, the optimum write voltage Vpgm is set so that the slowest cell among the memory cells simultaneously selected by one word line can complete the write within a desired time. In order to use the optimum write voltage Vpgm for each word line, in this embodiment, as shown in FIGS. 1 and 2, a part of the memory cell array 1 is set as the write voltage storage area 1a. In the example of FIG. 2, the range of two memory cells among the memory cells along each word line WL is set as the write voltage storage area 1a.
Therefore, four write voltages Vpgm represented by 2-bit data can be stored for each word line.

In the write voltage storage area 1a, optimum write voltage data is written based on the result of the die sort test at the wafer stage. And the completed EE
In writing data in the PROM, first, the write voltage data in the write voltage storage area 1a is read out in the same manner as a normal read operation. Then, the read data is determined by, for example, the control circuit 9, and based on the determination result, the drive power supply circuit 10 generates a required write voltage Vpgm for each word line. In the case of the step-up voltage type verify write, the start voltage is stored in the write voltage storage area 1a. In this case, the start voltage may be set so that the slowest cell among the memory cells simultaneously selected by one word line will complete the writing within a desired time.

According to this embodiment, since the optimum write start voltage is used for each word line, the number of overwritten memory cells is reduced, and the threshold distribution of the written memory cells is narrow. This is particularly effective when performing multi-value storage using a threshold voltage. In the above embodiment, the data read from the write voltage storage area 1a of the memory cell array 1 is performed using the sense amplifier / latch circuit 3 in the same manner as the normal read. A readout circuit may be provided separately from the readout circuit. In this case, the write voltage storage area 1
The data reading a may be automatically performed when the power is turned on, latched in the reading circuit, and the write voltage control may be performed based on the latched data.

[Embodiment 2] NAND type EEPROM
In FIG. 3, as shown in FIG. 3, select gate lines SGD and SGS are provided with a plurality of word lines WL (control gate lines) interposed therebetween. Due to the miniaturization of the memory cells, the width of the word line WL (gate length of the memory cell) is short,
The width of the select gate lines SGD and SGS cannot be reduced so much because the cutoff characteristics of the select gate transistors need to be secured. Therefore, a regular region of the pattern and a region where the regularity is broken occur in the memory cell array 1. In the word lines adjacent to the select gate lines SGD and SGS and other word lines, the former may have a narrower word line width due to process fluctuations.
When the word line width is reduced, the writing characteristics deteriorate due to the bird's beak effect and the short channel effect.

Therefore, in the second embodiment, a region where the regularity of the arrangement pattern of the memory cell array is maintained (in the above example, a range of the word line in which both sides are word lines).
And an area where the regularity is broken (in the above example, the word lines having the select gate lines SGD and SGS next to each other) are set as separate blocks, and an optimum write voltage is generated for each block. In this case, a part of the memory cell array 1 can be used for storing the write voltage as in the first embodiment, but another method is used in the second embodiment.

FIG. 6 shows a circuit configuration of the EEPROM according to the second embodiment. 1 are given the same reference numerals as in FIG. 1 and detailed description is omitted. In this embodiment,
According to the above-described block division, in order to generate different write voltages for each block having different write characteristics,
Separate drive power supply circuits 10a and 10b are provided.
Each power supply circuit 10a, 10b has a fuse circuit 61a, 6
1b is provided. The fuse circuits 61a, 61
In b, the optimum write voltage data for each block is written based on the result of the wafer test as in the previous embodiment. In the case of the verify write method using the step-up voltage, the data written in the fuse circuits 61a and 61b is a start voltage.

According to the second embodiment, a write state with a narrow threshold distribution can be obtained by using a write voltage optimally set according to the write characteristics of the memory cell. Of course, the write voltage storage method of the second embodiment can be similarly applied to the case where the range of one word line is one block as in the first embodiment.

[Embodiment 3] NAND type EEPROM
Then, in data writing, NAN of write prohibition
There is a method in which the channel of the D unit is floated so that a high electric field is not applied to unselected memory cells. For example, as shown in FIG. 7, two memory cells A,
The write operation will be described focusing on B, as follows. Writing (data “0”) is performed on the memory cell A, and writing is not performed on the memory cell B (that is,
"1" data retention). At this time, Vss = 0 V is applied to the bit line for writing “0” data, and Vcc is applied to the write-inhibited bit line, and these are transferred to the channel of each NAND cell unit. The select gate line SGD is set at Vcc. Thereby, the memory cell B
The side channel is charged to a potential slightly lower than Vcc, disconnected from the bit line by the selection gate, and floats.

In this state, a write voltage Vpgm is applied to the selected word line WL0, and a write inhibit voltage Vpass, which is an intermediate voltage higher than Vcc and lower than the write voltage Vpgm, is applied to the other unselected word lines. As a result, in the selected memory cell A, a large electric field is applied between the floating gate and the channel, an FN tunnel current flows, and electrons are injected into the floating gate. This is “0” writing. In this case, in the memory cell B, in the floating channel region, the channel potential increases due to the capacitive coupling between the control gate, the floating gate, and the channel, and no electron injection occurs in the floating gate.

In the third embodiment, the write voltage Vpgm is set for each block according to the write characteristics as in the first and second embodiments, and at the same time, the write inhibit voltage Vpass applied to the non-selected word lines is also changed. The voltage value is optimally set for each block. More specifically, the write inhibit voltage Vpass may be set high when the memory cells of the block for which write is inhibited are easy to write, and may be set low when the write is difficult. The optimum write inhibit voltage can be stored in the same manner as the write voltage data storage method in the first and second embodiments.

According to this embodiment, at the time of writing, the threshold value fluctuation of the write-protected memory cell is suppressed, so that it is possible to further suppress the spread of the threshold value distribution of the write memory cell.

[0027]

As described above, according to the present invention, E
By using the optimum write voltage for each block according to the write characteristics of the memory cell when writing in the EPROM, the variation in the threshold voltage of the memory cell after write is effectively suppressed, and the erroneous write is prevented. Becomes possible. In particular, when the regularity of the pattern is lost due to the EEPROM configuration and a difference in write characteristics occurs, the regular pattern region and the irregular pattern region are divided into blocks in the memory cell array, and the write voltage is optimally set for each block. By doing so, variations in the threshold voltage can be suppressed. Furthermore, by setting not only the write voltage but also the write inhibit voltage for the non-selected memory cells optimally for each block, the spread of the threshold voltage is further suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an EEPROM according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit of the memory cell array of the embodiment.

FIG. 3 is a layout of the memory cell array of the embodiment.

FIG. 4 is a sectional view taken along line A-A 'of FIG.

FIG. 5 is a sectional view taken along line B-B 'of FIG.

FIG. 6 is a diagram showing a circuit configuration of an EEPROM according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating an EEPROM according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a write voltage waveform of an EEPROM of a verify write system.

FIG. 9 is a diagram showing a threshold voltage distribution of a write memory cell;

FIG. 10 is a diagram showing a threshold voltage distribution of a four-valued EEPROM.

[Explanation of symbols]

1 ... memory cell array, 1a ... write voltage storage area,
2 ... column gate, 3 ... sense amplifier / latch circuit, 4
... I / O buffer, 5 ... Row address buffer, 6 ... Row decoder, 7 ... Column address buffer, 8 ... Column decoder, 9 ... Control circuit, 10, 10a, 10b ... Drive power supply circuit, 61a, 61b ... Fuse circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/115 G11C 17/00 611E 27/10 481 622E 491 633D H01L 27/10 434 F Term (Reference) 2G032 AA08 AD01 AE14 AH04 5B003 AA05 AB06 AC07 AD03 AD05 AD09 AE04 5B025 AA03 AB01 AC01 AD02 AD03 AD04 AD06 AD08 AD09 AD16 AE08 AE09 5F083 EP02 EP23 EP33 EP34 EP76 GA15 LA03 LA04 LA05 LA06 LA10 ZA20 ZA21

Claims (7)

[Claims] A memory cell array in which electrically rewritable nonvolatile memory cells are arranged; a decoding circuit for selecting a memory cell in the memory cell array by an address; sensing read data from the memory cell array; A sense amplifier / latch circuit for latching; a control circuit for controlling writing and erasing of a selected memory cell of the memory cell array; controlled by the control circuit to facilitate writing of each block of the memory cell array during writing A drive power supply circuit that generates a write voltage optimally set according to
A nonvolatile semiconductor memory device comprising: 2. The non-volatile semiconductor device according to claim 1, wherein the drive power supply circuit generates an optimum write voltage for each block by setting a range of one word line of the memory cell array as one block. Storage device. 3. The drive power supply circuit generates an optimum write voltage for each block, using a region where the regularity of the arrangement pattern of the memory cell array is maintained and a region where the regularity is broken as another block. 2. The nonvolatile semiconductor memory device according to claim 1, wherein: 4. A partial area of the memory cell array,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is used as a write voltage storage area for writing and storing a write voltage for each block based on a result of a wafer test. 5. The nonvolatile semiconductor memory device according to claim 1, further comprising a fuse circuit for writing and storing a write voltage for each block based on a result of the wafer test. 6. The drive power supply circuit outputs a pulse voltage whose voltage value increases stepwise under the control of the control circuit as the write voltage, and the start pulse voltage has a different value depending on the block. The nonvolatile semiconductor memory device according to claim 1, wherein: 7. The drive power supply circuit generates a write inhibit voltage applied to an unselected memory cell together with a write voltage to a selected memory cell, and the write inhibit voltage is set to an optimum value according to a block. The nonvolatile semiconductor memory device according to claim 1, wherein: