JP2010135003A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a memory cell to be easily multi-valued by narrowing a distribution width of threshold after the write-in of data in a nonvolatile semiconductor memory. <P>SOLUTION: After a first write-in operation, a second write-in operation is carried out by changing a threshold verifying voltage. At this time, since a relation of Verify(b)=Verify(a)-w/2 is in existence between a first threshold verifying voltage Verify(b) and a second threshold verifying voltage Verify(a), where the distribution width of the threshold after the first write-in operation is defined as w, the distribution width of the threshold after the second write-in operation becomes w/2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device provided with a writing method for increasing the accuracy of threshold control.

  Multi-level technology for nonvolatile semiconductor memory devices is a technology for storing data for two addresses or more in a single memory cell, and it is possible to increase the data capacity more than double with the same integration degree, so it is attracting attention. ing. However, although the threshold distribution width of the memory cell transistor is required to be narrowed in order to increase the number of values, the variation in manufacturing of individual memory cell transistors increases with the miniaturization of the memory cell. is doing. As a result, the variation of the threshold value of the memory cell transistor is also large, which hinders multi-leveling.

  For this problem, in order to narrow the threshold distribution width, a temporary verification voltage is set between the target verification voltage and the threshold value at the time of erasing, and then writing is performed. There has been proposed a nonvolatile semiconductor memory device including a writing method in which only a memory cell that does not reach a target verification voltage is rewritten (see, for example, Patent Document 1).

  In this method, first, when writing into a nonvolatile semiconductor memory device, in order to reach a desired threshold (Vth) level, the threshold is verified for each memory cell transistor after performing a write operation. Operation (hereinafter referred to as verification operation or verification read-out) is performed. The verification operation is performed for each memory cell transistor, and a memory cell transistor whose threshold value has reached the verification voltage (Vt1) is discriminated from a memory cell transistor that has not yet reached the verification voltage. In the write operation, the write voltage and the pulse width (application time) for applying the write voltage are changeable parameters. For the memory cell transistor whose threshold value has not reached the verification voltage, the write operation and the verification operation are repeated, and the threshold value of each memory cell transistor reaches the first verification voltage Vt1. The write (1), which is accompanied by the verify operation so far (1), is intended to cause the threshold value of each memory cell transistor to exceed the verify voltage Vt1. The threshold shows a wide distribution.

  Next, the verification voltage is changed to the second verification voltage Vt10, the writing voltage and the pulse width are also changed, and writing (2) is performed on the memory cell transistor whose threshold value has not reached Vt10. Similar to the write (1), the write (2) is completed when the threshold value of each memory cell transistor reaches the second verification voltage Vt10. Since the first verification voltage Vt1 is between the threshold value of each memory cell transistor before writing (at the time of erasing) and the second verification voltage Vt10, the threshold distribution width after the completion of writing (2) is Compared with the conventional writing method of writing (1) only, the absolute value of Vt1-Vt10 becomes narrower.

However, in Patent Document 1, since the relationship between the first verification voltage and the second verification voltage is not clear, there is a problem that it is difficult to obtain the effect of narrowing the threshold distribution width.
Japanese Patent Laid-Open No. 9-320285 (page 7, FIG. 2)

  In view of the above-described problems, an object of the present invention is to narrow a threshold distribution width after data writing in a nonvolatile semiconductor device.

  To achieve the above object, a nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of memory cell transistors arranged on a semiconductor substrate, and a writing unit that writes data to the plurality of memory cell transistors by a writing operation. And threshold verification means for verifying a magnitude relationship between threshold values of a plurality of memory cell transistors into which data has been written by the writing means and a constant threshold verification voltage, After setting the voltage to the first verification voltage and performing a first write operation on a desired memory cell transistor, the threshold verification voltage is set to be higher than the first verification voltage after the first write operation is completed. A memory cell transistor is set to a second verification voltage that is one-half larger than the threshold distribution width of the memory cell transistor, and has a smaller threshold value than the second verification voltage It is characterized by performing a second write operation to Le transistor.

  The distribution width of the threshold value at the end of the second writing can be made half of the distribution width after the first writing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  In the following, the case where the threshold value of the memory cell transistor after writing is higher than the threshold value at the time of erasing will be described.

  FIG. 1 shows a block configuration of a nonvolatile semiconductor memory device (for example, a NAND flash memory) according to an embodiment of the present invention. The NAND flash memory according to this embodiment includes a memory cell array 101, a sense amplifier / data latch 102, a column decoder 103, a row decoder 104, an address buffer 105, a data input / output buffer 106, a substrate potential control circuit 107, and a Vpgm generation circuit 108. , A Vpass generation circuit 109, a Vread generation circuit 110, and a control signal generation circuit 111.

  As will be described later, the memory cell array 101 is configured by arranging NAND strings in which nonvolatile memory cells are connected in series.

  The sense amplifier / data latch (bit line control circuit) 102 is provided to sense bit line data of the memory cell array 101 or hold write data. This circuit performs bit line potential control when performing verification reading after data writing and rewriting to an insufficiently written memory cell, and is composed mainly of, for example, a CMOS flip-flop.

  The sense amplifier / data latch 102 is connected to the data input / output buffer 106. The connection between the sense amplifier / data latch 102 and the data input / output buffer 106 is controlled by the output of the column decoder 103 that receives the address signal from the address buffer 105.

  The row decoder 104 is provided to select a memory cell with respect to the memory cell array 101, specifically, to control a control gate and a selection gate.

  A write voltage (Vpgm) generation circuit 108 is provided to generate a write voltage Vpgm boosted from the power supply voltage when data is written to a selected memory cell of the memory cell array 101. In addition to the Vpgm generation circuit 108, a write intermediate voltage (Vpass) generation circuit 109 for generating a write intermediate voltage Vpass to be applied to a non-selected memory cell at the time of data write, and a data read (at the time of verification read) A read intermediate voltage (Vread) generation circuit 110 for generating a read intermediate voltage Vread to be applied to a non-selected memory cell.

  The write intermediate voltage Vpass and the read intermediate voltage Vread are lower than the write voltage Vpgm but are boosted from the power supply voltage Vcc. The control circuit 111 is used to variably set a write operation, an erase operation, a read operation, a write verify operation, an overwrite verify operation, a data erase operation for a data latch unit, an initial voltage for a write operation, and a voltage pulse for a step-up. Controls rewrite operation and the like.

  FIG. 2 is an equivalent circuit of the memory cell array 101. A NAND string is configured in which a plurality of memory cell transistors MT are connected in series, and select transistors S are connected to both ends thereof. One end of the current path is connected to the bit line BL, and the other end is connected to the common source line.

  FIG. 3 is a plan view of a NAND string constituting the memory cell array 101. FIG.

  As shown in FIG. 3, a plurality of element regions AA <b> 0 to AA <b> 2 are provided on the main surface of the semiconductor substrate 31. These element regions AA0 to AA2 are each formed in a strip shape along a predetermined direction, that is, the vertical direction in FIG.

  These element regions AA0 to AA2 are insulated and isolated by an element isolation region 32. In the element regions AA0 to AA2, a plurality of diffusion regions 34 serving as the source / drain of the memory cell transistor MT are formed apart from each other by the word line WL of the memory cell transistor MT. A plurality of memory cell transistors MT are connected in series by sharing adjacent diffusion regions 34 to form a NAND string.

  On the element regions AA0 to AA2 and the element isolation region 32, the word lines WL of the plurality of memory cell transistors MT are arranged along the direction orthogonal to the predetermined direction, that is, the horizontal direction of FIG. 3, and the selection gate transistor S1 Selection gate lines SGS / SGD of / S2 are arranged in parallel with the word lines WL.

  Channels of the memory cell transistors MT are formed below the word lines WL intersecting with the element regions AA0 to AA2, respectively, and below the selection gate lines SGS / SGD intersecting with the element regions AA0 to AA2. Channels of the selection transistors S1 / S2 are formed respectively. The diffusion regions S or D of the selection transistors S1 / S2 are connected to the source line contact and the bit line contact, respectively.

  4 is a cross-sectional view taken along line AA ′ in FIG.

  As shown in FIG. 4, each memory cell includes a tunnel insulating film Tox provided on a (P well (not shown)) formed in a semiconductor substrate 31, and a floating gate provided on the tunnel insulating film Tox. FG, intergate insulating film IPD provided on floating gate FG, control gate CG (41) provided on intergate insulating film IPD, and silicide layer 41S provided on control gate CG (41) It is a laminated structure. Each memory cell constitutes a memory cell transistor MT whose threshold value changes by accumulating charges in the floating gate FG. Each floating gate FG is electrically isolated for each memory cell transistor MT. The control gate CG is connected to the word lines WL0 to WL31, and is electrically connected in common in the memory cell transistors in the word line direction.

  Each memory cell transistor MT includes a spacer 24 provided along the side wall of the stacked structure, and a source S or drain D provided in a P well so as to sandwich the stacked structure.

  The selection transistors S1 and S2 include a gate insulating film Gox, an inter-gate insulating film IPD, a gate electrode G, and a silicide layer 42S. The inter-gate insulating film IPD is provided so that the gate electrode G is separated and its upper and lower layers are electrically connected. The silicide layer 42S is provided on the gate electrode G.

  The selection transistors S1 and S2 include a spacer 24 provided along the side wall of the gate electrode G, and a source S or drain D provided in the P well so as to sandwich the gate electrode G.

  Since the selection transistors S1 and S2 select a NAND string along the direction of the bit line BL and connect it to the bit line BL, the gate electrodes G of the selection transistors S1 and S2 are connected to the selection gate lines SGS and SGD, respectively. .

  The source S of the selection transistor S1 is connected to the source line SL through source line contacts SC-1 and SC-2 in the interlayer insulating film 17-1.

  A bit line BL2 is provided in the interlayer insulating films 37-1 and 37-2. The bit line BL2 is electrically connected to the drain D of the selection transistor S2 via the bit line contacts BC1 to BC3 in the interlayer insulating film 37-1.

  FIG. 5 is a cross-sectional view taken along line BB ′ in FIG.

  As shown in FIG. 5, in the element region defined by the element isolation insulating film 33, memory cell transistors MT0 to MT2 are arranged at the intersections between the word line WL2 and the bit lines BL0 to BL2.

  In the NAND string, at least one or more selection gate lines SGS and SGD are sufficient. The number of memory cell transistors MT in the NAND string is not limited to this embodiment. For example, the number of memory cells in the NAND string may be plural, and it is 2n (n is a positive integer) or a number obtained by adding about 1 to 4 dummy cells to them. Is desirable.

  FIG. 6 shows basic operating conditions for writing and reading data in the NAND flash memory.

  In data writing, 0 V (in the case of “0” writing) or Vcc (in the case of “1” writing) is applied to the bit line BL according to the data. The selection gate on the bit line side is Vcc, and the selection gate on the source line side is 0V. Subsequently, a write voltage Vpgm of about 20 to 25 V is applied in a pulse form to the control gate of the selected memory cell (the cell surrounded by a circle in FIG. 5), and the intermediate voltage Vpass is applied to the control gate of the non-selected memory cell. Apply. As a result, when the data is “0”, the selection gate transistor on the bit line side is turned on, and the potential (0 V) of the bit line is transferred to the channel of the NAND string. In this case, while the channel potential is 0 V, the floating gate of the selected memory cell has a higher potential due to capacitive coupling with the control gate. Accordingly, a high electric field is generated between the channel (semiconductor substrate) and the floating gate, electrons are injected from the channel (semiconductor substrate) into the floating gate by a tunnel current, and the threshold voltage of the memory cell transistor moves in the positive direction. When the data is “1”, the selection gate transistor on the bit line side is OFF, and the channel of the NAND string is in a floating state. In that case, the floating channel has an intermediate potential due to capacitive coupling with the control gate, and no high electric field is generated between the floating gate of the selected memory cell and the channel (semiconductor substrate). Therefore, electrons are not injected into the floating gate, and the threshold voltage of the memory cell transistor does not change.

  After the data write operation by applying the write pulse voltage, a write verify operation is performed in order to check whether the threshold value of the memory cell transistor has reached a desired voltage (verification voltage). In the write verification operation, a verification voltage is applied to the control gate of the memory cell in which data is written to determine whether the memory cell transistor is ON (current flows) or OFF (current does not flow). Done. If the memory cell transistor is OFF, the threshold value of the memory cell transistor is lower than the verification voltage, so that writing is insufficient, and writing is repeated by applying the write voltage Vpgm to the memory cell as a pulse voltage. .

  FIG. 7 is a conceptual diagram of the threshold distribution of the memory cell transistor by the writing method according to the embodiment of the present invention.

  The threshold distribution before writing (at the time of erasing) is 201. A threshold distribution is 202 after the first verification write is performed with the first verification voltage as Verify (b). Assume that the distribution width of 202 is w, and Verify (a) such that Verify (a) = Verify (b) + w / 2 is set as the second verification voltage. The threshold distribution after the second verification write is performed with the verification voltage being Verify (a) for the memory cell whose threshold value is less than Verify (a) is 203. In the second verification writing, writing is not performed on a memory cell having a threshold value exceeding Verify (a), and writing is performed only on about half of the memory cells whose threshold value is less than Verify (a). The memory cells that have received the second verification write are distributed in the range of w / 2 width upward from Verify (a) after the completion of the second verification write. After all, after the completion of the second writing, the threshold values of all the memory cell transistors are distributed in the range of w / 2 width in the plus direction from Verify (a) together with the memory cells not subjected to the second writing. .

  FIG. 8 is a flowchart showing the writing method according to the embodiment of the present invention.

  First, let w be the distribution width of the threshold when writing with verification by the conventional method. Finally, the target write verification voltage Verify (a) is set as the second verification voltage, and a voltage w / 2 lower than Verify (a) is set as the first verification voltage Verify (b).

  A first write operation using the first verification voltage Verify (b) is performed on each memory cell (S01). Next, a verification operation is performed to determine whether the threshold value of the memory cell transistor to be written exceeds Verify (b) (S02). The first write operation is continued until the threshold values of all memory cell transistors to be written exceed Verify (b) (S01, S02). When it is determined that the threshold values of all the memory cell transistors to be written have exceeded Verify (b), the first write operation with the verification voltage as Verify (b) ends (S03). The threshold distribution of the memory cell transistors is mainly caused by manufacturing variation of each memory cell, and is almost the same regardless of the value of the verification voltage, and the distribution width after the first writing is w. .

  Next, the threshold value of each memory cell is determined using the write verification voltage as the second verification voltage Verify (a) (S04). Specifically, the second verification voltage Verify (a) is applied to the control gate of each memory cell, and it is determined whether the memory cell transistor is ON (current flows) or OFF (current does not flow). The If the memory cell is ON, the threshold value of the memory cell is smaller than Verify (a), so that the second write operation is performed. If it is OFF, the memory cell has a threshold value higher than Verify (a) and is not a target of the second write operation.

  For the memory cell whose threshold value is less than Verify (a), the second write operation is performed until the threshold value reaches Verify (a) (S05, S06). In the second write operation, the write voltage and the write pulse width may be the same as the first write operation in Verify (b) or may be changed.

  When it is determined that the threshold values of all the memory cell transistors to be written have exceeded Verify (a), the write operation ends (S07).

  Note that the threshold distribution width w by the first verification writing method can be obtained at the stage of product testing. If the obtained w is recorded in the ROM of the product chip as a parameter, it can be referred to at the time of writing.

  Further, since it is considered that the threshold distribution of the memory cell transistor at the time of the first verification write is a normal distribution, the threshold value of the first write using the first verification voltage Verify (b) is used. The value of Verify (b) may be determined so that the median value of the distribution becomes the second verification voltage Verify (a).

  As described above, according to the embodiment of the present invention, by performing the second write operation by changing the verification voltage after the first write operation, the conventional write operation is performed with respect to the threshold distribution of the memory cell transistor. One-half distribution width of the method is obtained. Further, in this writing method, since the second writing is performed on about one-half of all the memory cell transistors, it is possible to narrow the threshold distribution width while suppressing a decrease in writing speed.

1 is a block configuration of a NAND flash memory according to an embodiment of the present invention. 3 is an equivalent circuit of a memory cell of the NAND flash memory according to the embodiment of the present invention. 1 is a plan view of a NAND string of a NAND flash memory according to an embodiment of the present invention. FIG. 4 is a cross-sectional view of the NAND string of the NAND flash memory according to the embodiment of the present invention, cut along the line AA ′ of FIG. 3 and viewed in the direction of the arrow. FIG. 4 is a cross-sectional view of the NAND string of the NAND flash memory according to the embodiment of the present invention, cut along BB ′ in FIG. 3 and viewed in the direction of the arrow. 5 shows reading and writing conditions of the NAND flash memory according to the embodiment of the present invention. It is a conceptual diagram of the threshold distribution after writing of the NAND flash memory according to the embodiment of the present invention. 4 is a flowchart of a writing method of the NAND flash memory according to the embodiment of the present invention.

Explanation of symbols

24 Spacer 31 Semiconductor substrate 32 Element isolation region 33 Element isolation insulating film 34 Diffusion region (source or drain)
37 Interlayer insulating film 41 (CG) Control gate 42 Upper gate electrodes 41S, 42S Silicide layers BL0, BL1, BL2 Bit lines WL0-WL31 Word lines SGS, SGD Select gate lines MT Memory cell transistors S1, S2 Select transistors Tox Memory cell transistors Tunnel insulating film Gox selection transistor gate insulating film FG floating gate IPD inter-gate insulating film BC bit line contact SC source line contact S source D drain G selection transistor gate electrode 101 memory cell array 102 bit line control circuit 103 column decoder 104 row Decoder 105 Address buffer 106 Data input / output buffer 107 Substrate potential control circuit 108 Vpgm generation circuit 109 Vpass generation circuit 110 Vread generation circuit 111 Control signal generation circuit 201 Threshold distribution 202 before writing (in erasing) Threshold distribution 203 after writing operation to Verify (b) After writing operation to Verify (b), writing operation to Verify (a) Threshold distribution width after writing operation to threshold distribution w Verify (b)

Claims (3)

A plurality of memory cell transistors disposed on a semiconductor substrate;
Writing means for writing data to the plurality of memory cell transistors by a writing operation;
Threshold verification means for verifying a magnitude relationship between a threshold value of a plurality of memory cell transistors in which data is written by the writing means and a constant threshold verification voltage; and
After the threshold verification voltage is set to the first verification voltage and a first write operation is performed on a desired memory cell transistor, the threshold verification voltage is set to the first verification voltage higher than the first verification voltage. Is set to a second verification voltage that is one-half larger than the threshold distribution width of the memory cell transistor after the end of the write operation, and the second verification voltage is smaller than the second verification voltage. A nonvolatile semiconductor memory device characterized by performing a writing operation. A plurality of memory cell transistors disposed on a semiconductor substrate;
Writing means for writing data to the plurality of memory cell transistors by a writing operation;
Threshold verification means for verifying a magnitude relationship between a threshold value of a plurality of memory cell transistors in which data is written by the writing means and a constant threshold verification voltage; and
After the threshold verification voltage is set to the first verification voltage and a first write operation is performed on a desired memory cell transistor, the threshold verification voltage is set to the first verification voltage higher than the first verification voltage. Is set to a second verification voltage that is one-half smaller than the threshold distribution width of the memory cell transistor after the end of the write operation, and the second verification voltage is set to the second verification voltage greater than the second verification voltage. A nonvolatile semiconductor memory device characterized by performing a writing operation. A plurality of memory cell transistors disposed on a semiconductor substrate;
Writing means for writing data to the plurality of memory cell transistors by a writing operation;
Threshold verification means for verifying a magnitude relationship between a threshold value of a plurality of memory cell transistors in which data is written by the writing means and a constant threshold verification voltage; and
After setting the threshold verification voltage to the first verification voltage and performing a first write operation on a desired memory cell transistor, the center of the threshold distribution of the memory cell transistor after the completion of the first write operation The value is set as the second verification voltage, the second verification voltage is set to the threshold verification voltage, and the second write operation is performed on the memory cell transistor whose threshold does not reach the second verification voltage. A non-volatile semiconductor memory device, characterized in that:

Images