JP2001274283A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce such a fault as a pattern short generated in the wring patterns near the end surface of its board, in the semiconductor device wherein its semiconductor chip mounted on its board is sealed with a resin and its wiring pattern formed on its board which includes a plated wire reaches the edge of its board. SOLUTION: The semiconductor device has a board 11 wherein a wiring pattern 17A is formed on its one surface and the wiring pattern 17A reaches the edge the one surface, a semiconductor chip 12 mounted on the board 11 which has an integrated circuit, and a resin 15 so formed as to cover the wiring pattern 17A formed on the one surface and cover the semiconductor chip 12. Further, the resin 15 is so formed as to cover a plated wire 17B which reaches the edge of the one surface of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip mounted on a substrate is sealed with a resin, and in particular, external connection terminals formed on the back surface of the substrate are arranged in an area. BGA and LGA.

[0002]

2. Description of the Related Art In recent years, with an increase in the number of I / O pins and a reduction in pitch, a semiconductor device having I / O pins arranged in a two-dimensional area has been widely used. As a typical example,
Surface mount BGA (Ball Grid Array), LGA
(Land Grid Array).

In the BGA and LGA, a semiconductor chip is mounted on one surface of a substrate, this semiconductor chip is sealed with resin, and external connection terminals formed on the other surface of the substrate are provided. They are arranged in a two-dimensional area.

[0004] A conventional semiconductor device (BGA) will be described below.

FIG. 5 is a perspective view showing the structure of a conventional semiconductor device.

As shown in FIG. 5, a semiconductor chip (integrated circuit) 110 is mounted on a substrate 130 by bonding with an adhesive 120. The wiring patterns 140 formed on the substrate 130 are arranged radially so as to surround the semiconductor chip 110. Terminal 15 of semiconductor chip 110
Numeral 0 is electrically connected to an external connection terminal (ball) 160 via a bonding wire 155 and a wiring pattern 140 by wire bonding. The periphery of the semiconductor chip 110 is surrounded by the resin 170.

The substrate 130 on the side surface of the semiconductor device
A plating line 180 used when plating the wiring pattern 140 on the substrate 130 is exposed between the resin 170 and the resin 170. That is, the plating wire 180 from the end portion of the substrate 130 is exposed. This plated wire 180
Are those that reach from each wiring pattern 140 to the end face 190 of the substrate.

[0008]

In a semiconductor device having the above-described structure, a plating wire 1 is formed from the side of the semiconductor device.
80 is exposed. For this reason, moisture, Na, Cl, or the like adheres to the plating wire 180 when the plating wire 180 is touched during handling or when the plating wire 180 is used for a long time even if it is not touched. When current is supplied in a state where moisture, Na, Cl, etc. adhere to the plating wire 180,
There is a problem that migration occurs in the plating lines 180 and short-circuit occurs between the plating lines 180.

Therefore, the present invention has been made in view of the above-mentioned problems, and a semiconductor chip on a substrate is sealed with a resin, and a wiring pattern including a plating line formed on the substrate reaches an end surface of the substrate. It is an object of the present invention to provide a semiconductor device capable of reducing defects such as a pattern short-circuit occurring in a wiring pattern near an end face of the substrate.

[0010]

In order to achieve the above object, a semiconductor device according to the present invention has a first surface, a first surface and a second surface.
A second surface facing the first surface, and an end surface orthogonal to the first and second surfaces, wherein the wiring pattern formed on at least one of the first and second surfaces is the end surface. And a semiconductor chip mounted on a first surface of the substrate and having an integrated circuit; and a wiring pattern on the first surface and an end surface of the substrate so as to cover the semiconductor chip. And a formed resin.

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention comprises the steps of: forming a first slit in a substrate so as to surround a region where a semiconductor chip is to be mounted; A step of mounting a plurality of semiconductor chips on a substrate provided with a slit, and a step of covering the plurality of semiconductor chips with a resin and filling the resin in the first slit and on the substrate, Cutting the resin and the substrate between the semiconductor chips, and dividing the plurality of semiconductor chips covered with the resin into individual semiconductor chips.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a perspective view showing the structure of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a diagram of the semiconductor device as viewed obliquely from above.

This semiconductor device comprises a substrate 11, a semiconductor chip 12, an adhesive 13, a bonding wire 14, a resin 1
5. It has a terminal 16 for external connection.

The substrate 11 is made of a tape material made of polyimide, an organic material, ceramic or the like.

The semiconductor chip 12 is a semiconductor substrate on which a semiconductor integrated circuit is formed, and has on its surface terminals 19 connected to the semiconductor integrated circuit. The bonding wire 14 is a fine wire such as Au (gold) or Al (aluminum), and connects between the terminal 19 and the wiring pattern 17A.

The resin 15 protects the semiconductor chip 12 and the bonding wires 14 from external stress, and further protects from moisture and contaminants. The external connection terminal 16 includes:
The semiconductor device is made of a ball such as solder and is used to electrically connect the semiconductor device to the outside.

As shown in FIG. 1, a semiconductor chip (integrated circuit) 12 is mounted on one surface of a substrate 11 by bonding with an adhesive 13. The wiring patterns 17A on the substrate 11 are arranged radially so as to surround the semiconductor chip 12. The terminal 19 of the semiconductor chip 12 is electrically connected to the wiring pattern 17A via the bonding wire 14 by wire bonding. Further, the wiring pattern 17A is electrically connected to the external connection terminal 16 via a through hole (not shown).

At the end of the substrate 11, a wiring pattern 1
A plated wire 17B used when plating 7A is formed. The plated wire 17B extends from each wiring pattern 17A to the end face 18 of the substrate.

The substrate 11 including the semiconductor chip 12, the bonding wires 14, and the plating wires 17B is covered with a resin 15 and sealed. Further, the substrate end surface 18 is also covered with the resin 15. Thus, the structure is such that the plating wire 17B reaching the substrate end face 18 is not exposed.

When the plated wires are not formed on the four corners of the substrate 11, it is not necessary to cover the end surfaces of the corners with the resin 15 as shown in FIG. If a plating wire is also formed at the corner, the end face of the corner is covered with a resin 15.
To cover.

In a semiconductor device having such a structure,
Since the plating wire is not exposed to the outside, there is no possibility of touching the plating wire during handling or the like, and adhering moisture or contaminants. Furthermore, since it does not come into contact with the outside air, there is no possibility that moisture, contaminants, and the like will adhere thereto. Therefore, occurrence of migration can be suppressed, and short-circuit of wiring can be prevented.

[Second Embodiment] In the second embodiment, the external connection terminals formed by balls in the first embodiment are replaced with land patterns having no protrusions. The other configuration is the same as that of the first embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. Only different components will be described below.

FIGS. 2A and 2B are perspective views showing the structure of a semiconductor device according to a second embodiment of the present invention. FIG. 2A is a diagram of the semiconductor device as viewed obliquely from above, and FIG. 2B is a diagram of the semiconductor device as viewed obliquely from below.

As shown in FIG. 2B, a land 2 formed of an electrode pattern is
6 are provided.

In a semiconductor device having such a structure,
Since the plating wire is not exposed to the outside, there is no possibility of touching the plating wire during handling or the like, and adhering moisture or contaminants. Furthermore, since it does not come into contact with the outside air, there is no possibility that moisture, contaminants, and the like will adhere thereto. Therefore, occurrence of migration can be suppressed, and short-circuit of wiring can be prevented.

[Third Embodiment] In the third embodiment, the connection between the terminal 19 of the semiconductor chip 12 and the wiring pattern 17A performed by wire bonding in the first embodiment is described. This is performed with bumps, and the other configuration is the same as that of the first embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. Only different components will be described below.

FIG. 3 is a perspective view showing a configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 3 is a view of the semiconductor device as viewed obliquely from above.

As shown in FIG. 3, bumps 34 are formed on the terminals of the semiconductor chip 12, and the bumps 34 are connected to the wiring patterns 17A. As a result, the terminals of the semiconductor chip 12 become external connection terminals (balls) 16.
Is electrically connected to

In a semiconductor device having such a structure,
Since the plating wire is not exposed to the outside, there is no possibility of touching the plating wire during handling or the like, and adhering moisture or contaminants. Furthermore, since it does not come into contact with the outside air, there is no possibility that moisture, contaminants, and the like will adhere thereto. Therefore, occurrence of migration can be suppressed, and short-circuit of wiring can be prevented.

In the first to third embodiments, the plating wire exposed from the space between the substrate and the resin is covered with the resin to prevent handling and adhesion of moisture and contaminants in the atmosphere. In addition, wiring short-circuit due to occurrence of migration is prevented. Accordingly, it is possible to cope with a reduction in the gap amount of the plating line due to the trend of miniaturization of the package.

The resin covering the upper surface and the end surface of the substrate is
It is formed with a thickness of at least 0.1 mm from the end face, and maintains close contact with the end face. This makes it possible to lengthen the entry path for moisture and the like, and to achieve excellent moisture resistance.

[Fourth Embodiment] In the fourth embodiment, a method of manufacturing the semiconductor device of the first embodiment will be described.

FIGS. 4 (a) to 4 (e) show the above-described first embodiment.
FIG. 18 is a perspective view of each step showing the method for manufacturing a semiconductor device of the embodiment. FIGS. 4A to 4E show the semiconductor device viewed obliquely from above. In this embodiment, a plurality of, here four, semiconductor devices are made into one unit, and four semiconductor chips are simultaneously covered with resin,
Thereafter, the case of cutting into individual semiconductor devices will be described.

As shown in FIG. 4A, a slit 52 is formed on a substrate 51 so as to surround a region where a semiconductor chip is mounted.
To form Further, slits 53 are formed on both sides where four semiconductor chip mounting areas are secured.

In the step before the slits 52 and 53 are formed, the wiring pattern 17A on the substrate 51 is plated using the plating lines 17B. The plating wire 17B is cut by the slit 52.

The slit 52 is formed by the plating wire 17.
Depending on the state in which B is formed, if the plating lines 17B are formed on four sides of the semiconductor chip, they are formed on four sides,
If it is formed on three sides, it is formed only on three sides, and if it is formed only on two sides or only one side, it is formed only on two sides or only one side, respectively.

At this time, the shape of the slit 52 is as shown in FIG.
As shown in (a), the semiconductor chip may be formed on each of four sides individually for each side, or may be formed by connecting three sides into a “U” shape, and further connecting two sides to form “ It may be formed in the shape of "".

The thickness of the substrate 51 is 0.2 mm.
It is about 0.3 mm. The width of the slit 52 is set to a minimum of about 0.3 mm, and the length is set to a length capable of cutting all the plating lines 17B formed on one side. The width of the slit 53 is set to about 1.1 mm, and the length is set to a length capable of eliminating warpage caused by resin formation.

Next, on the substrate 51 provided with the slits 52 and 53, as shown in FIG.
2 are mounted, respectively. Further, the semiconductor chip 1
As shown in FIG. 4C, a bonding wire 1 is formed by wire bonding between the terminal 2 and the wiring pattern.
4 is formed.

Next, a resin 15 is formed on the substrate 51 including the four semiconductor chips 12, the bonding wires 14, and the slits 52 as shown in FIG.
1 is sealed. In this step, resin molding is performed so that the resin 15 enters the slit 52, and the four semiconductor chips 12 are simultaneously sealed with the resin. Furthermore, resin 15
External connection terminals (balls) 16 are formed on the back surface opposite to the substrate surface on which is formed.

Thereafter, as shown in FIG. 5E, the resin 15 and the substrate 51 are cut using a cutter 56, and the four integrated semiconductor devices are divided into individual semiconductor devices. In this step, the slit 52 filled with the resin 15 is used.
Is cut along the vicinity of the center of the substrate 51, so that the resin 15 remains on the end face of the substrate 51 in the slit 52, that is, as shown in FIG. The thickness of the resin 15 from the substrate end face 18 is set to a minimum of about 0.1 mm.

In the manufacturing method described above, a plurality of semiconductor chips 12 on the substrate 51 are sealed in a single resin molding step, and then cut into individual semiconductor devices. Therefore, even if the size of the semiconductor device changes,
If a desired size is cut in the cutting step, it is possible to cope with the size change. Therefore, it is not necessary to prepare a mold for resin molding according to the size change, and the mold can be unified. Therefore, manufacturing costs can be reduced.

Further, at this time, since four semiconductor chips are resin-sealed in one resin forming step, warpage may occur due to an increase in the size of the resin. However, this warpage can be eliminated by the slit 53 that divides the four integrated semiconductor chips.

In a state where the semiconductor chip 12 is mounted on the substrate 51 as shown in FIG. 5C, the individual semiconductor devices are divided by the slits 52, so that the electrical check of each semiconductor device can be performed. It is possible.

Also, the width of the slit 52 must be at least 0.3 m.
If m is ensured, a sufficient amount of resin can be left on the end face of the substrate even when the accuracy of resin loading and separation is taken into consideration.

In the above-described embodiment, the case where the wiring pattern is formed on one surface of the substrate and this wiring pattern (plated wire) reaches the end surface of the substrate has been described. However, the present invention is not limited to this. The present invention can be applied even when wiring patterns are formed on both sides and these wiring patterns (plated wires) reach the end face of the substrate. Further, the present invention can be similarly applied to a case where the substrate is a multilayer substrate, wiring patterns are formed on a plurality of layers, and these wiring patterns (plated wires) reach the end face of the substrate.

[0048]

As described above, according to the present invention, there is provided a semiconductor device in which a semiconductor chip on a substrate is sealed with a resin, and a wiring pattern including a plating line formed on the substrate reaches an end surface of the substrate. Further, it is possible to provide a semiconductor device capable of reducing problems such as pattern short-circuits occurring in a wiring pattern near the end face of the substrate.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a perspective view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a perspective view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention;

FIG. 4 shows the first embodiment as a fourth embodiment of the present invention.
FIG. 18 is a perspective view of each step showing the method for manufacturing a semiconductor device of the embodiment.

FIG. 5 is a perspective view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Substrate, 12 ... Semiconductor chip 13 ... Adhesive 14 ... Bonding wire 15 ... Resin 16 ... External connection terminal 17A ... Wiring pattern 17B ... Plating wire 18 ... End face of the substrate 11 19 ... Terminal of semiconductor integrated circuit 26 ... Land 34 ... Bump 51 ... Substrate 52 ... Slit 53 ... Slit 56 ... Cutting machine

Claims (8)

[Claims] 1. A first surface, a second surface facing the first surface.
A substrate having an end surface orthogonal to the first and second surfaces, and a wiring pattern formed on at least one of the first and second surfaces reaching the end surface; A semiconductor chip mounted on a first surface of the substrate and having an integrated circuit; and a resin formed on the first surface and the end surface of the substrate so as to cover the wiring pattern and the semiconductor chip. A semiconductor device, comprising: 2. The substrate according to claim 1, wherein the resin is not formed on at least one of the four corners of the end face of the substrate, and the end face of the substrate is exposed. Semiconductor device. 3. The semiconductor device according to claim 1, further comprising an external connection terminal formed on a second surface of the substrate and electrically connected to a wiring pattern on the first surface. 3. The semiconductor device according to 2. 4. A step of forming a first slit in a substrate so as to surround a region where a semiconductor chip is to be mounted, and mounting a plurality of semiconductor chips on the substrate provided with the first slit, respectively. And covering the plurality of semiconductor chips with a resin.
Filling the resin in the slits and on the substrate, cutting the resin and the substrate between the semiconductor chips, and dividing the plurality of semiconductor chips covered with the resin into individual semiconductor chips; A method for manufacturing a semiconductor device, comprising: 5. The step of forming the first slit, wherein the first slit is formed on at least one of sides around a semiconductor chip to be mounted. The method for manufacturing a semiconductor device according to claim 4, wherein: 6. The method according to claim 4, further comprising the step of forming an external connection terminal on another surface of the substrate opposite to the surface on which the semiconductor chip is mounted. . 7. In the step of dividing into individual semiconductor chips, the resin filled in the first slit is cut, and the resin is left on the end surface of the substrate in the first slit. 7. The method for manufacturing a semiconductor device according to claim 4, wherein: 8. The thickness of the resin on an end face of the substrate is:
The method for manufacturing a semiconductor device according to claim 7, wherein the thickness is at least 0.1 mm or more.