JP2001265828A - Logic verification system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently confirm the operation of a logic circuit when a fault of logical operation is detected by simulation by using a logic simulation result file with small capacity. SOLUTION: A logic simulation execution part 108 performs logic simulation by using logic circuit information 102, simulation execution control information 103, and state data 104 and obtained signal value variation information on an object logic circuit is stored in a simulation result (temporary) file 106; and a simulation result comparison part 101 compares the signal value variation information stored in the file with previously set expected value information. When they do not match each other, the signal value variation information stored in the simulation result (temporary) file 106 from the time which is a previously specified output range time before their discrepancy is generated until the discrepancy is generated is stored in a simulation result and the subsequent logic simulation is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation used at the time of logic verification of a logic device. When a defect existing in the logic device is detected in the logic simulation, output information of the logic device is stored in a file. It relates to a logic verification method.

[0002]

2. Description of the Related Art Conventionally, in a logic simulation, a logic circuit to be verified is converted into a format such as a Boolean algebra suitable for the simulation, and a specific signal value is set to a signal line on the logic circuit. Using a means for performing a logical operation on the signal value of each logical element of the logical circuit and propagating the signal value of the operation result in accordance with the connection state, a result file which is a logical simulation result is stored in a section designated in advance or from the end of the logical simulation. The signal value change information of the designated section was output. The method of confirming the logical operation using the waveform image using the logical simulation result file is an effective means for grasping the entire logical operation. A logic simulation method using these logic simulation result files is disclosed in JP-A-4-15757 and JP-A-4-18557.
No.

[0003]

The above prior art is effective as a means for confirming the operation of a logic circuit, but the output file capacity becomes large due to the huge amount of signal change information of the logic circuit, and the waveform display becomes very large. There is a problem that processing time is required, or information for pursuing a defect is insufficient due to insufficient output range specification, and a re-execution of the logic simulation is required. The object of the present invention is
An object of the present invention is to make it possible to efficiently check the operation of a logic circuit when a malfunction of a logic operation is detected during execution of a logic simulation using a logic simulation result file having a small capacity.

[0004]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is a logic verification method in a logic simulation for constructing a logic circuit information to be verified on a computer and verifying an operation of the logic circuit to be verified. Determining means for determining signal value change information of the verification target logic circuit during execution of the logic simulation; output means for outputting signal value change information of the verification target logic circuit as a result file based on the determination result; Means for designating an output range time to a file, wherein the output means, when the determination result of the determination means indicates the occurrence of a failure, the output range time specified by the logic simulation time at which the failure occurred. The signal value change information from the previous time to the logic simulation time at which the defect occurred is output to a result file, and So that to provide effective data for confirmation proof target logic circuit. Further, the determination means compares the signal value change information with a preset expected value, and outputs a determination result indicating the occurrence of the defect when the information does not match, and outputs the determination result indicating the occurrence of the defect. Then, the logic simulation is stopped. The signal value change information includes a plurality of types of signal value change information, and an expected value is set in advance for each type of the signal value change information, and the determining unit determines the signal value change for each type of the signal value change information. The information is compared with an expected value set in advance for the signal value change information, and when the information does not match, a determination result indicating the occurrence of the problem is output.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an example of a system configuration according to the present invention. Logic simulation execution unit (108)
Now, a simulation execution control information file (103) for controlling a simulation state, a logic circuit information file (102) of a target logic circuit which has been previously converted into a simulation executable format, and a test for operating the logic circuit The data file (104) is read, and the change of the signal value of the signal line specified by the simulation execution control information (103) is temporarily changed in each simulation time unit.
06). Simulation result comparison unit (10
In 1), the expected value information file (105) in which the output expected value of the logic circuit is stored and the temporary simulation result file (106) output by the logic simulation execution unit (108) are read, and at the simulation time, The output expected value is compared with the simulation result. If the contents are different, the signal value change information of the previous section specified by the simulation execution control information (103) is stored in the temporary simulation result file (1).
06) and the simulation result file (1
07).

FIG. 2 shows an example of a method of temporarily storing a simulation result. The signal value change information of the simulation result output during the execution of the logic simulation is divided into a predetermined time (output range time). 9 illustrates an example of a method of outputting signal value change information exceeding time to a temporary work file. In order to hold the simulation result for the specified output range time, it is necessary to secure a capacity at least a little larger than the capacity that can hold the simulation result for the output range time. Therefore, the capacity (A) that can hold the simulation results for the output range time specified by the simulation execution control information (103) is defined as the total capacity of the plurality of simulation result temporary storage files (202), The subdivision constant k is defined based on the rule, the capacity of one simulation result temporary storage file (202) is set to capacity (A) / k, and the capacity of the simulation result temporary storage file (202) is larger than the capacity capable of holding the simulation result for the output range time. (1 + k) simulation result temporary storage files (202) are allocated as temporary work files. Then, the simulation result is output to a simulation result temporary storage file (202) designated by the simulation result output destination instructing unit (201).

A simulation result output destination instructing unit (20)
1) initially indicates the simulation result temporary storage 1, but after writing the simulation result to the simulation result temporary storage 1, it indicates the simulation result temporary storage 2. In this way, after sequentially outputting the simulation result temporary storage k + 1, the process returns to the simulation result temporary storage 1 again. When the writing to the simulation result temporary storage 1 occurs, the previous simulation result already written in the simulation result temporary storage 1 disappears, but k simulation results from the simulation result temporary storage 2 to the simulation result temporary storage k + 1 are lost. The simulation result of the simulation result temporary storage file (202) remains, and the simulation result for the designated output range time can be held.

FIG. 3 shows a simulation result temporary file (106) to a simulation result file (10).
7) shows a method of making the above. Since the simulation result temporary file is reused during the execution of the logic simulation, a method for storing the output result from the simulation result temporary file in the order of the simulation time must be guaranteed. Here, an example is shown. In the simulation result temporary file (308), a signal information table (311) in which a simulation time and an output value are stored is stored for each signal, and one from the number specified by the subdivision constant k (408). The simulation result temporary storage file (202) having only the larger number of files. In order to create the simulation result file (310) from the simulation result temporary file (308), first, the simulation result output destination instructing unit (309) reads the simulation result temporary storage file (202) which is the current simulation result output destination. Read the file number (30
1). Next, it is determined whether the file number points to the last file of the temporary output file (302), and if it points to the last file, the file number is set to 1 (303). If it does not point to the last file, the file number is increased by one (306).

The corresponding simulation result temporary storage file (202) is read from the obtained file number (304). The read signal information is written to the simulation output result file (310) (30
5). Next, the file number is compared with the file number specified by the simulation result output destination specifying unit (30).
7) If they match, all simulation result temporary storage files (202) have been processed,
The process ends. If not, step 302
Return to and continue reading the file. By doing so, the simulation result temporary file (30
A simulation result file (310) in which signal information is stored in the order of simulation time based on 8) can be created.

FIG. 4 shows a specific execution method using a flowchart. First, in the input of the waveform output period (402), the simulation waveform output period (same as the output range time) is read (401). Next, the subdivision constant table (40
The subdivision constant k is obtained from 3), and the storage capacity per unit required for temporarily storing the simulation result (the same as the storage capacity of the simulation result temporary storage file (202)).
(404). In order to guarantee the simulation waveform output period, (k + 1) storage capacities are secured (40
5) That is, (k + 1) simulation result temporary storage files (202) are secured, and initial processing accompanying the simulation start is executed (406). Next, the value i of the simulation result output instruction unit is set to 1 (407). The simulation result output destination is stored in the simulation result output destination instruction unit (408),
Enables later reference. The signal value change information obtained by the simulation execution unit (409) is stored in the i-th storage location (410), and the expected value information (411) read in reading the expected value information (412)
Is compared with the signal value (413). If the comparison results in a mismatch, the (i + 1) -th to (k + 1)
The simulation result temporary storage file (20
The signal value change information stored in (2) and the first to i-th simulation result temporary storage files (2
02) is sequentially output to the simulation result file (415) (41).
4) Thus, the simulation result file (415) can be created in the order of the simulation time.

If the signal values match (413), the simulation time is updated (416). When the simulation time ends (417), the signal value change information already stored in the (i + 1) -th to (k + 1) -th simulation result temporary storage file (202), and the first to i-th simulation results The signal value change information stored in the temporary storage file (202) is output (414) to the simulation result file (415) in order. If the simulation time has not expired, the value of the simulation result output destination instructing unit is increased by one (418), and preparations are made for writing to the next simulation result temporary storage file (202). If the value of the simulation result output destination instructing unit becomes larger than the subdivision constant k (419), the simulation result temporary storage file (20) used first is used.
In order to write to 2), the value of the simulation result output destination instructing unit is set to 1 again (407). If the value of the simulation result output destination indicating section is equal to or smaller than the subdivision constant k, the simulation is continued (409). By changing the value of the simulation result output destination indicating unit in this way,
Waveforms for the simulation waveform output period can be guaranteed with a small storage capacity.

FIG. 5 shows a data flow at the time of simulation. The data flow until the simulation result shown in the time chart is stored in the simulation result output file (502) will be described in the order of the simulation time. Here, for the sake of explanation, the subdivision coefficient is set to 2, and the waveform output range time is set to 8 [ns].
Each simulation result temporary storage file can store 4 [ns] of results. First, at the start of the simulation, each signal value is stored in the signal value table (503). In creating the simulation result temporary storage file 1 (504), the signal value table (503) is copied and the initial value table (50) is copied.
5) is created. This is to guarantee the initial value in each simulation result temporary storage file, and is updated each time the simulation time advances. Next, the signal values obtained as a result of the simulation are stored in each signal information table (5).
06) together with the simulation time. However, in order to save capacity, a signal whose signal value does not change is not stored again. When the simulation result temporary storage file 1 (504) becomes full, the next simulation result temporary storage file 2 (507) is created, and the initial values and the respective signal values are stored in the same manner. After data is similarly stored in the simulation result temporary storage file 3 (508), the simulation result temporary storage file 1 (509) is created again. Here, the data of the old simulation result temporary storage file 1 (504) is discarded.

At each simulation time, the expected value information table (510) prepared in advance and the signal value table (503) are compared (511). If the expected value does not match the signal value, the simulation result is output. Create a file (502). First, according to the method described with reference to FIG.
The simulation result temporary storage file 2 (507) having the oldest simulation time is selected based on the value of 2), and the initial value table is stored in the simulation result output file (502) therefrom. Next, each signal information table (514) is stored in the simulation result output file (502). Similarly, each signal information table (5) of the simulation result temporary storage file 3 (508)
15), simulation result temporary storage file 1 (5
09) is stored in the simulation result output file (502). further,
A mismatch information table (52) that stores the names of the signals whose expected values did not match and the times of the signals in order to enable tracking of the failure.
0) and a simulation result output file (50
Store to 2). An output waveform (517) is displayed from the simulation result output file (502) thus obtained. First, the initial value table (518) is read, and the initial value of each signal is determined. Next, each signal information table (519) is read, and the value of each signal at each time is determined. The portion without the time inherits the signal value of the previous time as it is. If there is no previous time, the initial value is used. By doing so, it is possible to obtain an output waveform (517) in which the signal value in the output range from the time of occurrence of the failure is guaranteed.

[0014]

According to the present invention, when a malfunction of a logic operation is detected during execution of a logic simulation,
By outputting the signal value change information from the specified time before the specified time to the failure occurrence time as a result file, it is possible to obtain a sufficient amount of information to pursue the failure of the logic operation, and to use a logic simulation result file with a small capacity. An efficient operation check of the logic circuit can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a system configuration of the present invention.

FIG. 2 is a diagram illustrating an example of a method for temporarily storing a simulation result.

FIG. 3 is a diagram illustrating a flowchart of a process of creating a simulation result file from a simulation result temporary file.

FIG. 4 is a diagram showing a flowchart of specific processing for creating a simulation result file from a simulation result temporary file.

FIG. 5 is a diagram showing a data flow at the time of simulation.

[Explanation of symbols]

 Reference Signs List 101 Simulation result comparison unit 102 Logic circuit information file 103 Simulation execution control information file 104 Test data file 105 Expected value information file 106 Simulation result temporary storage file 107 Simulation result file 108 Logic simulation execution unit 201 Simulation result output destination instruction unit 202 Simulation result Temporary file

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yoshito Mizoue 1 Horiyamashita, Hadano-shi, Kanagawa F-term in Hitachi Information Technology Co., Ltd. 5B046 AA08 JA05 KA01

Claims (3)

[Claims] 1. A logic verification method in a logic simulation for constructing logic circuit information to be verified on a computer and verifying the operation of the logic circuit to be verified, wherein a signal value of the logic circuit to be verified during execution of the logic simulation Determining means for determining change information; output means for outputting signal value change information of the logic circuit to be verified based on the determination result as a result file; and means for specifying an output range time to the result file. The output means, when the determination result of the determination means indicates the occurrence of a failure, from a time preceding the logic simulation time at which the failure occurred by the specified output range time to a logic simulation time at which the failure occurred. The signal value change information is output to a result file, and valid data for confirming the logic circuit to be verified is output. Logic verification system which is characterized by subjecting. 2. The logic verification method according to claim 1, wherein the determination unit compares the signal value change information with an expected value set in advance, and when the information does not match, determines a determination result indicating the occurrence of the failure. A logic verification method, wherein the logic simulation is stopped when a determination result indicating the occurrence of the failure is output. 3. The logic verification method according to claim 2, wherein the signal value change information includes a plurality of types of signal value change information, and an expected value is preset for each type of the signal value change information. Compares the signal value change information for each type of signal value change information with an expected value set in advance for the signal value change information, and outputs a determination result indicating the occurrence of the problem when the values do not match. A logic verification method characterized by the following.