JPH03250260A - Method for outputting result of logic simulation - Google Patents

Abstract

PURPOSE:To shorten time for retrieval by dividing the result of logic simulation into plural blocks when the result is outputted to a storage device, and outputting a signal value at the time of the simulation as initial value data to the heads of the respective divided blocks. CONSTITUTION:When outputting signal change information to the storage device as the result simulated by a logic simulator 3, the optimum data amount for a means to refer the contents is calculated from the amount of data to be outputted, and outputted to storage devices 7 and 8 in the form of dividing the result into the plural blocks. Further, the signal change information as the number of all signal lines at the time of the simulation is outputted to the head of each divided block. Therefore, the signal change information can be easily referred for each block. Thus, the time chart of the arbitrary simula tion time can be processed in a short time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a logic simulation for verifying the logic of a logic device, and relates to a simulation result suitable for obtaining signal change information at an arbitrary simulation time from the simulation result. Regarding the output method.

[Conventional technology]

In general, the operation results of a logic circuit in a logic simulator are output, and the signal changes at any time in the operation of the logic circuit are displayed on a terminal device, or output in the form of a time chart on a list, etc., to verify the logic circuit. The aim is to quickly identify errors in logic circuits and realize early circuit design.

The method of outputting the signal change state of a logic circuit in a logic simulator on a time chart is based on the Japanese Patent Publication No. 62-5086.
As shown in Publication No. 0, triggered by a trigger signal,
One method is to output a fixed time before and after that as a time chart.

However, this method does not describe the procedure for outputting simulation results to a file and the procedure for reading the file, and in a large-scale logic device, simply outputting signal changes at a fixed time would significantly increase the file capacity. In addition, the signal change information that is the simulation result is outputted to a storage device such as a disk, and the signal change information stored on the disk is displayed on the screen using a time sharing system using a video terminal or the like. Means for verifying the operation of a logic circuit by displaying the information on the top is used. Similarly, Japanese Patent Laid-Open No. 154374/1984 discloses a method of reducing file capacity by outputting only signals in which signal changes have occurred to a storage device.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into account the display of the output signal change information from an arbitrary simulation time, and there is a problem that it takes a long time to display the time chart on a video terminal or the like.

The present invention aims to process time charts at arbitrary simulation times in a short time, and further includes:
The purpose of this invention is to provide a means for efficiently distributing simulation results to storage devices.

[Means to solve the problem]

In order to achieve the above purpose, when outputting signal change information of simulation results to a storage device, the optimal amount of data is calculated from the amount of data to be output, and the data is divided into multiple blocks. We used a method of outputting to a storage device.

In addition, in order to divide optimally, the simulation time corresponding to each division position is calculated using the number of signal lines of the logic circuit that is the target of simulation output, the total number of signal change information, and the simulation execution time. The method was to divide the data at each time interval. Furthermore, the signal change information for the total number of signal lines at the simulation time is output at the beginning of each divided block, so that the signal change information can be easily referenced for each block.

[Effect]

The results of the logic simulation are output by outputting signal change information of the logic circuit that changes at each simulation time to a storage device. The amount of signal change at each simulation time is not constant and differs from one another, but even if this signal change information is divided from the number of output target logic gates, simulation execution length, and total number of signal changes and output to the storage device, each memory block By managing the simulation time for each, no contradiction occurs.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using the drawings. FIG. 1 shows an overview of the present invention. Input the simulation target logic circuit 1 and the input data 2 for verifying the logic circuit 1 into the logic simulator 3, calculate the element operation of the logic circuit 1 until the simulation end time specified by the input data 2, and output the simulation output result. Get 4.

This simulation output result 4 contains, as management information, the simulation execution time, that is, the simulation length, which is the length of time the logic circuit 1 operated, the number of gates of the logic circuit 1, which is the target of signal value output of the simulation, and the simulation output result. It has the total number of signal changes, and also stores change information for signals that changed at each simulation time, arranging them at the simulation time. The simulation output result 4 may be stored in an external storage device such as a DISC, or may be stored in a storage device such as a main memory while the simulation is being executed.

Next, the result editor 5 reads the management information of the simulation output result 4, and determines the optimal simulation time for division (for example, signal change ÷ simulation length
In order to find the value of n where n>number of target gates, that is, the value that minimizes the data length from each division point when reading the simulation results again, we calculate the signal change at each simulation time of each division block. A numerical value whose total value is larger than the initial value data amount of the divided block is determined, and file management information 6 is created. After outputting the file name or data set name to which the signal change value is to be output and the simulation time at which output to the file is to be started to the file management information 6, the contents are read from the signal change information of the simulation output result 4.

The initial value and signal change information at each simulation time are output to the output file 7.8. In this embodiment, an example is shown in which the simulation time O to time 29 is output to file 7, and the data after time 1 time 30 is output to file 8.

FIG. 2 shows a time chart of simulation results for the logic circuit 1 shown in FIG. Next, the flow of result editing 5 will be explained with reference to the flowchart of FIG. First, extract the management information from the simulation output result 4 (301)
After calculating the capacity to be divided and outputting the management information to the file 6, the file to which the signal change information is to be output is selected (302). Here, as the start time O,
The end time to select file 7 corresponding to start time O and output to that file 7 is determined by reading the start time 30 of file 8 from the following management information, and changing the output time width of file 7 from O to Set to 29. Next, the signal change information at time O from the simulation output result 4 is outputted to the file 7 as an initial value, and at the same time, an initial value record corresponding to each signal change information is created as an initial value area (303). Furthermore, if you leave the time as is, step 3o4. Step 305. After step 306, the simulation time is updated in step 307, and if the updated time is less than the end time of the management information, step 3
After passing through step 09, the process returns to step 304. At this time, when the updated time matches the simulation output result 4, the signal change information at that time is rewritten for the same signal line in the initial value area provided earlier (304). Similarly, the signal change information of the simulation output result 4 having the same time as the simulation time is output to the output target file (305). This signal change information setting is continued in step 306 until there is no signal change information at the same time. After completing the signal change information at the same time, advance the simulation time. The simulation time is
When the value shown in the following management information (here 30) is reached (
309), summarizes the contents of the initial value area updated up to that time (310), and further switches the file to which the signal change information should be output, and then outputs the initial value area as the initial value to the file to be output (31. 1).

Thereafter, the process returns to step 304, and the signal change information at the same time as the simulation time indicated at that time is read from the simulation output result and output to the file to which the signal change information is output (304).

These series of operations are repeated, and when the end time of the management information is reached, the process ends (308). With the above flow, the content of the simulation output result 4 can be divided and the signal change information can be stored in the output files 7 and 8. When referring to these output files, by reading the contents stored in the management information file, for example, for the signal value at time 40, file 8 can be selected from the management information file, and the signal changes from the beginning of file 8. Obtained by reading information.

In addition to this embodiment, the file division method can also be realized by specifying the number of divisions by parameters or by specifying the number of divisions by specifying the simulation time by slightly modifying this procedure.

〔Effect of the invention〕

According to the present invention, signal value information at an arbitrary simulation time can be read from a file divided into a plurality of files from simulation results, and search time can be significantly reduced. Furthermore, since the search time is short at any of the simulation times (5), the time required for logic verification using the simulation results is also short, which contributes to shortening the development period of the logic device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an overview of a simulation in an embodiment of the present invention, FIG. 2 is a diagram showing an example of a time chart of simulation results, and FIG. 3 is a flowchart showing a file division method according to the present invention. be. 1... Logic circuit to be simulated, 2... Input data, 3... Logic simulator. 4...Simulation output result, 5...Result editing section, 6...Management information file, 7...Output file, 8...Output file. Shimazu

Claims (1)

[Claims] 1. In a logic simulation method that simulates a logic circuit and outputs the result to a storage device, when outputting the logic simulation result to the storage device, the logic simulation result is divided into multiple blocks, and at the beginning of each divided block. A logical simulation result output method characterized by outputting a signal value at the simulation time as initial value data. 2. The above-mentioned method for dividing the logical simulation results is characterized in that the division is performed in an optimal way for reading the simulation results based on the simulation execution time, the number of signal changes, and the number of signal lines for outputting signal values. The method for outputting logical simulation results according to item 1.