JP2001256205A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make each of multiple processors easily recognize itself. SOLUTION: In a multiprocessor system 1, multiple processors 11, a memory 12 and an application state register 26 are connected to a single system bus 13. The application state register stores the present state of applying the use of the system bus to all the processors 11. When an exceptional event occurs, a processor to respond to this event accesses a physical address corresponding to this exceptional event and runs a program for branching processing stored in the physical address. As a result, the processor accesses the application state register after the use is applied, recognizes that a processor determined under the application of the use is itself on the basis of the application state of the use reported from the application state register in response to access, reads the program of a specified processing routine previously assigned to the recognized processor itself and starts running this program.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor device in which a plurality of processors are connected to a common system bus.

[0002]

2. Description of the Related Art As one type of a multiprocessor device of the prior art, there is a common memory type multiprocessor device in which a plurality of processors share a single memory.

FIG. 6 shows a central processing unit (Central Processi).
FIG. 2 is a block diagram showing a configuration of a common memory type multiprocessor device 1 of the related art using an ng Unit (hereinafter abbreviated as “CPU”) as a processor. Multiprocessor apparatus 1 of FIG. 6 includes in addition to the memory 4 shared as a plurality of processors 3 ₁ to 3 _N and a main memory, a system bus 5 and arbiter 6 by all processors to share. Note that N
Is the number of processors and is an integer of 2 or more, and n is 1
It is an arbitrary integer not less than N and not more than N. All processors 3 ₁ ~3 _N
The memory 4 is connected to one system bus 5. Right of use of the system bus 5 (hereinafter simply referred to as "usage rights") is the bus arbiter 6, is applied to any one processor among all processors 3 ₁ to 3 _N. Each processor 3n accesses the main memory 4 via the system bus 5 only while the usage right is granted.

A multiprocessor device disclosed in Japanese Patent Application Laid-Open No. 2-77866 discloses an expansion of a memory capacity of a memory serving as a main memory in addition to a plurality of processors, a single memory, a single system bus and a bus arbiter. For this purpose, a memory decoder for controlling data output from the memory is further provided, and the entire storage area of the memory is divided into a plurality of memory blocks. Each processor supplies a signal designating any one memory block to two signal lines of all signal lines of an address bus of the connected system bus, and supplies the remaining signal lines with any one of the signal lines. Gives the address to be accessed in one memory block. The memory decoder selects one of the memory blocks based on the signals on the two signal lines, and gives an address on the remaining signal line to the selected memory block.

Japanese Patent Laid-Open Publication No. 2-42558 discloses an information processing system such as a general-purpose computer. In the information processing system, a plurality of service processors access the information processing main unit via the interface device and write data in a memory of the information processing main unit. In order to prevent inconsistency in the written data, the interface device permits or prohibits access to the memory of the information processing main unit from each service processor according to the access content.

The multiprocessor device 1 shown in FIG.
Conventional multi-processors of the shared memory type, such as the multiprocessor of Japanese Patent Application Laid-Open No. 77866/1995 and the information processing system of Japanese Patent Application Laid-Open No. 2-42558, are provided if all processors share a single address bus. if, the physical address space of all the processors 3 ₁ to 3 _N becomes common. When CPUs are used as the processors 3 _n in the conventional multiprocessor device 1, all the CPUs are used when exception factors such as resets and interrupts occur.
3 ₁ to 3 _N is often physical address to be accessed is equal to each other.

The multiprocessor system disclosed in Japanese Unexamined Patent Publication No. Hei 8-272756 discloses a boot process at the time of reset release when the physical addresses for activation when the exceptional factors of the processors 3 _n are equal to each other. The multiprocessor system of the publication includes a plurality of processors, a common memory that is a main memory, a system bus, and a bus arbiter,
In addition, a single boot ROM in which a code for booting the system is stored is included in the common memory.
When the system reset is released, all the operable processors respectively request acquisition of the right to use the system bus in order to access the boot ROM. The bus arbiter
The bus arbiter grants the right to use one of the processors requesting the right to use the other processor until the execution of the code stored in the boot ROM is completed by the one processor. The right to use has been suspended.

As described in Japanese Patent Application Laid-Open No. 8-272756, in a conventional multiprocessor device in which a plurality of processors share a single memory and a single system bus, all processors have a single physical address. Since the space is shared, if the predetermined starting physical addresses accessed by the processors at the time of occurrence of the exception cause are equal to each other, all the processors try to access the starting physical address of the memory at the time of occurrence of the exception cause. Therefore, when the above-mentioned exceptional factor occurs, all the processors execute the same single processing program.

In the multiprocessor device 1 of the prior art, it may be desired that the processors 3n execute mutually different programs. For example, Japanese Patent Application Laid-Open No. 8-
In the multi-architecture processor system disclosed in Japanese Patent No. 263460, when it is necessary to switch to another processor while any one of the processors is operating, the operating processor uses its interrupt control circuit to perform its own operation. And an interrupt routine is started in response to the interrupt. The processor executing the interrupt routine issues a hold signal from the toggle circuit to the remaining processors including itself other than the processor to be operated, and enables only the processor to be operated.

In the multi-architecture processor system, it is necessary to provide a dedicated main memory for each processor, and it is difficult to share a single main memory among a plurality of processors. As a result, advantages resulting from the use of the main memory, that is, low cost, small size, and low power consumption cannot be obtained. Further, in the multi-architecture processor system, since only one processor is always operating, it is difficult for a plurality of processors to operate in parallel even when all processors do not use the system bus, such as at the time of a cache hit. It is.

[0011]

In [0007] multiprocessor prior art it has been described above 1, particularly when the occurrence of an exception factor, thereby executing the mutually different programs to each processor 3 _n is desired. In addition, in order to reduce the manufacturing cost, the size of the device, and the power consumption, it is desired that the multiprocessor device 1 of the related art has a plurality of processors sharing the memory 4 and the system bus 5. . If CPUs having the same starting physical address accessed first when an exceptional factor occurs are used as the processor 3 _n , in the multiprocessor device 1, the memory 4 and the system bus 5 are shared, and each CPU 3 _n Since the physical address spaces are common to each other, any of the CPUs 3 _n will not
First, the physical address for activation is accessed. As a result, in the multiprocessor ₁ having a configuration in which a plurality of processors 3 _{1 to} 3 _N having the same starting physical addresses and a memory and a system bus are shared by the plurality of processors, each of the processors 3 3
It is impossible for _n to start different programs.

An object of the present invention is to cause a plurality of processors having the same physical address for activation when an exceptional factor occurs to share a memory and a system bus, and to cause the processors to execute mutually different processes when an exceptional factor occurs. It is to provide a multiprocessor device which can be used.

[0013]

SUMMARY OF THE INVENTION The present invention includes a plurality of processors, a memory, a system bus, and a bus arbiter.
All the processors and the memories are connected to the system bus, the bus arbiter grants the right to use the system bus to any one of the processors, and only the processor to which the right to grant is accessing the memory via the system bus. A multiprocessor device, including a self-aware circuit for notifying the current grant status of the use right to each processor to the processor in response to a request from the processor to which the use right is being granted; The processor is a multiprocessor device that recognizes that the processor determined to be granted the usage right is itself based on the grant status of the usage right notified from the self-recognition circuit.

According to the present invention, in a multiprocessor having a configuration in which a plurality of processors share a memory and a system bus, a recognized processor, which is one of the processors requiring self-recognition, is given a use right. Within a certain period, a notification of the use right grant status is received from the self-recognition circuit, and any one of the processors determined to be granted the use right based on the notified grant status recognizes itself. As described above, in the multiprocessor device, since the processor can recognize itself based only on the state of use right, the configuration for self-recognition becomes extremely easy. If self-recognition is possible in this manner, each processor can perform a process that requires self-identification.

In the multiprocessor device according to the present invention, the self-recognition circuit includes an assignment status register holding data indicating a current assignment status of the use right to all the processors, and the bus arbiter is provided for each processor. A bus grant signal whose state is determined according to the granting state of the use right to the processor, is given to the processor and the bit cells associated with the processor in the granting state register, and each bit cell of the granting state register is provided. Latches and holds the current state of the bus grant signal to the processor associated with each bit cell, and the self-recognition circuit responds to a request from the processor granting the right to use, The processor is notified of the state of the bus permission signal stored in all bit cells in the assignment state register.

According to the present invention, in the multiprocessor device, the current state of the bus permission signal given to each processor from the bus arbiter for controlling the grant of the right of use to each processor is provided in the self-recognition circuit. Each bit cell of the register is latched. The data stored in the result assignment state register is represented by a bit string composed of bits equal to or greater than the number of all processors, and uniquely indicates the processor to which the use right is assigned by a combination of the state of each bit. Thus, the self-recognition circuit can easily and extremely easily create data indicating the current grant status of the usage right to all processors. Since the data in the grant status register uniquely indicates the processor to which the use right is being granted, the processor to which the use right is being granted can be diverted as its own identification data. This facilitates the processing when the processor to which the usage right is being granted performs processing that requires self-identification.

The multiprocessor device of the present invention further includes a memory decoder which responds to a physical address given to an address bus in the system bus and controls transmission of data to a data bus in the system bus. The recognition circuit includes a grant status register holding data indicating a current grant status of the use right to each processor, and the memory decoder and the grant status register include:
The processor connected to the system bus and granting the usage right sends a predetermined physical address previously assigned to the grant status register to the address bus, and the memory decoder sends the predetermined physical address to the address bus of the predetermined physical address. The data stored in the assignment state register is transmitted to the data bus in response to the transmission of the data.

According to the present invention, in the multiprocessor device, a predetermined physical address is previously assigned to the assignment status register in the self-recognition circuit, and the assignment status register is connected to the system bus. Data transmission from the status register is controlled. As a result, the register that is granting the usage right can request the self-recognition circuit to notify the granting state in the same procedure as the general procedure for accessing the memory via the system bus and the memory decoder. Further, since the assignment status register is connected to the system bus, the right to use is always assigned to the processor that acquires data from the assignment status register. As a result, the processor that requests the self-recognition circuit to issue the grant status is automatically limited to the processor that is granting the usage right. In addition, each processor can cause the self-recognition circuit to create data that uniquely identifies itself only by accessing the assignment state register in the same procedure as that for accessing a general memory.

In the multiprocessor device according to the present invention, the self-recognition circuit delays a bus grant signal from the bus arbiter to each processor, and provides the delayed bus grant signal to each bit cell of the assignment status register. A delay circuit that changes the timing of the change of the state of the bus permission signal from the state in which the use right is not granted to the state in which the use right is granted, so that the processor to which the bus permission signal is applied can actually transmit an address to the system bus. The bus permission signal provided from the bus arbiter to the self-recognition circuit is delayed until the timing coincides.

According to the present invention, in the multiprocessor device, the bus arbiter is operated until the timing of the state transition of the bus grant signal accompanying the grant of the usage right coincides with the timing at which the address transmission from the processor newly granting the usage right actually becomes possible. Is delayed. The state of the delayed bus permission signal Delayed-GTNn is latched by the provision state register. This prevents a self-recognition error of the processor due to the difference between the two timings.

In the multiprocessor device according to the present invention, the memory stores a program for a predetermined specific processing routine individually assigned to each of the processors. Request for the right, (2) after granting the right to use, request the self-identifying circuit to notify the state of grant of the right to use, and (3) assign to the own processor recognized based on the state of grant of the right to be notified. The program of the specified processing routine is read out from the memory via the system bus, and the program is executed.

According to the present invention, in the multiprocessor device, after the processor is given the right to use the system bus, the processor performs self-recognition using the self-recognition circuit before reading the program of the specific processing routine. Therefore, it becomes possible to read the program of the specific processing routine assigned to itself. As described above, when the multiprocessor device has the self-recognition circuit and the self-recognition process is performed after the use right is granted and before the program of the specific processing routine is read, different programs can be activated for each processor.

In the multiprocessor device according to the present invention, each of the processors requests the bus arbiter for the use right in response to the occurrence of a predetermined exceptional event, and after the use right is granted, the processor in the memory via the system bus. When a physical address for access to a predetermined exception is accessed and an instruction described in the start address is executed, and the physical addresses for exception activation of all processors are equal to each other, the memory is set to an exception. The program further stores a branch processing routine program for branching processing at the time of activation, and a start address of the branch processing routine program in the memory is equal to the physical address for the exception activation,
The program of the branch processing routine is provided to a processor,
Requesting the self-recognition circuit to be notified of the current grant status of the use right, and reading a program of an individual processing routine for its own processor that is recognized based on the notified grant status. And

According to the present invention, in the multiprocessor device, if the physical addresses for exception activation of all the processors are equal to each other, a branch processing routine is added to a portion of the memory starting with the physical address for exception activation. The program is stored in advance. The branch processing routine program causes the processor under the use right to read the program with the self-recognition process. This allows the multiprocessor device to operate even when multiple processors share a single physical address space and physical addresses for exception activation of each processor are equal to each other when exceptional events such as interrupts and resets occur. Different programs can be started and executed each time.

[0025]

FIG. 1 is a block diagram showing an electrical configuration of a multiprocessor device 10 according to an embodiment of the present invention. The multiprocessor device 10 of FIG. 1 is a shared memory type multiprocessor system in which a plurality of processors 11 share a single memory 12 and a single system bus 13.

The multiprocessor device 10 includes a plurality of processors (processors) 11, a single shared memory 12, a system bus 13, and a bus arbiter (Arbite).
r: arbitration circuit) and a self-identification circuit (Self Identify Ci)
ruit) 15 at least. The system bus 13 is
It includes at least an address bus and a data bus. The multiprocessor device 10 preferably includes a memory decoder (Memory Decoder) 16 and an interrupt control circuit (Interr).
upt Controller) 17. All processors 11
The al, the shared memory 12, the memory decoder 16, and the interrupt control circuit 17 are connected to the system bus 13, respectively, and exchange addresses and data with each other via the system bus 13. In the following description, 2 or more 1
When a type of a building block is individually indicated, a subscript is added to a reference mark, and an arbitrary one of all building blocks is added.
When indicating one, a reference number is appended with a suffix n, and when all constituent blocks are collectively referred to, a suffix al is appended.

The shared memory 12 stores a program, which is an instruction sequence describing the operation contents to be executed by the processor 11, and data to be operated on (the source operand) of the instruction. The result (destination operand) is also stored. In particular, the shared memory 12 stores a program of a single branch processing routine described later and a program of a plurality of specific processing routines described later. All the processors 11n read an instruction from the shared memory 12 (instruction fetch), read data of the instruction to be operated on from the shared memory 12,
Interpretation and execution of the read instruction and writing of an operation result obtained by the instruction execution to the shared memory 12 are performed.

Since all processors 11al are connected to one system bus 13, all processors 11al
al shares a single physical address space. Shared memory 1
The access to the shared memory 12 from each processor 11n, such as reading instructions from the processor 2 and writing data to the shared memory 12, is performed via the system bus 13. The use of the system bus 13 by the processor 11n is determined by the right to use the system bus 13 (hereinafter, simply referred to as "right to use").
Is only possible while the The grant of the usage right to all the processors 11n is controlled by the bus arbiter 14.

When any single processor 11n needs to access the shared memory 12, the processor 1n
1n requests the bus arbiter 14 to grant a usage right prior to accessing the shared memory 12. The request for granting the right to use is made individually for each processor 11. The request for granting the right to use is continued until the processor 11n no longer needs to access the shared memory 12 irrespective of whether the right to use has been granted, and ends when the processor 11n no longer needs to access the shared memory 12. The bus arbiter 14 responds to a request for grant of usage right from at least one processor 11, preferably according to a predetermined bus priority, to one of all processors 11 currently requesting usage right. One processor 11
n, and grants the usage right to the selected processor 11n. The bus priority is a priority of use of the system bus 13 of each processor 11n, and is set, for example, for each processor 11n. The bus priority may be determined for each process that the processor 11n intends to execute with access to the system bus 13. Each processor 11n can access the shared memory 12 via the system bus 13 only while the usage right is granted. Thereby, access to the memory via the system bus 13 is always limited to any one of the processors 11al.

The memory decoder 16 is connected to the system bus 13
Responds to the physical address provided to the address bus within the
It controls transmission of instructions, data to be operated, and operation results to the data bus in the system bus 13. In the following description, data transmitted / received via the data bus is simply referred to as “data”. The physical address is stored in the shared memory 12
Not only storage elements such as memory chips 21 and 22 in the
It is also assigned to various other peripheral circuits connected to the system bus 13. The interrupt control circuit 17 controls a response of each processor 11n to the occurrence of an interrupt factor. The self-recognition circuit 15 determines whether or not the self-identification circuit 15
The processor 11n that is granting the right to use recognizes which of 1al.

The multiprocessor device 10 of the present embodiment
Are characterized by self-recognition of the processor 11n using the self-recognition circuit 15 and processing branches based on the self-recognition result. The self-recognition circuit 15 always holds the current individual grant status of the usage right to all the processors 11al. When the self-recognition processor 11n, which is any one of the processors, needs to recognize itself, it requests the self-recognition circuit 15 to notify the self-recognition circuit 15 of the granting state of the use right after obtaining the use right. The request for the notification of the grant status from the recognized processor 11n to the self-recognition circuit 15 is permitted only during a period in which the use right is granted to the recognized processor. The self-recognition circuit 15 is used for the recognized processor 11 to which the usage right is being granted.
In response to only the request from n, the current state of grant is notified to the recognized processor 11n. Recognized processor 11n
Recognizes that the processor to which the use right has been granted is the self in the use right grant state notified from the self-recognition circuit 15.

As described above, in the present embodiment, the multiprocessor 1 has a configuration in which a plurality of processors 11al share a single shared memory 12 and a single system bus 13.
At 0, the recognized processor 11n recognizes itself based on the status of granting the usage right to all the processors 11al. This is because, in the multiprocessor device, the right to use is always given only to the single processor 11n, and the processor capable of inquiring the grant state to the self-recognition circuit 15 is limited to the processor that is giving the right to use. This is because, at the time of inquiry, the processor to which the usage right is being granted and the recognized processor 11n whose inquiry state is to be inquired always match. This allows the recognized processor 11n to recognize itself based only on the usage right grant status, so that the processor 11n can recognize itself with an extremely simple configuration. Recognized processor 1
If 1n can recognize itself, the recognized processor can perform processing using the result of self recognition, for example, branch processing according to the result of self recognition.

The bus arbiter 14 preferably has a bus permission signal GN for which the signal state is determined for each processor 11 in accordance with the state of grant of the right to use the processor 11n for individual control of granting the right to use to all the processors 11al.
Tn is given to the processor 11n. In this case, the self-recognition circuit 15 includes an assignment state register 26 having bit cells 30n equal to or greater than the number N of all processors 11al. In addition, the self-recognition circuit 15 sends a bus permission signal G to each processor 11n to each bit cell 30n of the assignment state register 26.
It is designed so that NTn is given individually.

The assignment state register 26 stores all the processors 1
Create and hold data indicating the current individual grant status of the usage right to 1al. For this purpose, each bit cell 30n of the assignment state register 26 is provided with a bus enable signal GNT to the processor 11n associated with the bit cell 30n.
The state of n is latched and held. As a result, the assignment state data, which is data stored in the assignment state register 26, is represented by a bit string composed of bits equal to or more than the number of all processors 11al, and the state of the bit associated with each processor 11n is indicated by the bit string. The current grant status of the usage right to each processor 11n is shown. Since such grant status data indicates the current grant status of the usage right to all processors 11al, the grant status data uniquely represents the processor 11n currently granting the usage right. As described above, the self-recognition circuit 15 can generate the assignment state data only by latching the current state of the bus permission signal GNTal individually applied to all the processors 11al. It can be created very easily using the configuration.

The self-recognition circuit 15 responds to the notification request from the recognized processor 11n during the grant of the usage right, and transmits the state of all the bit cells 30n in the provision state register 26, that is, the provision state data to the recognized processor 11n. give. The recognized processor 11n can very easily recognize that the processor 11n uniquely granting the usage right uniquely indicated by the given grant status data is itself. Further, since the grant status data uniquely indicates the recognized processor 11n to which the usage right is being granted, the recognized processor 11n can be diverted as its own identification data. Thus, when the recognized processor 11n performs a process that requires self-identification, the assignment state data may be diverted as it is, so that the process is facilitated.

Preferably, the assignment status register 26 is connected to the system bus 13 and a predetermined physical address is assigned to the assignment status register 26. In this case, when viewed from each of the plurality of processors 11 ₁ to 11 _N,
The assignment status register 26 can be accessed from any processor 11n as the same physical address. In order for an arbitrary recognized processor 11n to obtain the grant status data in the grant status register 26 for self-recognition, it first requests the bus arbiter 14 to grant the usage right, and after granting the usage right, a predetermined number in the grant status register 26 is determined. The physical address is sent to the address bus of the system bus 13. In response to sending the physical address to the address bus, the memory decoder 16
Interpret the physical address sent to the address bus,
If the physical address is assigned to the assignment status register 26, the assignment status data stored in the assignment status register 26 is sent to the data bus of the system bus 13.

As described above, when the assignment status register 26 is connected to the system bus 13, the data transmission from the assignment status register 26 is controlled by the memory decoder 16. As a result, the processor 11n recognizes the assignment state register 26 as a part of the shared memory 12 and recognizes itself in the same procedure as a general memory access procedure performed via the system bus 13 and the memory decoder 16. It is possible to inquire the circuit 15 of the use right grant status.

If the grant status register 26 is connected to the system bus 13, the processor 11 must acquire the use right in order for the processor 11 to obtain data from the grant status register 26. by this,
The recognized processor 11n that inquires the self-recognition circuit 15 of the usage right grant status is replaced with the processor 11n that is granting the usage right.
Can always be limited to Further, only by the processor 11n performing a data read operation from the assignment state register 26 during the self-recognition process, the data in the assignment state register 26 is automatically converted to data indicating the processor 11n in response to the use right assignment to the processor 11n. Is rewritten. As described above, the assignment status register 26 stores the system bus 1
3, it is possible not only to access the assignment status register 26 in the same procedure as for the shared memory 12, but also to reliably obtain data that uniquely identifies itself without any special processing. Can be.

The multiprocessor device 10 shown in FIG. 1 specifically has two processors 11 ₁ and 11 ₂ , and each processor 11 ₁ and 11 ₂ has a central processing unit (hereinafter “CP
U "). FIG.
In the multiprocessor device 10, the shared memory 12
It includes an internal memory chip 21, an external memory chip 22, and an interface circuit 23 for the external memory chip. The internal memory chip 21 is directly connected to the system bus 13 and directly receives a chip select signal CS from the memory decoder 16. External memory chip 22
Are connected to the shared system bus 13 via the interface circuit 23 and the external system bus 13, and a chip select signal CS from the memory decoder 16 is input via the interface circuit. Each external memory chip 22 is connected to the external system bus 24 and the interface circuit 2.
3 and a configuration block connected to the shared system bus 13 via the shared system bus 13,
Send and receive addresses and data. In the example of FIG. 1, one internal memory chip 21 is realized by an On-Chip-ROM,
Each of the two external memory chips 22 is realized by a ROM and a RAM. The shared memory 12 is not limited to this.
Need only have at least one memory chip, and each of the external and internal memory chips 21, 22
May be realized by either a ROM or a RAM. In FIG. 1, a bus constituted by two or more signal lines is indicated by a thick line.

In the example of FIG. 1, each processor 11 ₁ , 11 ₂
Bus request signal REQ indicating the status of request for grant of usage right from
₁ and REQ ₂ are provided to the bus arbiter 14 from the _two processors 11 ₁ and 11 ₂ . Only while the bus request signals REQ ₁ and REQ ₂ from each processor are in the active state, each of the processors 11 ₁ and 11 ₂ requests the use right. Also, a bus permission signal GNT to each processor
₁ , while the GNT ₂ is in the active state, the right to use is given to each of the processors 11 ₁ and 11 ₂ and the system bus 13 can be driven. Also, the memory decoder 16
A chip select signal CSn for controlling data transmission to the data bus is individually given to all storage elements connected to the system bus 13 and to which physical addresses are assigned. The storage element described above is a shared memory 12
Not only each memory chip, but also the assignment state register 26. Further, memory decoder 16 has a strobe signal STB for controlling data reading from the data bus.
n is given to all the elements connected to the system bus 13 and capable of transmitting a physical address. Further, in the example of FIG. 1, the system bus 13 is a synchronous bus that operates according to a clock signal CLK output from a clock circuit in the CPU.

[0041] In the multiprocessor system 10 of FIG. 1, if the first processor 11 ₁ is required to access the system bus 13, the first processor 11 ₁ is in the active state of the bus request signal REQ ₁ self I do.
Similarly, if the second processor 11 ₂ is required to access the system bus 13, the second processor 11
₂ is a bus request signal REQ ₂ self active. The bus arbiter 14 according bus priority is predetermined, the processor of the processor 11 _1, 11 ₂ bus request signal is active, and selects one to be given the right to use, which is selected The bus permission signals GNT ₁ , GNT ₁ and GNT ₁ to each processor 11 ₁ and 11 ₂ are set so that only the bus permission signal GNTn to 11 n becomes active.
To control the GNT _2.

[0042] When the bus request signal REQ ₁ from one processor 11 ₁ is changed from the inactive state to the active state, the bus permission signal R to the other processors 11 ₂
If EQ ₂ is already active, preferably the bus arbiter 14 will send the new request processor 1
1 ₁ from the time of change of the bus request signal REQ ₁ until the end of the access to the shared memory 12 from another processor 11 currently being executed, the bus permission signal all processors GNTal
Wait for the state control, to control the status of the bus grant signal GNTal when other processors 11 _second access is terminated. As a result, a defect in the access being executed at the time of the new request for granting the usage right is prevented.

[0043] Upon selection of the processor 11n to be given the right to use the bus arbiter 14, it is higher towards the processor 11 ₁ of the new request priority, to cede from the processor 11 ₂ usage rights granted already in the processor 111 of the new request The bus request signal GNT of the processor of the new request
And ₁ to the active state, the bus grant signal GNT ₂ grants already processors inactive. As a result, the latter processor 11 ₂ access is stopped, can begin to access the shared memory 12 of the former processor 11 _1. If more grants already processor 11 ₂ is higher priority, while still maintaining, and bus grant signal assignment of the right to use the already processor GNT ₂ also active in the inactive state the bus permission signal GNT ₁ processor new requests keep. Consequently latter processor 11 _second access is continued. After the bus request signal REQ ₂ from the processor usage rights granted already is switched to the inactive state, the bus grant signal GNT ₁ of the former processor is switched to the active state.

[0044] when the processor selects, in addition to the processor 11 ₂ of the assignment of the right to use spent the processor 11 ₁ new requests, if there is one or more processors 11 of the assignment of the right to use waiting, of these three or more processors 11 Any one of the processors 11 having a higher priority is selected.

FIG. 2 is a block diagram showing the electrical configuration of the self-recognition circuit 15. FIG. 2 shows an example in which the number of processors in the multiprocessor device 10 is two. The self-recognition circuit 15 preferably further includes a delay circuit 27n for delaying the bus permission signal GTNn to each processor 11n, in addition to the assignment state register 26. Bus permission signal GNTn to each processor
Are supplied from the bus arbiter 14 to the delay circuit 27n.

The delay circuit 27n ideally shifts from the state in which the right to use the bus grant signal GTNn to any one of the processors 11n to the state in which the right to use is granted, that is, the timing of the bus permission signal GNTn. The bus grant signals GNTal to all the processors 11al are respectively delayed until the transition timing to the active state coincides with the timing at which address transmission from the processor 11n to the system bus 13 is actually enabled. Thereafter, the delay circuit 2
7n is referred to as a delayed bus permission signal Delayed-GNTn. Delayed bus permission signal Delay for the original bus permission signal GNTn
The delay time of ed-GNTn is variable. The delay time is
System bus 1 inside multiprocessor device 10
3 is controlled according to the state transition of the access to the shared memory 12 via the control unit 3.

Each bit cell 30 of the assignment state register 26
n is a delay bus permission signal Del from each delay circuit 27n.
The state of the aayed-GTNn is latched and held. The transmission of data from each bit cell 30n of the assignment state register 26 is controlled by an assignment state register chip select signal CSself supplied from the memory decoder 16. Specifically, data is transmitted from each bit cell 30n to the data bus only while the chip select signal is in the active state.

For this purpose, each bit cell 30n includes, for example, a D-type flip-flop circuit (hereinafter abbreviated as "FF") 31n and a tri-state buffer 32n for output control. The delayed bus permission signal Delayed-GNTn from the delay circuit 27n is supplied to the data terminal of the D-type FF 31n. The chip select signal CSself for the application state register 26 is supplied from the memory decoder 16 to the control terminal of the tri-state buffer 32n of each bit cell 30n. The clock signal CLK referred to by each component block of the multiprocessor device 10 is supplied to the clock terminal of the D-type FF 31n. D-type FF31n
Is supplied to the input terminal of the tristate buffer 32n. The level of the Q output signal of the D-type FF 31n corresponds to the state of the bit held in the bit cell 30n.

The D-type FF 31n of each bit cell 30n is
Each time a rectangular pulse of the clock signal rises, the delay bus enable signal Delayed-GNT of each processor 11n is output.
n is latched, and the latch result is output as a Q output signal. The level of the Q output signal of the D-type FF 31n is held until the rise of the next rectangular pulse of the clock signal CLK. As a result, the change timing of the Q output signal of the D-type FF 31n is synchronized with the rising of the clock signal. This is because the system bus of the multiprocessor device shown in FIG. 1 is a synchronous bus, and only the value at the edge of the signal waveform of the clock signal is significant. This is a circuit that controls whether to delay. Further, the D-type FF 31n outputs the clock signal CL
The signal can be delayed by one period of K. The output control tri-state buffer 32n outputs the D-type FF3 only while the chip select signal CSself is in the active state.
The 1n Q output signal is sent to the data bus.

FIG. 3 shows the multiprocessor device 10 of FIG.
It is a waveform diagram of various signals transmitted and received inside. Note that the description of FIG. 3 is an example where the number of processors 11 is two as shown in FIG. In FIG. 3, a signal that takes one of two states, an active state and an inactive state, is at a high level in the active state. Hereinafter, a memory access procedure in the multiprocessor device 10 of FIG. 1 will be described in detail with reference to FIG. Also, the description of FIG. 3 describes the memory access procedure in a situation where the right to use has not been granted to both processors 11 ₁ and 11 ₂ before time T1.

First processor 11₁In system
When access to the bus 13 becomes necessary, FIG.
Rise of the latest rectangular pulse P1 of the clock signal CLK
At time T1, the first processor 11₁But
When access to the system bus 13 is required, FIG.
The own bus request signal REQ shown in FIG.₁Active
Suppose that it was in the state. At time T1, as shown in FIG.
Second processor 11 shown _TwoBus request signal REQ from_Two
Is kept in an inactive state. Basua
The requester 14 receives the bus request signal REQ.₁Respond to changes in
And the bus request signal REQ of both processors₁, REQ_TwoThe ratio
Compare.

In order to use the system bus 13 efficiently, the selection of the processor 11n to which the usage right is granted is preferably performed each time a request for the usage right from any one of the processors 11 is started. More preferably,
It is also performed each time the usage right request from any one of the processors 11 ends. In the example of FIG.
When at least one of the bus request signals from 1al changes state, the processor 11 is selected. In the example of FIG. 3, the bus request signal RE of the first processor
Since only Q ₁ is active state, the first processor 11 ₁
Select switches only bus grant signal GNT ₁ to the first processor of FIG. 3 (D) in the active state, FIG. 3 (E)
Bus grant signal GNT ₂ to the second processor is kept in the inactive state.

The first rectangular pulse P of the clock signal CLK
At time T2 is one falling, the first processor 11 ₁ obtains the status of the bus grant signal GNT ₁ to self. Since the bus permission signal GNT ₁ to the first processor is in the active state, the first processor 11 ₁ knows that it may use the system bus 13. Thus, as shown in FIG. 3 (F), consisting of a first processor 11 ₁ to allow delivery of the physical address to the address bus A31-A0.

For example, an access control signal AC shown in FIG. 3 (G) is derived from a control bus included in the system bus. The access control signal AC is transmitted to the shared memory 12
Shows the status transition of access to. Access control signal AC
Indicates at least in each cycle of the clock signal CLK whether or not there is an access being continuously executed and, if there is an access being continuously executed, whether or not the access is completed within the cycle. Each processor 11n determines whether or not access by another processor has been completed based on the access control signal AC at each clock cycle after the bus permission signal GNTn for itself has shifted to the active state.
After completion, the address is actually sent to the address bus. In the example of FIG. 3, the first processor 11 ₁ outputs the clock signal C
The drive of the address bus is started at time T3, which is the rise of the rectangular pulse P2 next to LK.

Bus permission signal GN in delay circuit 27n
The delay time of Tn is also controlled by, for example, an access control signal. At the timing when the bus permission signal GNTn to any one processor 11n shifts to the active state, if any of the remaining processors 11 is accessing the shared memory 12, the total delay circuit 27al
Until the current access is completed.
NTal is respectively delayed. Each bit cell 30n of the assignment state register 26 latches the delayed bus enable signal Delayed-GNTn output from the delay circuit 27n every time the rectangular pulse of the clock signal CLK rises, and latches the latched result until the rise of the next rectangular pulse. Hold.

In the example of FIG. 3, the bus permission signal GNTn to the processor to be given is delayed by one clock cycle in the D-type FF 30n in the assignment state register 26. FIG.
Since the chip select signal CSself to the self-recognition circuit 15 shown in (I) and the strobe signal STBn to the given processor shown in FIG. 3 (J) change at the timing shown in FIG. The delay time of GNTn is sufficient to be delayed by the D-type FF 30n, and the bus permission signal GNTn need not be further delayed by the delay circuit 27n. If the access to the self-recognition circuit 15 is slow and needs to be delayed by another clock cycle, the bus permission signal GNTn is delayed by the delay circuit 27n.

FIG. 3H shows the bit cell 3 of the first bit.
0 _1, the delayed bus enable signal D of the first processor 11 ₁
elayed-GNT ₁ latch result, i.e. a waveform diagram showing a D-type FF 31 ₁ Q output for the first processor. In the example of FIG. 3, the access by another processor 11 has already been completed at the rising time T1 of the first rectangular pulse of the clock signal, or another access is made within one period of the clock signal CLK from the rising time T1. that the access by the processor 11 is completed, since it is notified by the access control signal AC, the delay time in the delay circuit 27 ₁ is less than the period of the clock signal CLK, the next rising time of the rectangular pulse P2 of the clock signal CLK At T3, the delay bus permission signal Dela
Yed-GNT ₁ has already transitioned to the active state. As a result, in FIG. 3, the change in the latch result of each bit cell 30n is delayed by one cycle of the clock signal CLK from the original bus permission signal GNTn.

As shown by a two-dot chain line in FIG. 3F, at the rising time T1 of the first pulse, the access by another processor 11 is continued, and one cycle of the clock signal from the rising time T1. If the access completion is not notified within the period, the delay time increases by an integral multiple of the clock signal period until the access completion is notified. As a result, as shown by a two-dot chain line in FIG. 3H, the change of the latch result of each bit cell 30n is delayed by an integer multiple of the clock cycle from the original bus enable signal GNTn.

The physical addresses sent to the address buses A31-A0 are input to the memory decoder 16. The memory decoder 16 interprets the physical address input from the address bus A31-A0, and changes only the chip select signal CSn of the storage element to which the physical address is assigned to an active state instructing data transmission. The chip select signal CS is kept in an active state for a predetermined period, for example, one cycle or more of the clock signal. Further, the memory decoder 16 once shifts the high state strobe signal STBn given to the processor 11n that has sent the input physical address, that is, the processor 11n to which the usage right is being granted, to the low state.
The strobe signal STBn is shifted to a high state before any one of the chip select signals CS changes to an inactive state. In the strobe signal STBn, the rising edge of the signal waveform is the active timing.

It is preferable that the timing at which the strobe signal STBn to the processor 11n during the grant of the use right returns to the high state is closer to the timing at which the chip select signal CSn in the active state returns to the inactive state. Most preferably, immediately before returning to the state. As a result, the processor 11n during the grant of the usage right can read the data after the data on the data bus is sufficiently stabilized.

FIG. 3I is a waveform diagram of the chip select signal CSself to the assignment state register 26.
(J) is a waveform diagram of a strobe signal STBn to the processor 11n during use right grant. In the example of FIG. 3, the memory decoder 16 is, for example,
1n, after the time when the access is enabled, the rising edge T1 of the latest rectangular pulse P11 immediately after interpreting the physical address.
In response to 1, only the chip select signal CSn of the storage element to which the physical address is assigned is changed to the active state. Further, in response to the falling edge T12 of the latest rectangular pulse P11 immediately after the interpretation of the physical address, the memory decoder 16 shifts the strobe signal STBn to the processor 11n under the right to use to the low state, and In response to the falling T14 of P12, the strobe signal STBn is returned to the high state. In this case, the strobe signal STBn is the chip select signal C
Sn is kept in a low state for a shorter period than a predetermined period in which it is kept in an active state. This makes it possible to return the strobe signal STBn to the high state before the chip select signal CSn returns to the inactive state.

If the physical address input to the address bus A31-A0 is allocated to the shared memory 12, any one of the memory chips in the shared memory 12 is input to the memory chip from the address bus A31-A0. At least a part of the physical address is obtained as an address in its own storage area, and in response to the change of the chip select signal CSn given to itself to the active state,
The data described at the acquired address in its own storage area is transmitted to the data bus. The processor 11n during the grant of the usage right gives the strobe signal STB given to itself.
In response to the change of n to a high state, the data sent from the memory chip to the data bus is latched.

If the input physical address is assigned to the assignment status register 26, the assignment status register 26
Is the chip select signal CSself given to itself.
In response to the change to the active state, the data consisting of the bits currently held by all the bit cells 30n of the assignment state register 26 is transmitted to the data bus. In response to the change of the strobe signal STBn applied to itself to the high state, the processor 11n that is granting the usage right latches the data sent from the grant state register 26 to the data bus.

The processor 11n during the grant of the use right can recognize itself according to the latched bit string. For example, the bus grant signal D to the first processor after the delay in the lowest bit cell 30 ₁ of the granted status register 26
elayed-GNT ₁ is given, the bus grant signal the Delayed-GN to the second processor after a delay from the lowest applied state register 26 to the second bit cell 30 ₂
If T ₂ is self-recognition circuit 15 is designed in the configuration given processor 11n in assignment of the right to use, the lower 2 bits of data from the applied state register 26 is "01"
If it is, it is the first processor 11 ₁ and the lower 2
If the bit is “10”, the self is the second processor 11 ₂
It turns out that it is.

[0065] In the first processor 11 ₁ in the assignment of the right to use, if there is no more need to occupy the system bus 13, at the rising time T21 is the latest of the rectangular pulse P21 of the clock signal CLK after the occupation reasons eliminated, self Of the bus request signal REQ ₁ is returned to the inactive state.
The bus arbiter 14, in response to the change of the bus request signal REQ ₁ from the first processor, said bus request signal RE
Check the Q _1, since the bus request signal REQ ₁ is returned to the inactive state to return the bus grant signal GNT ₁ from the first processor to the inactive state.

[0066] The clock signal at the time T22 is the fall of the rectangular pulse P21 occupation reasons after eliminating the initial CLK, the first processor 11 ₁ bus grant signal G to self
To obtain the status of NT _1. Since the bus permission signal GNT ₁ to the first processor is in an inactive state, the first processor 11 ₁ knows that the right to use is no longer given to itself. As a result the first processor 11 _1, the rise in a time T23 after the next rectangular pulse P22 of the clock signal CLK, and stops driving of the address bus A31-A0. This comprises a first processor 11 ₁ to impossible delivery address to the address bus A31-A0.

The reason for delaying the bus permission signal GNTn is as follows.
Based on the following reasons. The bus request signal REQn and the bus permission signal GNTn are signals for the processor 11n to negotiate with the bus arbiter 14. The signal on the address bus in the system bus 13 and the signal on the data bus in the system bus 13 are signals for communication between the negotiated processor 11n and peripheral circuits of the processor 11n. The processor 11n is designed to operate accurately in accordance with the timing based on the bus permission signal GNTn.

At the time of communication between the processor 11n and the peripheral circuit, first, the processor 11n that wants to exchange data with the peripheral circuit via the system bus 13 uses the bus request signal REQn and the bus permission signal GNTn to transmit the data to the bus arbiter 14. It is necessary to perform negotiation according to the above-described procedure and have the bus arbiter 14 grant the right to use the system bus 13. After such a so-called bus master is selected, the processor 11n to which the right to use is assigned drives the address bus, and the memory decoder 16 selects a bus slave which is a peripheral circuit of a communication partner, and as a result, the peripheral selected as the bus slave The circuit and the processor 11n can communicate with each other. As a result, the actual data exchange start timing between the processor 11n and the peripheral circuit is later than the change timing of the bus permission signal GNTn.

As can be seen from a comparison between FIG. 3D and FIG. 3J, prior to the rising timing of strobe signal STBn indicating the data reading timing of a certain processor 11n, the bus permission to the processor is made at timing T13. Since the signal GNTn has returned to the inactive state, the processor 11n cannot recognize itself even if the bus permission signal GNTn is returned to the processor via the self-recognition circuit 15 as it is. Therefore, the self-recognition circuit 15 delays the bus permission signal GNTn by at least one clock cycle, and keeps the bus permission signal GNTn in a state indicating that the usage right is being granted until after the rising timing of the strobe signal STBn. As a result,
Assigned processor 11 output from self-recognition circuit 15
n is accurately returned to the grant processor 11n, so that the grant processor 11n
n enables accurate self-recognition.

For the above reason, the delay circuit 27n delays the bus enable signal GNTn before being latched by each bit cell 30n of the assignment state register 26. As a result, the change timing of the data indicating the usage right grant status held in the grant status register 26 is determined by the
No. 3 is corrected so as to coincide with the change timing of the actual use situation. Therefore, the change in the state of the signal from each bit cell always coincides with the actual use state of the system bus 13.

The multiprocessor device 10 preferably further includes a cache memory 28n and a cache controller 29n for each processor 11n, as shown in FIG. 1, in order to cause a plurality of processors to perform parallel operations. . For each processor 11n, the processor 11
n and the cache controller 29n for the processor may be integrated on a single semiconductor chip, and the cache memory 28n of the processor may also be integrated on the semiconductor chip. Processor 11n
Each time, the processor 11n accesses the system bus 13 by the cache controller 29 for the processor.
n. The processor 11n itself,
It is not known whether the next data to be obtained is in the cache memory 28n or only in the shared memory 12. The cache controller 29n accesses the shared memory 12 via the system bus 13 or determines whether the cache memory 28
Switching between reading data and the like from n.

In the above case, the instructions read from the shared memory 12 by each processor 11n and the data to be operated on are also stored in the respective cache memories 28n. When reading data, each processor 11n first accesses its own cache memory 28n. When an instruction and data requested by the processor 11n exist in the cache memory 28n for the processor 11 (hit), such as when fetching an instruction already stored in the cache memory 28n for the processor 11, the processor 1
The processor 11n keeps the bus request signal REQn in an inactive state without making it active, since it is sufficient that 1n directly accesses the cache memory 28n via the cache controller 29n. The data requested by the processor 11n is stored in the cache memory 28 for the processor.
n (miss hit), the shared memory 12
, The processor 11n sets the bus request signal REQn to an active state. If the next instruction requested by the processor 11n hits the cache memory 28n, the processor 11n returns the bus request signal REQn to the inactive state because the system bus 13 does not need to be occupied.

As long as the processor 11n is operating, the processor 11n needs to keep fetching the program. Therefore, if the plurality of processors 11n are not provided with the cache memory 28n and the cache controller 29n, respectively, Processor 11al
Cannot operate in parallel at all. Therefore, in order to operate a plurality of processors 11al in parallel, each processor 11al
n need to be provided with a cache memory 28n and a cache controller 29n, respectively. As a result, while any one processor has a cache hit, the other processor can operate. As described above, when the cache memory 28n is prepared for each processor 11n, each processor 11n only needs to access the system bus 13 when there is a mishit in the cache memory 28n. ) Becomes possible.

The multiprocessor device 10 shown in FIG. 1 is further characterized by a process branch involving a self-recognition process. For this purpose, basically, the shared memory 12 stores a plurality of predetermined processing programs of specific processing routines, and each specific processing routine is individually assigned to the processor 11n. Prior to reading the program, the arbitrary processor 11n requests the bus arbiter 14 for a usage right, and requests the self-recognition circuit 15 to notify the status of the usage right after the usage right is granted. After the notification of the grant status, the processor 11
n recognizes itself based on the notified use right grant status, reads a program of a specific processing routine assigned to the recognized self processor from the shared memory 12 via the system bus 13, and Start execution.

As described above, when the multiprocessor 10 has the self-recognition circuit 15 and the processor 11 performs the self-recognition prior to reading the program of the specific processing routine from the shared memory 12, the processor 11 allocates itself. The program of the specified processing routine can be executed. As a result, a plurality of specific processing routine programs stored in the shared memory 12 can be individually assigned to each processor 11 and executed, and a different program can be activated for each processor 11.

The processing branch with self-awareness is preferably
Used in an exception handling routine that is a processing routine executed in response to the occurrence of an exceptional event. Exception event (ex
“ception” is a trigger event for executing a function of forcibly interrupting a currently executing program and forcibly branching to a predetermined address. As exceptional events,
For example, a software interrupt, an interrupt request (IRQ: interrupt request) from the outside to the processor, reset of the multiprocessor device 10, abort of instruction and data (abort), fetch of undefined instruction, fast interrupt request (FIQ: fast interrupt) request).
Hereinafter, a physical address that is predetermined to be accessed by the processor 11n in response to the occurrence of an exception event is referred to as an exception activation address. When two or more exceptional events are set, an exception activation address is set for each exceptional event.

The association between the exception event and the exception activation address is fixedly set, for example, as a processor specification. Particularly, when a single-specification processor is mass-produced, the exception activation addresses of the produced processors are equal to each other. When the multiprocessor device 10 of FIG. 1 is configured by using a plurality of processors having the same exception activation address, all the processors 11al
Are connected to the system bus 13 so that all processors 11al share a single physical address space.
All of the processors 11n access the same exception activation address after acquiring the right to use in response to the occurrence of the exception event. For this reason, it is difficult for the multiprocessor having the above configuration to execute mutually different processing routines for each processor when an exception event occurs.

When the multiprocessor 10 of FIG. 1 is configured using a plurality of processors having the same exception activation address, preferably, a program for a branch processing routine for branching the exception processing according to the processor is provided. , And the shared memory 12. In the storage area of the shared memory 12, the start address of the program of the branch processing routine is equal to the exception start address, or a jump instruction to the start address of the program of the branch processing routine is described in the interrupt exception address. The start address of the program is a head address of a portion where the program is described in the storage area of the shared memory 12. The program of the branch processing routine is a program for causing the processor 11n, which is in the process of granting the usage right and reading out the program from the shared memory, to execute the above-described operation at the time of occurrence of the exceptional event. Specifically, the program of the branch processing routine includes a request for notifying the self-recognition circuit 15 of the current grant status of the usage right, a self-recognition based on the notified grant status of the usage right, and The processor 11n reads the program of the individual processing routine and starts execution.

As described above, if the above-mentioned branch processing routine program is stored in the storage area of the shared memory 12 with the exceptional activation address at the top, all processors 11
al exception start addresses are equal to each other,
Different programs can be activated for each processor 11. Thereby, the multiprocessor device 1
0 indicates that a different program can be executed for each processor 11n even when the processors 11n share a single physical address space and the exception activation addresses of the processors 11n are equal to each other.

FIG. 4 is a flowchart for explaining in detail an interrupt processing routine which is one of the exception processing routines. When an external or internal interrupt event occurs in the multiprocessor device, an interrupt signal is provided to the interrupt control circuit 17. Thus, the process proceeds from step S0 to step S1. In step S1,
The interrupt control circuit 17 determines, based on the type of the interrupt event, which of the processors 11al the generated interrupt event is an interrupt event for. The interrupt control circuit 17 interrupts the processor 11n by giving an interrupt signal to one of the processors 11n selected as a result of the determination.

In step S2, any one of the processors 11n that has received the interrupt jumps to an interrupt activation address which is a predetermined exception activation address associated with the interrupt event. That is, the processor that has received the interrupt (hereinafter referred to as “interrupted processor”) 11n
First responds to the interrupt by requesting the bus arbiter 14 for a use right, and after the use right is granted, sends a predetermined interrupt activation address to the address bus A31-A0. As a result, the memory decoder 16 causes the data described in the interrupt activation address in the shared memory 12 to be transmitted from the shared memory 12 to the data bus. In step S3, the interrupted processor 11n sets the interrupt processing branch processing routine program. Can be sequentially executed from the beginning. The interrupted processor 1
In 1n, if another process is being executed at the time of receiving the interrupt signal, the other process is interrupted, and after the interrupt, the process jumps to the interrupt activation address.

In step S3, the interrupted processor 11n sets the assignment state register 2 in the self-recognition circuit 15
6 is read, and based on the data obtained as a result of the read, the self recognizes one of the processors 11al by the procedure described with reference to FIGS. That is, the interrupted processor 11n sends out the predetermined physical address assigned to the assignment status register 26 to the address bus A31-A0 because the usage right has already been assigned at the time of reading the register in step S3. This causes the memory decoder 16 to change the assignment state register 26
Of the chip select signal CSself in the active state, the assignment state register 26 sends the stored data to the data bus. Since the use right has already been given to the interrupted processor 11n at the time of reading the register in step S3, the data in the assignment status register 26 is data uniquely indicating the interrupted processor 11n. The interrupted processor 11n latches the data sent to the data bus, and recognizes that the processor uniquely represented by the latched data is itself.

After self-recognition, the interrupted processor 11n
Jumps to the start address of the processing routine assigned to the recognized own processor. That is, the interrupted processor 11n selects the recognized start address of the processing routine assigned to its own processor 11n from the start addresses of the specific processing routines assigned to all the processors 11al prepared in advance. Then, the selected start address is stored in the address bus A3.
1-A0. Thereby, the memory decoder 16
Causes the data described at the selected start address in the storage area of the shared memory 12 to be transmitted to the data bus.
In steps S4 and S5, the interrupted processor 11
Can sequentially execute the instructions described in the specific processing routine program assigned thereto from the beginning.

For example, as shown in FIG.
The server device 10 has two processors 11 ₁, 11_TwoPlace with
In this case, as a result of self recognition,₁In
Then, if the interrupted processor recognizes, the process proceeds to step S3.
Then, the process proceeds to step S4 and the first processor 11₁Assigned to
The execution of the specified processing routine is started. Self is first
2 processors 11_TwoIs recognized by the interrupted processor
Then, the process moves from step S3 to step S5 and the second
Processor 11_TwoOf the specific processing routine assigned to
Start a line. At the interrupted processor 11n
Execution of the specific processing routine assigned to
If so, the interrupt processing routine ends in steps S6 and S7.
I do.

As described above, the multiprocessor device 10 of FIG. 1 uses the self-recognition circuit 15 to execute the processing executed when an interrupt event occurs even if the physical address spaces of all the processors 11al are the same. Can be switched for each processor 11. Even when another exception event such as a reset occurs, the same switching can be performed if the processor 11 that has received the signal accompanying the occurrence of the exception event performs the processing of steps S2 to S6.

As described above, each processor of the multiprocessor device shown in FIG. 1 performs the self-recognition using the self-recognition circuit only once in the branch processing routine immediately after the occurrence of the exceptional event. The programs of the specific processing routines assigned to the respective processors are arranged at mutually different physical addresses in the shared memory. Each processor individually stores the address to be accessed next by its own internal program counter, etc., so while each processor is executing the specific processing routine assigned to itself, You don't have to worry about it. Therefore, since the time for occupying the system bus for self-identification is extremely short, the self-identification processing has almost no effect on other processing that requires access to the memory.

As described above, when a plurality of processors connected to a single system bus share a memory connected to the system bus, the following effects can be obtained. As disclosed in Japanese Patent Application Laid-Open No. 8-263460, if a system bus to which the processors are connected is separated for each processor, a plurality of processors need to communicate with each other in order to share data. Data sharing procedures are complicated. Further, as the amount of shared data increases, the load of inter-processor communication increases, so that it becomes more difficult to share data as the data amount increases. If a plurality of processors 11al are connected to the single system bus 13 as shown in FIG. 1, a single physical address space is shared by the plurality of processors 11al. Therefore, if the shared memory 12 is connected to the shared system bus 13, the plurality of processors 11 can share data only by accessing the same physical address.
The data sharing procedure becomes extremely easy. The plurality of processors 11al and the shared memory 12 are connected to a single system bus 13
In this configuration, communication between processors for data supply is not required, so that a load does not increase due to an increase in the amount of data, so that data sharing is easy.

FIG. 5 is an ASIC (Application Specific Int.) For a mobile phone using the multiprocessor device of FIG.
2 is a block diagram illustrating a configuration of an egrated circuit. Of the constituent blocks of the ASIC of FIG. 5, those corresponding to the constituent blocks of the multiprocessor device of FIG. 1 are denoted by the same reference numerals. The multiprocessor device in the ASIC in FIG. 5 includes two CPUs connected to a common system bus 13 as the processor described in the present invention. In addition, the ASIC includes a DSP for performing audio compression and the like, which are connected to a bus different from the common system bus 13.

The multiprocessor device inside the ASIC of FIG.
Two processors 11 ₁, 11_TwoOne of
Processor 11₁Is a communication protocol for mobile phones
Processor 11_TwoIs multimed
Used for processing related to the data. These two processors
11₁, 11_TwoAre connected to a common system bus 13
Connected directly or indirectly to the system bus.
The shared memory 12 is shared. On the other hand, processor 11₁
The other processor by communication controlled protocol
11₁Is given to the shared memory 12.
And the other processor 11_TwoWill also be shared.

Since the amount of data used for multimedia-related processing is relatively large, two processors 1
1 _1, 11 ₂ can be difficult to share the data with inter-processor communication. As described above, in the configuration of the multiprocessor device of FIG. 1, only the two processors access the physical address of the shared memory 12 storing the data, and the two processors easily share the data. be able to. Thus, in the mobile phone with a built-in ASIC, whereas the data provided by the communication protocols are controlled by the processor 11 _1, be used for multimedia related processing in the other processor 11 _2, is facilitated.

In the ASIC of FIG. 5, if the multiprocessor device performs exception processing including the branch processing routine described with reference to FIG. The specific process assigned in advance can be executed in response to the occurrence of the exceptional event. As a result, even if a plurality of built-in processors have the same standard specification and model number, and therefore have the same exception activation address, processing branching can be performed for each processor. This facilitates mass production of multiprocessor devices. The part of the exception handling routine that performs branch processing needs to be code that can be commonly executed by all processors 11al. That is, all the processors 11al may be realized by different types of processors, but the instruction codes of the different types of processors must be completely equal to each other. That is, all processors 11al have a so-called binary compatible configuration. For example, at a minimum, all processors 11al need to be processors of the same family of a single manufacturer. When all the processors 11al that satisfy such conditions are realized by one type of processor, there is an advantage that the cost can be reduced because only one license fee is required.

The multiprocessor device 10 of the present embodiment
Is an example of the multiprocessor device of the present invention, and can be realized in other various forms as long as the main configuration and operation are the same. In particular, the detailed configuration and operation of each constituent block of the multiprocessor device 10 are not limited to the above-described configuration and operation, and may be realized by another configuration and operation as long as the same effect is obtained.

[0093]

As described above, according to the present invention, in a multiprocessor device having a configuration in which a plurality of processors share a memory and a system bus, the self-recognition circuit determines the current assignment status of the right to use to all processors. , And notifies the processor to which the usage right is being granted. The processor to which the usage right is being granted recognizes that one of the processors to which the usage right has been granted is the self at the time of the notification, based on the notified grant status. This makes it possible for each processor to perform self-recognition using a very simple configuration in the multiprocessor device.

Further, according to the present invention, the current state of the bus permission signal given to each processor for controlling the grant of usage right to each processor is latched in each bit cell of the grant state register provided in the self-recognition circuit. Then, the latch results of all the bit cells are used as data indicating the status of granting the usage right to all processors. Thus, the self-recognition circuit can easily and extremely easily create data indicating the current grant status of the usage right to all processors.

Still further, according to the present invention, a predetermined physical address is previously assigned to the assignment status register, and the assignment status register is connected to the same system bus as the processor. As a result, the recognized processor can acquire data uniquely indicating itself only by accessing the assignment state register in the same procedure as a general procedure for accessing a memory.

Further, according to the present invention, in the multiprocessor device, the state transition timing of the bus permission signal accompanying the grant of the use right is changed until the timing at which the address transmission from the processor with the new use right is actually enabled becomes coincident.
The bus grant signal from the bus arbiter is delayed, and the state of the delayed bus grant signal is latched in the grant status register. This prevents a self-recognition error of the processor due to the difference between the two timings.

Further, according to the present invention, after granting the right to use the system bus, the processor performs self-recognition using the self-recognition circuit before reading the program from the shared memory. As a result, different programs can be activated for each processor. Further, according to the present invention, if predetermined physical addresses to be jumped when an exceptional event occurs in all the processors are equal to each other, a branch processing routine program is stored in advance in a portion starting from the physical address in the memory. ing. The branch processing routine program causes the processor that is granting the right to use the self-recognition processing and the reading of the specific processing routine program assigned to the recognized self. Thereby, even when a plurality of processors share a single physical address space and the physical addresses for the exception activation of each processor are equal to each other, the multiprocessor device differs from processor to processor when an exception event occurs. The program can be started and executed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a multiprocessor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a self-recognition circuit in the multiprocessor device of FIG. 1;

FIG. 3 is a timing chart showing signal waveforms transmitted and received inside the multiprocessor device of FIG. 1;

FIG. 4 is a flowchart illustrating an interrupt processing routine in the multiprocessor device of FIG. 1;

FIG. 5 is an ASIC using the multiprocessor device of FIG. 1;
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 6 is a block diagram illustrating a configuration of a conventional multiprocessor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Multiprocessor apparatus 11 Processor 12 Shared memory 13 System bus 14 Bus arbiter 15 Self-recognition circuit 16 Memory decoder 17 Interrupt control circuit 26 Assigned state register 27 Delay circuit 28 Cache memory 29 Cache controller 31 D-type FF 32 Tri-state buffer for output control

Claims (6)

[Claims] A plurality of processors, a memory, a system bus, and a bus arbiter, wherein all the processors and the memory are connected to the system bus, and the bus arbiter grants a right to use the system bus to any one of the processors;
In a multiprocessor device in which only the processor to which the usage right is granted accesses the memory via the system bus, the current grant status of the usage right to all the processors is responded to a request from the processor to which the usage right is being granted. A self-recognizing circuit for notifying the processor, wherein the processor that is granting the right to use is determined to have been granted the right to use based on the state of grant of the right of use notified from the self-recognizing circuit. A multiprocessor device, which recognizes that the user is self. 2. The self-recognition circuit includes an assignment status register holding data indicating a current assignment status of the usage right to all of the processors. A bus permission signal whose state is determined according to the grant state of the processor is given to the processor and the bit cell associated with the processor in the grant state register. Each bit cell of the grant state register is assigned to each bit cell. The present state of the bus permission signal to the associated processor is latched and held, and the self-recognition circuit responds to a request from the processor to which the usage right is being granted, and stores all the data in the grant state register. 2. The multiprocessor device according to claim 1, wherein a state of the bus permission signal stored in the bit cell is notified to the processor. Place. 3. A self-recognition circuit, further comprising a memory decoder that responds to a physical address given to an address bus in the system bus and controls transmission of data to a data bus in the system bus. A grant status register holding data indicating a current grant status of the use right to a processor, wherein a memory decoder and a grant status register are connected to the system bus; A predetermined physical address previously assigned to the assignment state register is sent to the address bus. 3. The multiprocessor device according to claim 1, wherein the data is transmitted to a data bus. 4. The self-recognition circuit further includes a delay circuit for delaying a bus grant signal to each processor provided from a bus arbiter, and providing the delayed bus grant signal to each bit cell of a grant status register. Until the change timing of the bus grant signal from the unlicensed state to the licensed state is coincident with the timing at which the processor to which the bus grant signal is given can actually send an address to the system bus. 4. The multiprocessor device according to claim 3, wherein a bus permission signal provided from the bus arbiter to the self-recognition circuit is delayed. 5. The memory stores a program for a predetermined specific processing routine individually assigned to each of the processors. The processor requests: (1) the bus arbiter for the use right; 2) After the use right is granted, the self-recognition circuit requests the self-recognition circuit to notify the use right grant state. (3) A specific processing routine assigned to its own processor recognized based on the notified use right grant state The multiprocessor device according to any one of claims 1 to 4, wherein the program is read from the memory via the system bus and the program is executed. 6. Each of the processors requests the bus arbiter for the use right in response to the occurrence of a predetermined exception event, and after the use right has been granted, a predetermined exception activation physical in the memory via the system bus. When the address is accessed to execute the instruction described in the activation address, and the physical addresses for exception activation of all the processors are equal to each other, the memory branches the processing at the time of exception activation. The program further stores a branch processing routine program for executing the program, wherein the start address of the branch processing routine program in the memory is equal to the physical address for activating the exception.
Requesting the self-recognition circuit to be notified of the current grant status of the use right, and reading a program of an individual processing routine for its own processor that is recognized based on the notified grant status. The multiprocessor device according to claim 5, wherein