JP2001256179A - Processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor system based on PCI bus specifications. SOLUTION: In the configuration registers 61 and 71 of bus slaves 6 and 7, a delay cycle number is stored corresponding to required memory space and I/O space. The delay cycle number is the time required after a transaction is received from a bus bridge 5 until data transfer becomes possible. A host bridge 3 reads the delay cycle number of the bus slaves 6 and 7 in a configuration cycle and stores it in the configuration register 31 as a delay cycle table. When the host bridge 3 issues the transaction, a delay cycle counter 32 starts counting the pertinent delay cycle number and the same transaction is reissued when the delay cycle number is counted up.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor system, and more particularly, to a PCI (Peripheral Computer).
ent Interconnect) bus.

[0002]

2. Description of the Related Art A PCI bus is a clock-synchronous bus that is standardly employed in personal computers, and is employed as a system bus for controllers of personal computers and industrial embedded devices.

In a processor system employing a PCI bus, the number of devices that can be connected to one PCI bus is limited due to the electrical specifications of the PCI bus (limitation of load capacity). Therefore, two PCI buses and a PCI-P for mutually transmitting transactions between the two buses
By providing a CI bridge, the processor system P
It is possible to increase the number of PCI devices that can be connected to the CI bus. Hereinafter, the PC near the main processor
The I bus is called a primary PCI bus, and is a PCI-PCI
The opposite PCI bus separated by the bridge is called a secondary PCI bus.

Further, by separating the primary PCI bus and the secondary PCI bus by a PCI-PCI bridge, concurrent processing in which separate data transfer is simultaneously performed on two PCI buses becomes possible, and higher system throughput can be obtained. It becomes possible.

However, for example, when the bus slave device on the secondary PCI bus is a low-speed device, the bus master device on the primary PCI bus is PCI-P.
When accessing a bus slave device on the secondary PCI bus via the CI bridge, the secondary P
Data transfer between the PCI-PCI bridge and the bus slave device performed on the CI bus may take a very long time. In such a case, the primary PCI bus remains occupied by the bus master device until data transfer on the secondary PCI bus is completed,
This reduces the transfer efficiency of the primary PCI bus, and significantly lowers the performance of the entire system.

To solve this problem, a technique called "delayed transaction" is used. Hereinafter, the mechanism of the delayed transaction will be described.

When a bus master device on the primary PCI bus attempts to access a bus slave device on the secondary PCI bus via the bus bridge, the bus bridge firstly requests the bus master device for the requested contents (target address to be accessed, command , Data, etc.) in the internal delayed transaction queue and return a retry response to the bus master device.

[0008] Upon receiving the retry response, the bus master
The primary PCI bus is once released, and after a lapse of a predetermined time, the right to use the primary PCI bus is acquired again to execute the same access again. During this time, the bus bridge device transfers the access requested by the bus master device to the secondary P.
Executes on the CI bus and completes write / read access to the bus slave device. In the case of read access, the bus bridge stores data read from the bus slave device in an internal delayed transaction buffer. The bus bridge keeps returning a retry response to the reaccess request from the bus master device until the access to the bus slave device is completed.

When the bus bridge completes the bus slave access on the secondary PCI bus, the bus bridge returns a data transfer response on the primary PCI bus in response to the re-execution of the transaction by the bus master device. Access to the bus slave device is completed.

However, in the above-described delayed transaction system, immediately after receiving the retry response, the bus master device acquires the right to use the primary PCI bus to execute the transaction again. Therefore, as long as the access to the bus slave device on the secondary PCI bus is not completed, the bus bridge continuously returns a retry response to the bus master device, so that the bus master device returns to the primary PCI bus.
The bus will be occupied for a long time.

Therefore, as a conventional example of setting a waiting time before retrying a transaction, Japanese Patent Laid-Open No.
There is a “computer system and bus transaction control method” described in Japanese Patent Application Publication No. 269169. In this conventional example, a method of estimating a waiting time (delayed time) is used in a delayed time generation circuit provided in a bus bridge. The estimated waiting time is determined by the command / retry response during the transaction retry response.
The bus master device is notified using a byte enable signal or a sideband signal.

[0012]

However, the above conventional example has the following problems.

First, since a delayed time table and a delayed time generation circuit used for predicting the delayed time are provided in the bus bridge, a bus bridge designed in the past or a general-purpose bus bridge conforming to the PCI bus specification is used. No, it needs to be redesigned.

Also, in order to notify the bus master device of the waiting time, signals not specified in the PCI bus specifications, such as command / byte enable signals and sideband signals, are used. Not compliant.

Also, since only bus access via a bus bridge is considered, the present invention is not applicable when a bus master device performs a bus access to a bus slave device existing on the same bus as a bus master device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce the issue of useless transactions due to retries and to prevent a decrease in throughput of a bus to which a bus master device is connected. To provide a processor system that can

Another object of the present invention is to provide a processor system which can be realized at low cost without departing from the standard bus specifications.

[0018]

A processor system according to the present invention includes first and second buses, a first bus master device, a bus bridge, and one or more bus slave devices. The first bus master device is connected to the first bus. The bus bridge is connected between the first and second buses and has a delayed transaction function. The bus slave device includes a latency storage unit that stores a predetermined standard latency, and is connected to the second bus. The first bus master device includes a table storage unit, an initialization unit, a count unit, and an access unit. The table storage means stores a latency table in which the standard latency is associated with the bus slave device. The initialization means reads the standard latency from the bus slave device and stores it in the table storage means. The counting means is for counting the standard latency stored in the table storage means. The access means starts the counting means when issuing the transaction to the bus slave device, and re-issues the transaction when the counting means finishes counting the latency.

In this processor system, the standard latency is read from the bus slave device and stored in the table storage means of the bus master device. When the bus master device issues a transaction to the bus slave device, the counting means starts counting the standard latency stored in the table storage means, and when the counting means finishes counting the latency, the transaction is reissued. As a result, the number of unnecessary transactions issued from the bus master device decreases,
It is possible to prevent a decrease in the throughput of the first bus. In addition, since the bus slave device has the latency storage means, a bus bridge conforming to the standard bus specification can be used.

Preferably, the bus slave device includes a configuration register. The latency storage means is included in a configuration register.

Since the standard latency is registered in a configuration register defined in the PCI bus specification, it is not necessary to provide a storage area for the standard latency.

Preferably, the processor system further includes a processor and a main memory. The main memory is connected to the first bus master device. The first bus master device is a host bridge connected between the processor and the first bus.

More preferably, the host bridge includes a configuration register. The initialization means includes a configuration means for reading a standard latency from a configuration register of the bus slave device by issuing a configuration cycle and storing the read standard latency in the configuration register of the host bridge.

Therefore, the standard latency can be read from the configuration register of the bus slave device in the configuration cycle defined in the PCI bus specification and stored in the configuration register of the host bridge.

More preferably, the processor system further includes a second bus master device connected to the first bus. The host bridge includes means for transferring the latency table to a second bus master device.

Therefore, the standard latency of the bus slave device collected by the host bridge can be used by the second bus master device.

[0027] More preferably, the second bus master device includes a configuration register and means for receiving the latency table transferred from the host bridge and storing the same in the configuration register of the second bus master device.

Since the latency table transferred from the host bridge is stored in the configuration register specified in the PCI bus specification, it is not necessary to provide a storage area for the latency table.

Preferably, the first bus master device is provided with a plurality of counting means. The bus bridge includes a plurality of delayed transaction queues. The plurality of delayed transaction queues are provided corresponding to the plurality of counting means, and store information of the plurality of transactions received from the bus master device.

Therefore, even if the bus master device issues a plurality of transactions at the same time, a plurality of delayed transaction queues store information on the plurality of transactions. Therefore, there is no useless retry response in all transactions, and a decrease in the throughput of the first bus can be prevented.

Preferably, the access means temporarily releases the first bus when receiving a retry issued from the bus bridge.

Accordingly, another bus master device can acquire the right to use the first bus while the first bus is released.

Preferably, when a retry is received again when the transaction is reissued, the access means reissues the transaction after a predetermined waiting time has elapsed.

When the bus master device accesses the bus slave device, it receives a retry for the first transaction, waits for the standard latency obtained by referring to the latency table, and then reissues the second transaction. If a retry is received again, a delay may have occurred in internal processing of the bus slave device. Particularly in the case of a low-speed bus slave device, since the standard latency is very long, it is often useless to wait for the longer standard latency once after receiving a retry in the second transaction. . Therefore, in the waiting time after the second retry reception, the transaction is reissued after the elapse of a predetermined waiting time instead of using the standard latency of the latency table. As a result, access to the bus slave device can be terminated early.

[0035] More preferably, said access means comprises:
The waiting time is reduced as the number of issued transactions increases.

Therefore, the access to the bus slave device can be completed earlier.

[0037] More preferably, said access means comprises:
The number of retries received is monitored, and if the number of retries is greater than a predetermined number, the standard latency is rewritten to a longer latency.

When the host bridge accesses the bus slave device, it may repeatedly receive retries despite waiting using the standard latency of the latency table. In this case, the actual latency may be always longer than the standard latency assumed by the bus slave device. In such a case, by rewriting the corresponding standard latency in the latency table to a longer latency, useless retry can be prevented.

Preferably, when issuing a burst transaction, the access means calculates a latency obtained by adding a burst time to a standard latency. The counting means counts the calculated latency.

In the case of burst access, after waiting for the standard latency time, when the second transaction is issued, the second and subsequent burst data is being transferred between the bus bridge and the bus slave device.
The bus bridge always returns a retry response to the bus master device. In order to avoid this, the latency obtained by previously adding the unit cycle of the burst transfer to the standard latency is set as a new latency, so that unnecessary retry can be prevented.

The first and second buses have different clock frequencies. The access means converts the latency at the clock frequency of the second bus into the latency at the clock frequency of the first bus. The counting means counts the converted latency.

For example, the clock frequency of the first bus is 66 MHz, and the clock frequency of the second bus is 33 MHz.
, It is assumed that the standard latency of the bus slave device is 10 cycles. Since the counting means in the bus master device counts using the clock of the first bus, the bus master device counts 10 cycles at 66 MHz. This is 5 cycles at a clock frequency of 33 MHz, which is smaller than the original standard latency (10 cycles at 33 MHz), so that a useless retry response always occurs.

Therefore, when the clock frequencies of the first and second buses are different, the standard latency used by the counting means is recalculated according to the difference between the clock frequencies. The calculated latency is used.

[0044] Preferably, the first bus master device includes a configuration register. The configuration register has a status flag indicating that the configuration register has counting means.

Therefore, the host bridge can determine whether or not the bus master device has the counting means by referring to the status flag of the configuration register.

Preferably, the first bus master device includes a configuration register. The configuration register has a status flag indicating that a latency storage unit is provided.

Therefore, the host bridge only needs to execute the configuration read for the number of delay cycles to the bus slave device having the latency storage means. Therefore, by referring to the status flag, the host bridge can determine whether or not the bus master device has the latency storage unit.

Another processor system of the present invention includes a bus, a bus master device, and one or more bus slave devices. The bus master device is connected to the bus. The bus slave device includes a latency storage unit that stores a predetermined standard latency, and is connected to the bus. The bus master device includes a table storage unit, an initialization unit, a count unit, and an access unit. The table storage means stores a latency table in which the standard latency is associated with the bus slave device. The counting means is for counting the standard latency stored in the table storage means. The access means starts the counting means when issuing the transaction to the bus slave device, and re-issues the transaction when the counting means finishes counting the latency.

In this processor system, similarly to the above, the number of unnecessary transactions issued from the bus master device can be reduced, and a decrease in bus throughput can be prevented.

[0050]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] FIG. 1 is a schematic block diagram showing an overall configuration of a processor system (hereinafter referred to as "the present system") according to a first embodiment of the present invention.
As shown in FIG. 1, the system includes a primary PCI bus 1, a secondary PCI bus 2, and a host bridge 3.
, A bus master 4, a bus bridge 5, a first bus slave 6, a second bus slave 7, and a CPU (Centra
l Processing Unit) 8. Host bridge 3
Is connected between the CPU 8 and the primary PCI bus 1. The bus master 4 is connected to the primary PCI bus 1. The bus bridge 5 is connected between the primary PCI bus 1 and the secondary PCI bus 2. The first bus slave 6 and the second bus slave 7 are connected to the secondary PCI bus 2 respectively. The host bridge 3 is connected to the CPU 8 via the system bus 10 and further connected to the main memory 9 via the memory bus 11. Hereinafter, the host bridge 3, the bus master 4, and the bus slaves 6, 7 are collectively referred to as "PCI devices".

In FIG. 1, only one bus master 4 is connected to the primary PCI bus 1, but two or more bus masters are connected to the primary PCI bus 1 and the secondary PC.
It may be connected to the I bus 2. Although only two bus slaves 6 and 7 are connected to the secondary PCI bus 2 in FIG. 1, one or more bus slaves may be connected to the primary PCI bus 1.
The above bus slaves may be connected to the secondary PCI bus 1.

The PCI buses 1 and 2 are clock synchronous buses based on the PCI bus specification. Primary PCI
The clock frequency of the bus 1 is 66 MHz, and the clock frequency of the secondary PCI bus 2 is 33 MHz.
When each bus width is 32 bits, the primary PCI bus 1
Has a maximum data transfer rate of 266 Mbytes / sec.
The maximum data transfer rate of the secondary PCI bus 2 is 13
3 Mbytes / sec.

The CPU 8 is a central processing unit (main processor), controls the host bridge 3 by executing a program stored in a memory (not shown), and thereby operates the PCI devices 4, 6, and 7. . CPU8
Is, for example, RISC (Reduced Instruction Set Comp
This is realized by a microprocessor using the uter) method.

The system bus 10 includes an address / data bus, command signal lines, various control signal lines, and the like. The CPU 8 issues various commands to the host bridge 3 via the system bus 10.

The main memory 9 stores various data processed by the present system, and is also used as a work area and a data buffer when the CPU 8 executes a program. The main memory 9 is allocated to the PCI address space and is an area that can be accessed from the bus master 4. The main memory 9 includes, for example, a plurality of SDRAMs (Synchronaus Dynamic
Random Access Memory).

The memory bus 11 includes an address bus, a data bus, various memory control signal lines, and the like. The host bridge 3 performs read / write control on the main memory 9 via the memory bus 11.

The host bridge 3 functions as a bus master device for accessing the main memory 9 and other PCI devices in accordance with an instruction from the CPU 8, and receives signals from other bus master devices connected to the PCI buses 1 and 2. Functions as a bus slave device that responds to access to internal resources.

The bus master 4 is a primary PCI bus 1
Function as a bus master device for the host bridge 3
P including (when functioning as a bus slave device)
All PCI devices on the CI buses 1 and 2 can be accessed. In addition, the bus master 4
It also functions as a bus slave device responding to an access request from another bus master device (for example, host bridge 3) on the PCI buses 1 and 2.

As a PCI device having a bus master function, for example, there is a network controller connectable to a PCI bus. Upon receiving data from an external network interface, the network controller having the bus master function becomes a bus master of the PCI bus and can transmit data to the main memory 9.

Here, a method in which the bus master acquires the right to use the PCI bus will be described. All bus masters on the PCI bus are connected to a bus arbiter (not shown) via a common bus use request signal line (not shown) and a common bus use permission signal line (not shown). PC
A bus master who wants to use the I bus first asserts a bus use request signal to the bus arbiter. The bus arbiter arbitrates (arbitrates) a bus use request signal from each bus master in an internal arbitration unit, and asserts a bus use permission signal only to a bus master that permits use of the bus to notify the bus use permission. The bus master that has received the bus use permission signal starts a bus transaction after the PCI bus enters an idle phase.

The bus slaves 6 and 7 are connected to the host bridge 3
Alternatively, it functions as a bus slave device responding to an access request from the bus master 4.

As a PCI device having a bus slave function, for example, a USB (Univ.
ersal Serial Bus) controller. The USB controller receives data from an external USB interface and stores the data in an internal buffer memory. Thereafter, the host bridge 3 functions as a bus master device, whereby data is read from the buffer memory and stored in the main memory 9. The present system converts the data received from the external USB interface into a PCI
The data can be transferred to the main memory 9 via the buses 1 and 2.

The bus bridge 5 has two PCI buses 1,
2 is a PCI-PCI bridge that interconnects
It has a function of mutually transmitting transactions between the two PCI buses 1 and 2. The bus bridge 5 also has a PCI-
It has a delayed transaction function defined in the PCI bridge specification.

FIG. 2 is a detailed block diagram showing the overall configuration of the present system. As shown in FIG.
Includes a delayed transaction buffer 52 and a delayed transaction queue 53 for performing a delayed transaction. Bus bridge 5
When a transaction issued from a bus master device such as the host bridge 3 or the bus master 4 is received, the transaction information (address, command, write data, etc.) is first stored in a delayed transaction queue 53, and Return a retry response. The bus master device that has received the retry response reissues the transaction until a data transfer response is received from the bus bridge 5. During this time, the bus bridge 5 accesses a bus slave device such as the first bus slave 6 or the second bus slave 7 instead of the bus master device, and after completing data transmission / reception, transfers the data to the delayed transaction buffer 52. To save. After that, bus bridge 5
Responds to a transaction from the bus master device with a data transfer response using the data in the delayed transaction buffer 52. When the bus access with the bus master device is completed, the contents of the delayed transaction queue 53 and the delayed transaction buffer 52 are erased.

The host bridge 3, bus master 4,
The bus bridge 5 and the bus slaves 6 and 7 include configuration registers 31 and 4 conforming to the PCI bus specification.
1, 51, 61, and 71, respectively.

Configuration registers 31 and 4
As shown in FIG. 3, each of 1, 1, 61, and 71 has a configuration space of 256 bytes of addresses 00h to FFh, and includes a header part (addresses 00h to 3Fh) defined by the PCI bus specification and a device. (Addresses 40h to FFh).

The unique area can be used freely for each device. According to the PCI bus specification, each header section includes a device (Device) ID, a vendor (Vender) ID, a status (Status) register, a command (Command) register, and a base address register (BAR), as shown in FIG. ). A 32-bit base address can be set in each of the base address registers BAR0 to BAR5, and the base address register BAR of the address 10h is set.
Base address register BAR from address 0 to address 24h
As many as five can be used in order.

In each of the configuration registers 61 and 71 of the bus slaves 6 and 7, as shown in FIG.
Base address delay register BA corresponding to AR5
DR0 (address 40h) to BADR5 (address 54
h) is provided in the unique area. Each base address delay register previously stores the number of delay cycles of the corresponding base address register. This number of delay cycles depends on each PC functioning as a bus slave device.
This is the standard latency of the I device, and more specifically, the shortest time from when each PCI device receives a request to access the internal I / O space or memory space to when data can be transmitted / received (data transfer phase). Equivalent to time.
The number of delay cycles is stored as the number of cycles (the number of clocks) based on the clock frequency of the PCI bus 1 or 2 to which the PCI device is connected.

On the other hand, since the host bridge 3 and the bus master 4 function not only as a bus master device but also as a bus slave device, the configuration registers 31,
41, base address delay registers BADR0 (address 40h) to BADR5 (address 54h) are provided in the unique area as shown in FIG. 6, similarly to the bus slave device, and correspond to each base address delay register. The number of delay cycles in the base address register is stored in advance.

Since the host bridge 3 and the bus master 4 also function as bus master devices, areas (addresses 60h to FFh) for storing a delay cycle (latency) table are secured in each unique area. Then, the address blocks PADR1 to PADR
The DR 20 stores the base address of the PCI device in the PCI address space, and the address blocks PDLY1 to PDLY20 store the number of delay cycles of the PCI device, respectively.

As shown in FIG. 2, the host bridge 3 and the bus master 4 are provided with a delay cycle counter 3
2, 42 respectively. When the host bridge 3 functions as a bus master device, the delay cycle counter 32 of the host bridge 3 refers to the delay cycle table of the configuration register 31 and
The number of delay cycles of the PCI device that returns a retry response despite issuing a transaction is counted. The same applies to the delay cycle counter 42 of the bus master 4.

Although only one set of the delayed transaction buffer 52 and the delayed transaction queue 53 is shown in the bus bridge 5 in FIG. 2, a plurality of sets are usually provided. In this case, the host bridge 3 and the bus master 4 can simultaneously issue a plurality of bus accesses to the bus slaves 6 and 7 via the bus bridge 5. Therefore, delay cycle counters 32 and 42 are provided in host bridge 3 and bus master 4.
Are provided by the same number as the number of sets of the delayed transaction buffer 52 and the delayed transaction queue 53, so that different delay cycle counters can be assigned to a plurality of delayed transactions issued from the same bus master device, respectively. Useless retry responses are eliminated in all transactions.

Next, the operation of the present system will be described. <Configuration Cycle> First, the configuration procedure for initializing the PCI address space is shown in FIG.
This will be described with reference to the flowchart of FIG.

The CPU 8 controls the host bridge 3 and
All the PCI devices connected to the PCI buses 1 and 2 are searched (step S101). here,
Three PCI devices, a first bus slave 6, a second bus slave 7, and a bus master 4, are detected.

Next, the CPU 8 controls the host bridge 3 to acquire configuration information from the configuration registers 31, 41, 51, 61, 71 of all the PCI devices 3 to 7 (step S10).
2). By checking the initial values of the base address registers BAR0 and BAR1 of each configuration register, it is possible to know the size of the memory space and the I / O space required by each PCI device.

Here, the structure of the base address register will be described. Least significant bit 0 of each base address register
Indicates a memory space or an I / O space. When this bit is “0”, it indicates a memory space.
/ O space. In addition, some lower bits are implemented as read-only bits of “0” according to the required size of the address space.

For example, as shown in FIG. 8, in the configuration register 61 of the first bus slave 6, a base address register BAR0 (address 10)
The initial value of h) is “FFC00000h”. This means that the least significant bit is “0”, requesting the memory space, and since bits 21 and below are all implemented as read-only bits of “0”, the size of the memory space is This means that 4 Mbytes are requested. Also, the base address register BAR1
The initial value of (address 14h) is “FFFFFF01h”
It is. This means that the least significant bit is “1”, requesting the I / O space, and since bits 7 and below are all implemented as read-only bits of “0”, the I / O space is required. This means that 256 bytes are required as the size of the space.

Therefore, from the base address registers BAR0 and BAR1 of the configuration register 61 of the first bus slave 6, the first bus slave 6
Is 4 Mbytes of memory space and 256 bytes of I / O
It turns out that it needs space.

Similarly, based on the base address registers BAR0 and BAR1 of the configuration register 71 of the second bus slave 7 shown in FIG. 9, the second bus slave 7 has a memory space of 1 Mbyte and an I / O of 256 bytes. It turns out that it needs space.

The base address register BAR0 of the configuration register 41 of the bus master 4 shown in FIG. 10 indicates that the bus master 4 requires a memory space of 32 Mbytes.

Further, the host bridge 3 shown in FIG.
From the base address registers BAR0 and BAR1 of the configuration register 31, the host bridge 3 has a memory space of 32 Mbytes and a memory space of 256 bytes.
It can be seen that the / O space is required.

Next, the CPU 8 controls the host bridge 3 to check whether or not each PCI device implements the number of delay cycles (step S103), and reads the number of delay cycles if implemented. (Step S
104). In order to determine whether or not the number of delay cycles has been set, for example, a status flag indicating the presence or absence of the number of delay cycles is provided in a status register (address 04h; see FIG. 4) of the configuration register, and a host bridge is provided. 3 determines whether or not the number of delay cycles is set based on the status flag.

Next, the CPU 8 controls the host bridge 3 to store each PCI device according to the size of the memory space and the I / O space required by each PCI device.
Assigned to the CI address space (step S105).

FIG. 12 is a block diagram showing the size of the memory space and I / O space required by each PCI device. FIG. 13 shows the memory space and I shown in FIG.
6 is an address map showing assignment of a / O space. Here, the base address of the I / O space is “00000000”.
h ”, and the base address of the memory space is“ 8000 ”.
0000h ".

[0086] As shown in FIG.
It requires 56 bytes of I / O space.
The area in the address space is allocated as shown in FIG.
As shown in FIG. 12, the first bus slave 6 requires an I / O space of 256 bytes, and therefore, an area in the address space is allocated as shown in FIG. FIG.
As shown in FIG. 13, the second bus slave 7 requires an I / O space of 256 bytes, and therefore, an area in the address space is allocated as shown in FIG. As shown in FIG. 12, the host bridge 3 requires a memory space of 32 Mbytes, and therefore, an area in the address space is allocated as shown in FIG. As shown in FIG. 12, the bus master 4 requires a memory section of 32 Mbytes, and therefore, an area in the address space is allocated as shown in FIG. As shown in FIG. 12, the first bus slave 6
An M-byte memory space is required, for which an area in the address space is allocated as shown in FIG. As shown in FIG. 12, the second bus slave 7 requires a 1-Mbyte memory space, and therefore, an area in the address space is allocated as shown in FIG.

Table 1 below shows the base address, the number of delay cycles, and the size of the address space of each area shown in FIG. These pieces of information are temporarily stored in the main memory 9.

[0088]

[Table 1]

Next, the host bridge 3 creates a delay cycle table in which the base addresses of the areas 1 to 3 are associated with the number of delay cycles in the unique area of the configuration register 31 (step S106). That is, as shown in FIG. 14, the area (host bridge 3) is stored in the address 60h of the configuration register 31.
The base address of the I / O space is stored in an address 64h, and the number of delay cycles of the area is "00000000"
4h "(4 cycles) is stored. Similarly, after the address 68h, the base address and the number of delay cycles of the area 1 are stored.

Next, the host bridge 3 executes step S1
The base addresses of the memory space and the I / O space allocated in 05 are assigned to each PC in the configuration write cycle.
Set for each I device (step S10
7). Therefore, as shown in FIG. 14, in the configuration register 31 of the host bridge 3,
The base address register BAR0 (address 10h) stores the base address "80000000h" of the area (memory space of the host bridge 3), and the base address register BAR1 (address 14h) stores the area (I / O space of the host bridge 3). The base address “00000001h” is stored.

As shown in FIG. 15, in the configuration register 61 of the first bus slave 6, the base address register BAR0 (address 10h) stores the base address "of the area (memory space of the first bus slave 6)". 8400000h ”is stored, and the base address“ 00000101h ”of the area (I / O space of the first bus slave 6) is stored in the base address register BAR1 (address 14h). FIG.
As shown in (2), in the configuration register 71 of the second bus slave 7, the base address register BAR0 (address 10h) stores the base address “8440” of the area (memory space of the second bus slave 7).
0000h ”is stored in the base address register BA
In R1 (address 14h), the base address of the area (the I / O space of the second bus slave 7) is “0000020”.
1h "is stored. As shown in FIG. 17, in the configuration register 41 of the bus master 4, the base address register BAR0 (address 10
In h), the base address "8200000h" of the area (memory space of the bus master 4) is stored.

It is determined whether such a PCI device to be set is a bus master device (step S10).
8) In the case of a bus master device, it is determined whether or not the bus master device has a delay cycle counter (step S109). If a delay cycle counter is provided, the delay cycle table is transferred to the bus master device (step S11).
0). Here, the only bus master device other than the host bridge 3 is the bus master 4. Since the bus master 4 has the delay cycle counter 42, the delay cycle table (see FIG. 14) created in the configuration register 31 of the host bridge 3 is written at the same address in the configuration register 41 of the bus master 4. (See FIG. 17).

As a method of determining whether or not the bus master device has a delay cycle counter, a flag indicating the presence or absence of the delay cycle counter is provided in the status register (address 04h) of the configuration register. , It is possible to determine whether or not it has a delay cycle counter.

When the above setting is completed for all the PCI devices, the initialization (configuration) of the PCI address space is completed (step S11).
1).

<Bus Access> Next, the bus access procedure will be described with reference to the flowchart of FIG. Hereinafter, the following two cases will be described.

(A) The host bridge 3 operates in the I / O space (base address 000000020) of the second bus slave 7.
(B) The bus master 4 performs a burst read access to the memory space (base address 84000000h; area) of the first bus slave 6 (one transfer unit = 8 bursts). First, it is checked which address block of the delay cycle table contains the address of the bus slave to be accessed by the bus master device (steps S201 and S202). Then, the number of delay cycles of the address block including the address to be accessed is read from the delay cycle table (step S).
203).

If the address to be accessed is not included in any of the address blocks registered in the delay cycle table, a default number of delay cycles predetermined by the present system is read (step S204).

In the case of (A), the address “000002”
Since 00h is included in the area (see Table 1), the number of delay cycles is “0000001Bh” (27
Cycle).

In the case of (B), the address "840000"
00h "is included in the area (see Table 1), so that" 00000020h "(32
Cycle).

Next, if the bus access is a single access (not a burst access), step S2
The number of delay cycles read in 03 or S204 is directly used as the number of delay cycles. On the other hand, if the bus access is burst access, the number of burst transfer cycle cycles is added to the read number of delay cycles to obtain the number of delay cycles (steps S205 and S20).
6).

In the case of (A), since the access is a single access, the number of delay cycles "0000001Bh" (27 cycles) read in step S203 is directly used as the number of delay cycles.

In the case of (B), burst access is performed,
Since one burst transfer unit is “8”, the number of delay cycles “000000” read in step S203 is read.
Add "8" to "20h" (32 cycles) to get "000
"00028h" (40 cycles) is the number of delay cycles.

Next, the bus master device is the primary P
Clock frequency of CI bus 1 and secondary PCI bus 2
Are compared (step S207). If they differ, the number of delay cycles determined in steps S205 and S206 is converted into the number of delay cycles based on the clock frequency of the connected bus, and the value is converted. Set to delay cycle counter (step S
208). On the other hand, if the clock frequencies are the same, the number of delay cycles determined in steps S205 and S206 is directly set in the delay cycle counter (step S209).

In the case of (A), the number of delay cycles is “0”.
000001Bh ”(27 cycles). Since this cycle number is a value based on the clock frequency of 33 MHz of the secondary PCI bus 2 to which the second bus slave 7 is connected, the number of cycles is “000000001B” based on the clock frequency of 66 MHz of the primary PCI bus 1.
h ”(27 cycles) × (66/33) to convert the number of delay cycles into“ 00000 ”
036h "(54 cycles), and this value is set in the delay cycle counter 32.

In the case of (B), the number of delay cycles is “0”.
0000028h ”(40 cycles). Since the number of cycles is a value based on the clock frequency of 33 MHz of the secondary PCI bus 2 to which the first bus slave 6 is connected, the number of cycles is “00000002” based on the clock frequency of 66 MHz of the primary PCI bus 1.
h ”(40 cycles) × (66/33) to convert the number of delay cycles into“ 00000 ”
050h "(80 cycles), and this value is set in the delay cycle counter 32.

Next, the bus master device is the primary P
The right to use the CI bus 1 is acquired, a transaction is issued, and the delay cycle counter is started (step S210).

In the case of (A), the host bridge 3 issues an I / O read command to the address “00000200h”, starts a transaction, and starts counting of the delay cycle counter 32.

In the case of (B), the bus master 4 issues a memory read command to the address "84000000h" to start a transaction, and starts counting by the delay cycle counter 42.

Next, in the case of (A), after the host bridge 3 issues a transaction, the bus bridge 5 stores the access request contents (access target address, command, data, etc.) from the host bridge 3 in a delayed transaction queue. 53, and returns a retry response to the host bridge 3. The bus bridge 5 makes a single read access to the second bus slave 7 on the secondary PCI bus 2, stores the read data in the delayed transaction buffer 52 and ends the transaction with the second bus slave 7. I do.

In the case (B), after the bus master 4 issues a transaction, the bus bridge 5 holds the contents of the access request (target address, command, data, etc., to be accessed) from the bus master 4 in the delayed transaction queue 53, A retry response is returned to the bus master 4. Then, the bus bridge 5 performs a burst read access to the first bus slave 6 on the secondary PCI bus 2, stores the read data in the delayed transaction buffer 52, and ends the transaction with the first bus slave 6. I do.

If the host bridge 3 or the bus master 4 does not receive a response by the device select signal DEVSEL # indicating that the bus slave has started responding to the bus master within four cycles from the bus bridge 5, the master abort is performed. (Step S21)
1). The mechanism by which a master abort occurs is defined in the PCI bus specification.

Next, when the response from the bus bridge 5 is a retry, the transaction is temporarily ended. The bus master device releases the primary PCI bus 1 and does not reissue the transaction until the delay cycle counter has finished counting (steps S212 and S21).
3). Meanwhile, the bus bridge 5 completes the bus access to the bus slaves 6 and 7 on the secondary PCI bus 2. That is, during this time, another bus master device on the primary PCI bus 1 can acquire the right to use the primary PCI bus 1 and issue a transaction.

When the delay cycle counter finishes counting, the bus master device renews the primary PC.
The right to use the I bus 1 is acquired, the transaction is reissued, and the delay cycle counter is restarted (step S210).

In the case (A), the host bridge 3 receives the retry response from the bus bridge 5 and
Release bus 1. Then, the transaction is not reissued until the count of the delay cycle counter 32 is completed. During this time, on the secondary PCI bus 2, the bus bridge 5 makes a single read access to the I / O space (base address "00000200h"; area) of the second bus slave 7. When the delay cycle counter 32 finishes counting (27 cycles), the host bridge 3 reissues the transaction and restarts the delay cycle counter 32 (count value = 27 cycles).

In the case (B), the bus master 4 receives the retry response from the bus bridge 5 and releases the primary PCI bus 1. Then, the delay cycle counter 42
Do not reissue the transaction until the end of the count. During this time, in the secondary PCI bus 2, the bus bridge 5 performs a burst read access to the memory space (base address "84000000h"; area) of the first bus slave 6. When the delay cycle counter 42 finishes counting (40 cycles), the bus master 4 reissues the transaction and restarts the delay cycle counter 42 (count value = 40 cycles).

If the response from the bus bridge 5 is not a retry response but a data transfer response in step S212, the transaction is completed normally after the data transfer ends (step S214). Then, the bus master device stops the delay cycle counter and resets the count value.

In the case (A), the bus bridge 5 makes a single read access to the second bus slave 7 on the secondary PCI bus 2 and stores the read data in the delayed transaction buffer 52. The bus bridge 5 ready for data transfer thereafter performs a single read data transfer response instead of a retry response to the transaction from the host bridge 3, and the transaction is completed normally. Then, the delay cycle counter 32 stops, and the count value is reset.

In the case (B), the bus bridge 5 makes a burst read access to the first bus slave 6 on the secondary PCI bus 2 and stores the read data for eight bursts in the delayed transaction buffer 52. . The bus bridge 5 that is ready for the 8 burst data transfer thereafter performs a burst read data transfer instead of a retry response to the transaction from the bus master 4, and the transaction is completed normally. Then, the delay cycle counter 42 stops, and the count value is reset.

If normal data transfer is not performed in step S214, an access that cannot be processed by the bus slave device is performed, and the transaction is aborted due to the target abort.

Here, a case where a retry response occurs twice or more in the processing of steps S210 to S214 in the bus access processing procedure shown in FIG. 17 will be described.

Normally, the bus bridge 5 always starts a retry response to the first transaction issued by the bus master device, and the bus master device waits until the delay cycle counter finishes counting, and then re-issues the second transaction. Completes the normal data transfer. This is because the count value of the delay cycle counter is set to a time (delay cycle) required until the bus slave device can transfer data. However, the secondary PCI bus 2
Is occupied by another bus master device for a long time, or if there is contention for access to the same resource inside the bus slave device, the bus bridge 5
It takes time for bus access between the bus and the slave device, and the bus bridge 5 must return a retry response many times for the second and subsequent transactions. In such a case, step S208 or S209
In this case, it becomes meaningless to wait every time in step S213 for the delay cycle number initially set, and a useless waiting time may be generated.

Therefore, when a retry response occurs twice or more, it is desirable to reset the number of delay cycles to a new value before restarting the second and subsequent counts of the delay cycle counter in step S210.

For example, after the second and subsequent retry responses are received, there is a method of using a predetermined number of delay cycles (for example, first two to three cycles) in this system.

There is a method of gradually reducing the number of delay cycles according to the number of times a retry response has been received. For example, when the second retry response is received, the delay is read from the delay cycle response table and waits for half the number of delay cycles initially set, and when the third retry response is received, the first retry response is received. Is set to wait for one third of the number of delay cycles set in. That is, after receiving the n-th retry response, the initially set number of delay cycles is set to n
The value reduced to one-half is reset as the number of delay cycles.

When a transaction that causes a retry response to occur twice or more as described above in the bus access to the same address block occurs many times,
It is conceivable that internal resource contention occurs frequently for a long time in the bus slave device, or that the number of delay cycles is set to an incorrect value for some reason. In such a case, the host bridge 3 monitors the number of receptions of the retry response, and when the number of receptions of the retry response becomes larger than a predetermined number, the delay cycle of the corresponding address block in the delay cycle table. The number may be rewritten to a cycle number larger than the original cycle number. At this time, the changed delay cycle number is transferred to all other bus master devices having the delay cycle counter by executing a configuration write cycle to a configuration register address corresponding to the corresponding address block.

FIG. 19 is a timing chart showing a comparison of bus transactions when the bus access of FIG. 19A is performed by the conventional method and the method of the present invention. In FIG. 19, the horizontal axis indicates the flow of transactions on the primary PCI bus 1 and the secondary PCI bus 2.

A1 is the address phase of the transaction issued by the host bridge 3 and represents the start of single read access to the I / O space of the second bus slave 7. A1 'is an address phase of a transaction issued by the bus bridge 5 to the second bus slave 7, and corresponds to A1 described above. R indicates a retry response, and SD indicates a single data phase.

A2 indicates the start of burst read access to the memory space of the first bus slave 6 in the address phase of the transaction by the bus master 4. BD (8) represents a data phase of 8 bursts. This transaction represents the burst access of the above (B).

As shown in FIG. 19, in the conventional method, useless retry transactions occur on the primary PCI bus 1 four times. Meanwhile, the primary PCI bus 1 is almost exclusively used by the host bridge 3. However, since the useless retry transaction does not occur in the method according to the first embodiment, while the delay cycle counter is operating, the host bridge 3
Releases the primary PCI bus 1 and is effectively used by another bus master device (for example, the bus master 4).

As described above, according to the first embodiment,
When the bus master device accesses the bus slave device via the bus bridge 5, it is possible to avoid unnecessary retry overhead compared to the conventional delayed transaction method, and to prevent a decrease in bus throughput. it can.

Since the bus slaves 6 and 7 themselves use the number of delay cycles preset in the configuration registers 61 and 71 as a waiting time before retrying the transaction, the value of the waiting time (number of delay cycles) is used. Is accurate.

Further, by using the unique area of the configuration registers 31, 41, 61, and 71 as an area for storing the number of delay cycles and the delay cycle table, a system completely compliant with the PCI bus specification is constituted. can do. As for the bus bridge 5, the conventional PCI-PCI conforming to the PCI bus specification
Since the bridge can be used as it is, there is no need to change the specifications of the bus bridge 5 when employing this system. Further, since the signal timing of the bus transistor completely conforms to the PCI bus specification, there is no problem regarding the connectivity with other PCI devices.

[Second Embodiment] In the first embodiment described above, the system including the two PCI buses 1 and 2 and the bus bridge 5 connected between them is shown. In the second embodiment, The secondary PCI bus 2 and the bus bridge 5 do not exist, and the bus slave itself has a delayed transaction function.

FIG. 20 is a schematic block diagram showing an overall configuration of a processor system according to the second embodiment. FIG.
As shown in FIG.
1 and the first bus slave 6 and the second bus slave 6
Are connected to the PCI bus 301.

FIG. 21 is a detailed block diagram showing the entire configuration of the system shown in FIG. As shown in FIG. 21, the first bus slave 306 includes a delayed transaction buffer 362 and a delayed transaction queue 363, and has a delayed transaction function. Similarly, the second bus slave 307 includes a delayed transaction buffer 372 and a delayed transaction queue 373, and has a delayed transaction function. Configuration and bus access according to the second embodiment are performed in the same procedure as in the first embodiment.

First, the CPU 8 sets each P at the time of system startup.
In order to initialize the CI device, the host bridge 3 is controlled to issue a configuration cycle. Initialization (configuration) of the PCI address space is performed according to the procedure (steps S101 to S111) shown in the flowchart of FIG.

Next, the bus access is performed according to the first embodiment.
Almost in the same manner as described above, the procedure is performed according to the procedure shown in the flowchart of FIG. The difference from the first embodiment is that bus master devices such as the host bridge 3 and the bus master 4 directly access the bus slaves 306 and 307 because the bus slaves 306 and 307 themselves have a delayed transaction function. It is to do. Also, secondary P
Since the CI bus does not exist, step S in FIG.
207 is always “YES”, and the process of step S208 does not occur.

[Other Embodiments] The First Embodiment
In the example, the bus master 4 is connected to the primary PCI bus 1 and the bus slaves 6 and 7 are connected to the secondary PCI bus 2, but the configuration of the present system is not limited to this.
That is, the bus slaves 6, 7 are connected to the primary PCI bus 1.
May be connected, and the bus master 4 may be connected to the secondary PCI bus 2.

The numbers of the PCI bus, bus master, bus bridge, and bus slave are not limited to those described above. The bus to which the bus master device or the bus slave device is connected is not limited to the PCI bus.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0141]

As described above, according to the present invention, a predetermined standard latency is stored in the bus slave device, and the bus master device reads out the standard latency and creates a latency table corresponding to the bus slave device. Since they are stored, a processor system conforming to the standard bus specifications can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a processor system according to a first embodiment of the present invention.

FIG. 2 is a detailed block diagram showing the overall configuration of the processor system shown in FIG.

FIG. 3 is a diagram showing an address space of a configuration register shown in FIG. 2;

FIG. 4 is a diagram illustrating a configuration of a header section of the configuration register illustrated in FIG. 3;

FIG. 5 is a diagram showing a configuration of a configuration register of each bus slave shown in FIG. 2;

FIG. 6 is a diagram illustrating a configuration of a configuration register of the host bridge or the bus master illustrated in FIG. 2;

FIG. 7 is a flowchart showing a configuration cycle by the processor system shown in FIGS. 1 and 2;

8 is a diagram illustrating a state before configuration of a configuration register of a first bus slave illustrated in FIG. 2;

9 is a diagram illustrating a state before configuration of a configuration register of a second bus slave illustrated in FIG. 2;

10 is a diagram illustrating a state before configuration of a configuration register of the bus master illustrated in FIG. 2;

11 is a diagram illustrating a state before configuration of a configuration register of the host bridge 3 illustrated in FIG. 2;

12 is a block diagram showing the sizes of a memory space and an I / O space required by each PCI device shown in FIG.

13 is an address map showing allocation of a memory space and an I / O space required by each PCI device shown in FIG. 12 in a PCI address space.

14 is a diagram illustrating a state after configuration of a configuration register of the host bridge illustrated in FIG. 11;

FIG. 15 is a diagram showing a state after configuration of a configuration register of the first bus slave 6 shown in FIG. 8;

16 is a diagram illustrating a state after configuration of a configuration register of a second bus slave illustrated in FIG. 9;

17 is a diagram illustrating a state after configuration of a configuration register of the bus master illustrated in FIG. 10;

FIG. 18 is a flowchart showing a procedure of bus access by the processor system shown in FIGS. 1 and 2;

FIG. 19 is a timing chart showing the bus access shown in FIG. 18 in comparison with a conventional method.

FIG. 20 is a schematic block diagram showing an overall configuration of a processor system according to a second embodiment of the present invention.

FIG. 21 is a detailed block diagram showing the overall configuration of the processor system shown in FIG.

[Explanation of symbols]

1 primary PCI bus, 2 secondary PCI bus, 3 host bridge, 4 bus master, 5 bus bridge, 6, 7, 306, 307 bus slave, 8
CPU, 9 main memory, 31, 41, 51, 61,
71 Configuration register, 32, 42 Delay cycle counter, 52, 362, 372 Delayed transaction buffer, 53, 363, 37
3 Delayed transaction queue.

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (16)

[Claims] A first bus connected to the first bus; a first bus master device connected to the first bus; and a bus bridge connected between the first and second buses and having a delayed transaction function. And 1 or 2 connected to the second bus, including latency storage means for storing a predetermined standard latency.
The first bus master device comprises: a table storage unit for storing a latency table in which the standard latency is associated with the bus slave device; and the first bus master device stores the standard latency from the bus slave device. Initialization means for reading and storing in the table storage means; counting means for counting standard latency stored in the table storage means; and starting the counting means when a transaction is issued to the bus slave device. And an access unit for reissuing the transaction when the counting unit has finished counting the latency. 2. The processor system according to claim 1, wherein said bus slave device includes a configuration register, and wherein said latency storage means is included in said configuration register. 3. The processor system further includes: a processor; and a main memory connected to the first bus master device, wherein the first bus master device is connected between the processor and the first bus. 3. The processor system according to claim 2, wherein said processor system is a host bridge. 4. The host bridge includes a configuration register, and the initialization unit reads a standard latency from a configuration register of the bus slave device by issuing a configuration cycle to read a standard latency from the configuration register of the host bridge. The processor system according to claim 3, further comprising a configuration unit configured to store the information in the processor. 5. The processor system further comprises: a second bus master device connected to the first bus; and the host bridge includes means for transferring the latency table to the second bus master device. The processor system according to claim 4. 6. The second bus master device includes: a configuration register; and means for receiving the latency table transferred from the host bridge and storing the latency table in the configuration register of the second bus master device. The processor system according to claim 5. 7. The first bus master device is provided with a plurality of the counting means, and the bus bridge is provided corresponding to the plurality of counting means, and is configured to receive information of a plurality of transactions received from the bus master device. The processor system according to claim 1, further comprising a plurality of delayed transaction queues that respectively store. 8. The processor system according to claim 1, wherein said access means temporarily releases said first bus when receiving a retry issued from said bus bridge. 9. The processor system according to claim 1, wherein the access unit reissues the transaction after elapse of a predetermined waiting time when the retry is received again when the transaction is reissued. . 10. The processor system according to claim 9, wherein said access unit shortens said waiting time as the number of times of issuing said transaction increases. 11. The processor according to claim 9, wherein the access unit monitors the number of times the retry is received, and rewrites the standard latency to a longer latency when the number of times of reception is greater than a predetermined number. system. 12. The apparatus according to claim 1, wherein, when issuing a burst transaction, the access unit calculates a latency obtained by adding a burst time to the standard latency, and the counting unit counts the calculated latency. Processor system. 13. The first and second buses have different clock frequencies from each other, and the access means converts latency at the clock frequency of the second bus into latency at the clock frequency of the first bus. The processor system according to claim 1, wherein said counting means counts the converted latency. 14. The first bus master device includes a configuration register, wherein the configuration register has a status flag indicating that the device has the counting means.
The processor system according to claim 1. 15. The processor system according to claim 1, wherein the first bus master device includes a configuration register, and the configuration register has a status flag indicating that the configuration includes the latency storage unit. 16. A bus, comprising: a bus master device connected to the bus; and one or more bus slave devices connected to the bus, including a latency storage unit for storing a predetermined standard latency. A table storage unit for storing a latency table in which the standard latency is associated with the bus slave device; and initialization for reading the standard latency from the bus slave device and storing the read standard latency in the table storage unit. Means for counting the standard latency stored in the table storage means, and starting the counting means when issuing a transaction to the bus slave device, wherein the counting means counts the latency. When finished And an access means to reissue Nzakushon, processor system.