JP2001252447A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow an electric component control means to reliably receive a command when the command is transmitted from a game control means to the electric component control means in a game machine. SOLUTION: An INT signal (payout control signal INT) from a main substrate is connected to the CLK/TRG2 terminal of a payout control CPU. When a clock signal is inputted to the CLK/TRG2 terminal, the value of a timer counter register CLK/TRG2 stored in the payout control CPU is counted down. When the register value becomes 0, an interrupt for activating a command receiving process occurs. The payout control CPU periodically executes the payout control process via the timer interrupt. The command receiving process is executed preferentially to the payout control process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine, a coin game machine, a slot machine, etc., in which a game is played in accordance with a player's operation. A gaming machine in which a game is played in accordance with a game machine.

[0002]

2. Description of the Related Art As an example of a gaming machine, when a game medium such as a game ball is fired into a game area by a launching device, and a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of game media are played. Some prize balls are paid out to players. Further, a variable display unit whose display state can be changed is provided, and when a display result of the variable display unit becomes a predetermined specific display mode, a predetermined game value is provided to the player. There is.

[0003] The game value means that the state of the variable winning ball device provided in the game area of the gaming machine is in a state that is advantageous for a player who is likely to win a hit ball, or is in a state that is advantageous for the player. Rights, or a condition in which conditions for paying out prize game media are easily established. Further, when a predetermined amount of game balls or coins are awarded or points are added in accordance with establishment of predetermined conditions such as winning, these are referred to as valuable values.

In a pachinko gaming machine, when a display result of a variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is generally called a "big hit". When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. In each open period, a predetermined number (for example, 10
) Will be closed when there is a prize in the special winning opening.
The number of opening of the special winning opening is a predetermined number (for example, 16
Round). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Further, at the time when the special winning opening is closed, predetermined conditions (for example, winning in the V zone provided in the special winning opening)
Is not established, the big hit gaming state ends.

[0005] Further, among the combinations of display modes other than the combination of "big hits", when a part of the display results of the plurality of variable display portions is not yet derived and displayed, it is already definite or temporary. A state in which the display mode of the variable display unit on which the various display results are derived and displayed satisfies the display condition that is a combination of the specific display modes is referred to as “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of "big hit", the result is "missing" and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

When a game ball wins a winning opening provided on the game board, a predetermined number of award balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means,
It is transmitted to a payout control board equipped with a payout control means. Hereinafter, control means other than the game control means may be referred to as electric component control means. The payout control unit is an example of a value assignment control unit.

In such a gaming machine, a speaker is provided, and various sound effects are emitted from the speaker as the game progresses in order to enhance the game effect. In addition, a light-emitting body such as a lamp or an LED is provided in a game area or a frame of the gaming machine, and the light-emitting body is turned on or off as the game progresses in order to enhance a game effect. Since the sound from the speaker and the lighting / extinguishing of each illuminant are controlled according to the progress of the game, the control thereof is generally performed as follows.
This is performed by game control means for controlling the progress of the game.
In this case, if a voice control unit provided separately from the game control unit and specifically controls the speaker and a luminous body control unit performing specific control on the luminous body are provided, the control load of the game control unit is reduced. be able to.

[0008]

In the case where various electric component control means are provided separately from the game control means,
A control command must be transmitted from the game control means to each electric component control means. Also, each electric component control means performs various processing based on the received control command, but since the control command is generated based on the processing of the game control means, it operates independently of the game control means. The control command can be transmitted at any stage during the execution of the process of the electric component control means. That is, the control command is not sent out at a fixed timing, but the control command is sent out suddenly during the operation of the electric component control means. If the control command is received incorrectly, it will interfere with the control that the electrical component control means must perform.
Each electric component control means needs to reliably receive a control command from the game control means.

In view of the above, the present invention provides a gaming machine in which a command is sent from a game control means to another electric component control means, in which the electric component control means can reliably receive the command. The purpose is to provide.

[0010]

A gaming machine according to the present invention comprises:
A game machine in which a player can play a predetermined game, a game control means for controlling the progress of the game, and an electric component control for performing an electric component control process for controlling an electric component provided in the game machine Means, the game control means executes a command output process for outputting command data and a capture signal designating capture of the command data to the electrical component control means, and the electrical component control means performs a predetermined period of time. A command reception for executing a predetermined periodic interrupt process in response to the interrupt generated in the above and receiving a command output by the game control means in response to an interrupt based on an input of a capture signal from the game control means The processing is executed, and the command reception processing is executed prior to the periodic interruption processing.

It is preferable that the electric component control means is configured not to permit the interruption until the command receiving process is completed.

When an interruption based on the input of the fetch signal occurs during the execution of the periodic interrupt processing, the electric component control means is configured to interrupt the periodic interrupt processing and execute the command receiving processing. Is preferred.

It is preferable that the periodic interrupt processing is configured to be executed in an interrupt permission state.

[0014] The electric component control means may be configured to execute processing relating to electric component control in response to an interrupt generated at a predetermined cycle.

The electric component control means includes a plurality of interrupt generating units capable of generating an interrupt, wherein the priority of each interrupt generating unit can be set, and an interrupt for a command receiving interrupt is generated. The priority of the interrupt generating unit that performs the interrupt may be set higher than the priority of the interrupt generating unit that generates the interrupt for the periodic interrupt processing.

The electric component control means includes updating means for updating the value of the specific register in response to the input of the capture signal from the game control means, and the game is executed in response to the value of the specific register reaching a predetermined value. It may be configured to execute a command receiving process for receiving a command output by the control unit.

The electric component control means may be configured to set an initial value in a specific register in the initial setting process.

The electric component control means may be configured to be able to simultaneously store a plurality of input command data.

The command receiving process may be configured to include a command determining process for determining whether or not the input command data is proper command data.

One command information sent to the electric component control means may be constituted by two command data.

The game control means may be configured to be able to output the first command data and the next command data in an identifiable manner.

[0022]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the mechanical board of the pachinko gaming machine 1 as viewed from the back. In the following embodiments, a description will be given of a pachinko gaming machine as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine,
For example, a coin gaming machine or the like may be used. Further, the present invention can be applied to an image-type gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing storage balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In addition, a pass storage display (ordinary symbol storage display) 41 including four LEDs is provided below the variable display 10. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In the passage between the passage gate 11 and the ball exit 13, there is a gate switch 12 for detecting a hit ball passing through the passage gate 11. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6 and is turned on by the starting port switch 17.
Is detected by In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14.
The variable winning ball device 15 is opened by the solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the gaming balls into the respective winning ports 19 and 24 is determined by setting the corresponding winning port switches 19a and 19a.
24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. Also, on the upper left and right sides outside the game area 7,
Two speakers 27 that emit sound effects are provided.
A game effect LED 28a and game effect lamps 28b and 28c are provided on the outer periphery of the game area 7.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a premium ball is paid out, and a ball out lamp 52 which is lit up when the supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming table 1 and enables lending of a ball by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card can be used. If there is a fraction (less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols accompanied by a probability change, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back side of the variable display device 8, as shown in FIG. 2, a ball storage tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, the game balls from above. Ball storage tank 3
8 is supplied. The game ball in the ball storage tank 38 reaches the ball payout device through the guiding gutter 39.

On the mechanism board 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. 31), a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a payout control board 37 mounted with a prize ball control microcomputer for controlling payout of game balls. Is installed. Further, a ball is hit on the lower part of the mechanism plate 36 by using the rotating force of the motor in the game area 7.
Ball launching device 34 that launches on a game effect lamp / LE
D28a, 28b, 28c, a prize ball lamp 51 and a lamp control board 35 for sending signals to the ball out lamp 52 are provided.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine 1 as viewed from the rear. The balls stored in the ball storage tank 38 pass through the guide gutter 39, pass through the ball cut detectors (ball cut switches) 187a and 187b, and are dispensed through the ball supply gutters 186a and 186b, as shown in FIG. Device 9
Reaches 7. The ball-out switches 187a and 187b are switches for detecting the presence or absence of a game ball in the game-ball passage, and a ball-out detection switch 167 for detecting a shortage of replenishment balls in the ball tank 38 is also provided. The game balls paid out from the ball payout device 97 are supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45.
On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls are paid out based on the prize, and the hitting ball supply tray 3 becomes full. Finally, after the game balls reach the contact port 45, the game balls are further paid out. It is led to the ball tray 4. When the game balls are further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In that state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hit ball firing device 34 also stops.

Next, the structure of the intermediate base unit installed on the mechanism plate 36 will be described. The intermediate base unit includes the ball supply gutters 186a and 186b and the ball discharging device 9
7 is installed. As shown in FIG. 4, connecting concave protrusions 182 are formed on the upper and lower sides of the intermediate base unit. The connection concave projection 182 connects and fixes the intermediate base unit and the upper base unit and the lower base unit of the mechanism plate 36.

A passage member 18 is provided above the intermediate base unit.
4 is fixed. The ball dispensing device 97 is fixed to a lower portion of the passage body 184. The passage body 184 is a payout ball passage 186 that allows two rows of game balls whose flow direction has been changed left and right by the curve gutter 174 (see FIG. 3) to flow down.
a, 186b. Dispensing ball passages 186a, 186b
On the upstream side of the ball, ball breaking switches 187a and 187b are provided. The ball out switches 187a and 187b
It detects the presence or absence of a game ball in the payout ball passages 186a and 186b, and detects a ball out switch 187a or 187b.
Stops detecting the game ball, the rotation of the payout motor (not shown in FIG. 4) in the ball payout device 97 is stopped, and the ball payout is immobilized.

It should be noted that the ball out switches 187a, 187b
Is locked by a locking piece 188 at a position where it can be detected that about 27 to 28 game balls exist in the payout ball paths 186a and 186b. That is, the out-of-ball switches 187a and 187b are the maximum payout amount of one unit of the prize ball (15 in this embodiment) and the maximum payout amount of one unit of the ball lending (100 yen: 25 in this embodiment).
It is installed in a position where it can be confirmed that the above is secured.

The central portion of the passage body 184 is formed in a shape curved right and left so as to reduce the ball pressure of the game ball flowing down inside. And the payout ball passages 186a, 186b
A stop hole 189 is formed therebetween. The mounting boss provided on the intermediate base unit is fitted into the back surface of the stop hole 189. The set screw is screwed in that state,
The passage body 184 is fixed to the intermediate base unit. Before being screwed, the positioning of the passage body 184 can be performed by a locking projection 185 provided on the intermediate base unit.

Below the passage body 184, a ball payout device 97 is provided.
To supply the game balls to the ball, and in the event of failure, the ball payout device 9
A ball stopping device 190 for stopping the supply of game balls to the game ball 7 is provided. The ball dispensing device 97 installed below the ball stopping device 190 is housed inside a rectangular parallelepiped case 198. Protrusions are provided at four places on the left and right of the case 198. The lower end of the case 198 is fitted into an elastic engagement piece provided at a lower portion of the intermediate base unit with each projection being related to a positioning projection provided on the intermediate base unit.

FIG. 5 is an exploded perspective view of the ball payout device 97. The configuration and operation of the ball payout device 97 will be described with reference to FIG. Ball payout device 97 in this embodiment
, A stepping motor (payout motor) 289 rotates a screw 288 to pay out pachinko balls one by one. The ball payout device 97 pays out not only premium balls based on winnings but also game balls to be lent.

As shown in FIG. 5, the ball dispensing device 97
There are two cases 198a and 198b. The ball dispensing device 9 is provided at two places on the left and right of each case 198a, 198b.
7 is provided with an engagement projection 280 that is in contact with a positioning projection provided at the upper part of the installation position. In each case 198a, 198b, a ball supply path 281a,
81b are formed. Ball supply path 281a, 281b
Has curved surfaces 282a and 282b, and has curved surfaces 282a and 282b.
Below the end of 282b, there is a ball feed horizontal path 284a, 2
84b are formed. In addition, ball feed horizontal path 284
Ball discharge passages 283a and 283b are formed at the ends of a and 284b.

The ball supply paths 281a and 281b, the ball feed horizontal paths 284a and 284b, and the ball discharge paths 283a and 283b.
Are formed in front of partition walls 295a and 295b that partition the cases 198a and 198b forward and backward, respectively.
Further, in front of the partition walls 295a and 295b, a ball pressure buffering member 285 is sandwiched between the cases 198a and 198b. The ball pressure buffering member 285 distributes the ball supplied to the ball payout device 97 to the left and right sides and the ball supply paths 281a, 281.
81b.

Further, below the ball pressure buffering member 285, a payout motor position sensor including a light emitting element (LED) 286 and a light receiving element (not shown) is provided. Light emitting element 2
86 and the light receiving element are provided at a predetermined interval. The distal end of the screw 288 is inserted into the space. The ball pressure buffering member 28
When the cases 198a and 198b are attached to each other, the case 5 is completely stored and fixed therein.

The ball feed horizontal paths 284a and 284b have a screw 28 rotated by a payout motor 289.
8 are arranged. The payout motor 289 is fixed to the motor fixing plate 290, and the motor fixing plate 290 is
Fixing grooves 291a, 2 formed behind 5a, 295b
Fits into 91b. In this state, the motor shaft of the dispensing motor 289 projects forward of the partition walls 295a, 295b, so that the screw 288 is fixed forward of the projection. On the outer periphery of the screw 288, a spiral protrusion 288a for moving the game ball placed on the ball feed horizontal path 284a, 284b forward by the rotation of the payout motor 289.
Is provided.

A recess is formed at the tip of the screw 288 so as to house the light emitting element 286, and two notches 292 are formed 180 degrees apart from each other on the outer periphery of the recess. Therefore, while the screw 288 makes one rotation, the light from the light emitting element 286 is
Is detected twice by the light receiving element via the.

That is, the dispensing motor position sensor including the light emitting element 286 and the light receiving element is for stopping the screw 288 at a fixed position and detecting that the dispensing operation has been performed. The wires from the light emitting element 286, the light receiving element, and the payout motor 289 are collectively pulled out to the outside through drawout holes formed below the rear portions of the cases 198a, 198b, and connected to the connector.

The game balls are moved horizontally by ball 284a, 284b.
When the payout motor 289 rotates in a state where the screw 288 is placed on the
The game ball moves forward on the ball feeding horizontal paths 284a and 284b. And finally, ball feed horizontal path 28
4a, 284b from the end of the ball discharge path 283a, 283b
To fall. At this time, the left and right ball feed horizontal paths 284a,
The drop from 284b is performed alternately. That is, every time the screw 288 makes a half turn, one game ball falls from one side. Therefore, every time one game ball falls, light from the light emitting element 286 is detected by the light receiving element.

As shown in FIG. 4, a ball distribution member 311 is provided below the ball payout device 97. The ball distribution member 311 is driven by the distribution solenoid 310. For example, when the solenoid 310 is on, the ball sorting member 311 falls to the right, and when it is off, it falls to the left. Below the distribution solenoid 310, a prize ball count switch 301A and a ball lending count switch 301B are provided by proximity switches. At the time of the prize ball based on the winning, the ball sorting member 311 falls to the right side and the ball discharge path 283
The balls from a and 283b are both prize ball count switches 3.
Pass through 01A. Also, when lending a ball, the ball distribution member 3
The ball 11 from the ball discharge paths 283a and 283b both passes through the ball lending count switch 301B. Accordingly, the ball payout device 97 can switch the payout flow path between the time of winning a ball and the time of lending a ball, and can pay out a predetermined number of game media.

As described above, by providing the ball sorting member 311, the balls that have fallen in the two ball passages can receive the prize ball count switch 301 A and the ball lending count switch 30.
1B. Therefore,
The number of prize balls or the number of ball lending can be immediately grasped from the detection output of the prize ball counting switch 301A and the ball lending count switch 301B without determining whether the ball is a prize ball or a ball lending.

In this embodiment, a ball payout device 97 that pays out game balls by rotation of a stepping motor is used as a ball payout device that pays out game balls by driving an electric drive source. A ball payout device having a structure in which a game ball is sent out by a driving source of the above may be used, or a ball payout device having a structure in which a stopper is removed by driving an electric drive source to pay out the game ball by its own weight may be used. Also, here, the ball sorting member 311
A mechanism for switching between a ball payout path when winning a prize ball and a ball payout path when lending a ball is used, but a configuration in which a ball payout mechanism when awarding a ball and a ball payout mechanism when lending a ball are provided independently. May be used.

FIG. 6 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 6 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
And a switch circuit 58 for giving signals from the gate switch 12, the starting port switch 17, the V count switch 22, the count switch 23, the winning port switches 19a and 24a, and the prize ball count switch 301A to the basic circuit 53. And a solenoid circuit 59 for driving the solenoid 16 for opening and closing the variable winning ball device 15 and the solenoid 21 for opening and closing the opening and closing plate 20 in accordance with a command from the basic circuit 53.

According to the data supplied from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display on the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to the program, and an I / O port unit 5.
7 inclusive. In this embodiment, the ROM 54 and the RAM 5
5 is built in the CPU 56. That is, the CPU 5
Reference numeral 6 denotes a one-chip microcomputer. In addition, 1
The chip microcomputer has at least the RAM 55
And the ROM 54 and the I / O port unit 57 may be external or internal. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 includes a system reset circuit 65 for resetting the basic circuit 53 when the power is turned on, and an address signal supplied from the basic circuit 53 to decode the I / O port section 57. I /
An address decode circuit 67 for outputting a signal for selecting the O port is provided. Note that the ball payout device 9
There is also switch information input to the main board 31 from 7,
They are omitted in FIG.

A hit ball firing device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a firing control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 is used to display the start memory display 18, the gate passage memory display 41 and the decoration lamp 25 provided on the game board. Controls the game and the game effect lamp / LED 28 provided on the frame side.
a, 28b, and 28c, display control of the award ball lamp 51, and the ball out lamp 52 are performed. Here, the lamp control unit is an example of the illuminant control unit. The display control of the variable display unit 9 for variably displaying special symbols and the variable display 10 for variably displaying ordinary symbols is performed by display control means mounted on the display control board 80.

FIG. 7 shows a circuit configuration in the display control board 80, in which an LCD (liquid crystal display) 82, which is an example of the variable display section 9, an variable display 10, and an output port (port 0, 2) It is a block diagram shown together with 570, 572 and output buffer circuits 620, 62A. Output port (output port 2) 572 outputs 8-bit data, and output port 570 outputs a 1-bit strobe signal (INT signal).

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and receives an INT signal from the main board 31 via the noise filter 107 and the input buffer circuit 105B, and receives a display control command via the input buffer circuit 105A. As the input buffer circuits 105A and 105B, for example, 74HC540 and 74HC14, which are general-purpose ICs, can be used. When the display control CPU 101 does not include an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

The display control CPU 101 performs display control of the screen displayed on the LCD 82 according to the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. VDP103
Reads necessary data from the character ROM 86. The VDP 103 controls the LCD 8 according to the input data.
2 to generate image data to be displayed on the LCD 2, and output R, G, B signals and a synchronization signal to the LCD 82.

FIG. 7 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, figures, or symbols displayed on the LCD 82.

The input buffer circuits 105A and 105B
The signal can be passed only in the direction from the main board 31 to the display control board 80. Therefore, the display control board 8
There is no room for a signal to be transmitted from the 0 side to the main board 31 side. That is, the input buffer circuits 105A and 105B together with the input ports constitute irreversible information input means. Even if a circuit in the display control board 80 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side.

The outputs of the output ports 570 and 572 may be output to the display control board 80 as they are, but the output buffer circuits 620 and 62A capable of transmitting signals only in one direction.
, The main board 31 to the display control board 8
One-way signal transmission to 0 can be more reliably performed. That is, the output buffer circuits 620 and 62A together constitute an irreversible information output unit with the output ports.

For example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off the high-frequency signal. The effect is eliminated. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

FIG. 8 is a block diagram showing a signal transmission / reception portion of the main board 31 and the lamp control board 35.
In this embodiment, a game effect LED 28a and game effect lamps 28b, 28 provided outside the game area 7 are provided.
c and lighting / extinguishing of the decorative lamp 25 provided on the game board, and lighting / extinguishing of the prize ball lamp 51 and the ball out lamp 52.
A lamp control command indicating turning off is output from the main board 31 to the lamp control board 35. Also, the start memory display 1
8 and the lamp control command indicating the number of lighting of the gate passage memory display 41 are also transmitted from the main board 31 to the lamp control board 35.
Is output to

As shown in FIG. 8, the lamp control commands relating to the lamp control are output ports (output ports 0, 3) 570, 5 of the I / O port unit 57 in the basic circuit 53.
73. Output port (output port 3) 57
3 outputs 8-bit data, and output port 570 is 1
It outputs a bit INT signal. In the lamp control board 35, a control command from the main board 31 is transmitted to the CPU for lamp control via input buffer circuits 355A and 355B.
351. When the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the input buffer circuits 355A and 355B and the lamp control CPU 351.

In the lamp control board 35, the CPU 351 for lamp control includes a game effect LED 28a, a game effect lamp 28b, and a game effect lamp 28b, which are defined according to each control command.
8c, according to the lighting / extinguishing pattern of the decorative lamp 25,
Game effect LED 28a, game effect lamps 28b, 28
c, output a light-on / light-off signal to the decorative lamp 25; The ON / OFF signal is output to the game effect LED 28a, the game effect lamps 28b and 28c, and the decoration lamp 25. It should be noted that the lighting / extinguishing pattern is determined by the lamp control CPU.
351 is stored in an internal ROM or an external ROM.

On the main board 31, the CPU 56
When there is an unpaid prize ball remaining number in the memory contents of M55, the control command for instructing lighting of the prize ball lamp 51 is output, and the control command is provided upstream of the payout ball passages 186a, 186b on the back of the game board. Ball switch 187a, 187b
When the game ball is no longer detected (see FIG. 3), a control command for instructing lighting of the ball out lamp 52 is output. In the lamp control board 35, each control command is transmitted to the lamp control CPU via input buffer circuits 355A and 355B.
351. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball out lamp 52 according to the control commands. The light-on / light-off pattern is stored in a built-in ROM or an external ROM of the lamp control CPU 351.

Further, the lamp control CPU 351 outputs a light-on / light-off signal to the start storage display 18 and the gate passage storage display 41 in response to the control command.

As the input buffer circuits 355A and 355B, for example, a 74HC54 which is a general-purpose CMOS-IC
0,74HC14 is used. Input buffer circuit 35
5A and 355B are connected to the lamp control board 35 from the main board 31.
The signal can be passed only in the direction toward. Therefore, there is no room for a signal to be transmitted from the lamp control board 35 side to the main board 31 side. For example, even if a circuit in the lamp control board 35 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

In the main board 31, the output port 5
Buffer circuits 620 and 63A are provided outside 70 and 573. As the buffer circuits 620 and 63A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be supplied from the lamp control board 70 to the main board 31 is more reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 63A.

FIG. 9 is a block diagram showing a configuration example of the voice control command signal transmission portion and the voice control board 70 on the main board 31. In this embodiment, according to the progress of the game, the voice control command for instructing the voice output of the speaker 27 provided outside the game area 7 is:
It is output from the main board 31 to the voice control board 70.

As shown in FIG. 9, the voice control command is
The data is output from output ports (output ports 0, 4) 570, 574 of the I / O port unit 57 in the basic circuit 53.
Output port (output port 4) 574 outputs 8-bit data, and output port 570 outputs 1-bit I
An NT signal is output. In the audio control board 70, each signal from the main board 31 is supplied to the input buffer circuit 705A,
The data is input to the CPU 701 for voice control via 705B.
If the audio control CPU 701 does not have an I / O port, the input buffer circuits 705A, 705
An I / O port is provided between B and the voice control CPU 701.

The voice synthesizing circuit 702 using, for example, a digital signal processor is
The sound and the sound effect corresponding to the instruction 01 are generated and output to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the voice control CPU 701 to a level corresponding to the set volume and outputs the output level to the volume amplification circuit 704. The volume amplification circuit 704 outputs the amplified audio signal to the speaker 27.

As the input buffer circuits 705A and 705B, for example, a 74HC54 which is a general-purpose CMOS-IC
0,74HC14 is used. Input buffer circuit 70
5A and 705B can pass signals only in the direction from the main board 31 to the voice control board 70. Therefore, there is no room for a signal to be transmitted from the voice control board 70 side to the main board 31 side. Therefore, even if a circuit in the voice control board 70 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

In the main board 31, the output port 5
Buffer circuits 620 and 67A are provided outside 70 and 574. As the buffer circuits 620 and 67A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be supplied from the voice control board 70 to the main board 31 is more reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 67A.

FIG. 10 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 10, the detection signal from the full tank switch 48 is input to the I / O port 57 of the main board 31 via the relay board 71. The full tank switch 48 is a switch that detects whether the excess ball tray 4 is full. In addition, the ball out switch 187 (187a, 187)
The detection signal from b) is also used for the relay board 72 and the relay board 7.
1 is input to the I / O port 57 of the main board 31.

The CPU 56 of the main board 31 determines whether or not the detection signal from the out-of-ball switch 187 indicates the out-of-ball state.
Alternatively, when the detection signal from the full tank switch 48 indicates the full tank state, a payout control command to instruct payout prohibition is transmitted. When receiving the payout control command instructing the payout prohibition, the payout control CPU 37 of the payout control board 37
1 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. The prize ball count switch 301A is provided in the payout mechanism of the ball payout device 97, and detects a prize ball payout ball actually paid out.

When there is a prize, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
, A payout control command indicating the number of winning balls is input. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal). The payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371
A payout control command is input via the / O port 372a, and the ball payout device 97 is driven in accordance with the payout control command to perform award ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and has at least a RAM.

In the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside 70 and 571. As the buffer circuits 620 and 68A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal inputted from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 is connected to the output port 3
Via 72g, a ball lending number signal indicating the lending ball number is output to the terminal board 160, and a buzzer driving signal is output to the buzzer board 75. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the payout control board 37
Detection signals from the winning ball count switch 301A and the ball lending count switch 301B are input to the relay board 72b via the relay board 72. Ball rental count switch 3
01B is provided in the payout mechanism portion of the ball payout device 97,
Detects the actual loaned ball. Dispensing control board 3
7 is transmitted to the payout motor 289 in the payout mechanism of the ball payout device 97 via the output port 372c and the relay board 72.

The card unit 50 is equipped with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

The balance display board 74 is used to move the card unit 50
In response to the operation of the player, a ball lending switch signal and a return switch signal are given via the payout control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connection state / non-connection state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the payout control board 37. The payout control CPU 3 of the payout control board 37
When the EXS signal to the card unit 50 rises and the fall of the BRQ signal from the card unit 50 is detected, the payout motor 289 drives the payout motor 289 to pay out a predetermined number of loaned balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, if the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed.

As described above, all signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31.

In this embodiment, the case where the card unit 50 is provided is taken as an example. However, the present invention can be applied to a case where a game ball is lent according to the amount of money when a coin is inserted. Further, in this embodiment, a case where a game ball is lent is taken as an example, but the present invention can be applied to a case where points are added.

In this embodiment, at least the main substrate 3
1 and the RAM in the payout control board 37 are backed up by a backup power supply. That is, even if the power supply to the gaming machine is stopped, the contents of the RAM are stored for a predetermined period. When detecting a drop in the power supply voltage, each CPU performs a predetermined process, and then enters a power recovery wait state. When the power is turned on, each CPU
If the data is stored in the memory, the state before the power is turned off is restored based on the stored data.

Further, as described above, the payout control board 3
7. The main board 31 for sending commands to the display control board 80, the lamp control board 35, and the voice control board 70
An INT signal is output from each output port (output port 0) 570 to each electric component control board. In this case, for example,
The output port 570 has an 8-bit configuration, where bit 0 is an INT signal to the payout control board 37, bit 1 is an INT signal to the display control board 80, and bit 2 is a lamp control board 3
The INT signal to bit 5, bit 3 is the I signal to voice control board 70
Used for outputting the NT signal.

FIG. 11 is a block diagram showing an example of a configuration around the CPU 56. As shown in FIG. 11, a voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) is output to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56.
It is connected to the. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of various DC power supplies used by the gaming machine and detects a drop in the power supply voltage. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value falls below a predetermined value, a low-level voltage drop signal is generated. VSL
Is the largest DC voltage used in gaming machines, and is +30 V in this example. Therefore, the CPU 56
Can confirm the occurrence of power interruption by interrupt processing. In this embodiment, the first power supply monitoring circuit is mounted on a power supply board described later.

FIG. 11 also shows a system reset circuit 65, but in this embodiment, the system reset circuit 65 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, the reset IC 651
When the power is turned on, the output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level after the predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage of VSL, which is the same power supply voltage as the power supply voltage monitored by the first power supply monitoring circuit, and sets the voltage value to a predetermined value (the first power supply monitoring circuit outputs a voltage drop signal). When the voltage falls below the power supply voltage value), a low-level voltage drop signal is generated. Accordingly, the CPU 56 performs a predetermined power supply stop processing in response to the voltage drop signal from the first power supply monitoring circuit, and then performs a system reset. In this embodiment, the reset signal and the voltage drop signal from the second power supply monitoring circuit are the same signal.

As shown in FIG. 11, the reset IC 651
Is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. When the input to the clear terminal goes low, the counter IC 941 counts the clock signal from the oscillator 943.
The Q5 output of the counter IC 941 is output to the NOT circuit 9
45, 946 and input to the NAND circuit 947. The Q6 output of the counter IC 941 is input to a clock terminal of a flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The other input of the OR circuit 949 is connected to the NAND circuit 9.
The output of 47 is introduced via NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, two reset signals (low-level signals) are supplied to the reset terminal of the CPU 56 when the power is turned on.
Starts operation reliably.

Then, for example, the detection voltage of the first power supply monitoring circuit (the voltage at which the voltage drop signal is output) is set to +
22 V, and the detection voltage of the second power supply monitoring circuit is +9 V. In such a configuration, since the first power supply monitoring circuit and the second power supply monitoring circuit monitor the voltage of the same power supply VSL, the timing at which the first voltage monitoring circuit outputs the voltage drop signal The difference between the timings at which the second voltage monitoring circuit and the second voltage monitoring circuit output the voltage drop signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop processing in response to the voltage drop signal from the first power supply monitoring circuit until the power supply stop processing is completely completed.

In this example, the first detection condition that the first power supply monitoring means outputs a detection signal is that the +30 V power supply voltage has dropped to +22 V, and the second power supply monitoring means outputs the detection signal. The second detection condition to be output is that the +30 V power supply voltage has dropped to +9 V.
However, the voltage value used here is an example,
Other values may be used.

However, although the monitoring range is narrowed, the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit is +
It is also possible to use a 5V power supply voltage. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

While power is not supplied from the + 5V power supply which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are retained even if the power supply to the gaming machine is cut off. Is saved. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to the normal operation state. At that time, since the necessary data is stored in the backup RAM, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

In FIG. 11, when the power is turned on, the CPU 5
6 shows a configuration in which a reset signal (low-level signal) is applied twice to the reset terminal. However, in the case of using a CPU in which reset is surely released even if the reset signal rises only once, , Reference numerals 941 to 9
The circuit element indicated by 49 is unnecessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

CPU 56 used in this embodiment
Incorporates an I / O port (PIO) and a timer / counter circuit (CTC). PIO is PB0-PB
It has a port of 3 4 bits and 1 byte of PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set for both input and output. However, in this embodiment, no built-in PIO is used. In that case, for example, all ports are set to the input mode, and all ports are connected to the ground level. When power is turned on, P
IO is automatically set to input mode.

FIG. 12 is a block diagram showing a configuration example of a power supply board 910 of a gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the audio control board 70, the lamp control board 35, and the payout control board 37, and each of the electric component control boards in the gaming machine and Generates voltages used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21
V, + 12V DC and + 5V DC. Also,
The capacitor 916 serving as a backup power supply is DC + 5
V, that is, charged from a power supply line for driving an IC or the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 22V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
5 is connected to, for example, a relay board, from which electric power of a voltage required for each electric component control board and mechanism components is supplied. A power switch 918 for stopping and starting power supply to the gaming machine is provided on the input side of the transformer 911.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is provided with an electric power so as to be able to hold a storage state in a backup RAM (power-backed-up RAM, that is, storage means that can be in a storage state) when the power supply to the gaming machine is cut off. Backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 has the first
The power supply monitoring IC 902 constituting the power supply monitoring circuit of FIG. The power supply monitoring IC 902 detects the occurrence of power interruption by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), a voltage drop signal is output assuming that power supply is cut off. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after conversion from AC to DC, is used. The voltage drop signal from the power supply monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect a power-off is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Therefore, the monitoring range can be extended for the voltage required by the CPU. Therefore,
More precise monitoring can be performed. Furthermore, when VSL (+30 V) is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, when monitoring the voltage of the + 30V power supply,
The drop can be detected at a stage before + 12V generated after the generation of 0V starts to fall. Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state where the switch output is not detected.

Since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the first power supply monitoring circuit supplies a voltage drop signal to the plurality of electric component control boards. Can be. Regardless of how many electric component control boards require a voltage drop signal, it is sufficient that only one first power supply monitoring means is provided, so that each electric component control means in each electric component control board performs a return control described later. Doing so does not add much to the cost of the gaming machine.

In the configuration shown in FIG. 12, the detection output (voltage drop signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control) via buffer circuits 918 and 919. Transmitted to the board 37). For example, one detection output is transmitted to the relay board,
The same signal may be distributed from the relay board to each electric component control board. Further, a buffer circuit may be provided according to the number of substrates requiring a voltage drop signal.

Next, the operation of the gaming machine will be described. FIG.
3 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56
First, necessary initial settings are performed (step S1).

Then, it is confirmed whether or not data protection processing (for example, NMI processing for power failure occurrence such as addition of parity data) of the backup RAM area has been performed when the power is turned off (step S2). In this embodiment, when an unexpected power failure occurs, a process for protecting data in the backup RAM area is performed. The case where such protection processing has been performed is regarded as backup. After confirming that there is no backup, the CPU 56 executes an initialization process (steps S2 and S3). In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off.
For example, if "55H" is set in the backup flag area, it means that there is a backup (on state),
If a value other than “55H” is set, it means that there is no backup (off state). “55H” set in the backup flag area is data set when the data protection processing of the backup RAM area is completed in the power failure occurrence NMI processing.
This is a parity code based on the data of the area.

If the backup data exists in the backup RAM area, the CPU 56
A data check (for example, a parity check) of the M area is performed (step S4). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power-off, the initialization processing executed at the time of power-on, not at the time of restoration from power failure, is executed (steps S5 and S3).

If the check result is normal, the CPU 56
Performs a game state restoring process for returning the internal state to the state when the power is turned off (step S6). As shown in FIG.
When the value of the backup flag is set to “55H” and the check result is normal, the game state restoring process of step S6 is executed. Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the program returns to the address (step S7).

Execution of normal initialization processing (step S3)
Is completed, the process shifts to a loop process in which the monitoring of the timer interrupt flag (step S9) is confirmed in the main process. In the loop, a display random number update process (step S8) is also performed.

In this embodiment, step S2
The backup area is checked in step S4 after the backup data is checked in step S4 if the backup data exists. However, after the backup area check result is confirmed to be normal in step S4. ,
The presence or absence of backup data may be confirmed. Alternatively, whether to execute the power failure recovery process may be determined by confirming whether there is backup data or checking the backup area.

Also, for example, at the time of the parity check (step S4) when determining whether or not to execute the power failure recovery processing, that is, when determining whether or not to restore the game state, the RAM data stored at the time of the parity check is determined. According to the special process flag, etc. and the data of the number of memorized start winnings in the game machine, the game machine is in the game standby state (the symbol is not fluctuating,
If it is confirmed that the game is not being changed reliably and that there is no start winning memory, the initialization process may be executed without performing the game state restoration process.

FIG. 15 is a flowchart showing the initial setting process in step S1. In the initial setting process, C
The PU 56 first sets interrupt prohibition (step S1).
a). When the interrupt is set to be prohibited, the CPU 56 sets the interrupt mode to the interrupt mode 2 (step S1b), and sets the stack pointer designated address to the stack pointer (step S1c). Then, the CPU 56 initializes the built-in device register (step S1d). In addition, CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits)
Is initialized (step S1e), and the RAM is set in an accessible state (step S1f).

CPU 5 used in this embodiment
6 has the following three types of modes as maskable interrupt (INT) modes. When an interrupt that can be masked occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

Interrupt mode 0: The built-in device that has issued the interrupt request receives an RST instruction (1 byte) or a CALL instruction (3 bytes).
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. Upon reset, CPU 56 automatically switches to interrupt mode 0
become. Therefore, when it is desired to set the mode to the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the mode to the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
In this mode, the camera always jumps to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is the interrupt address. Mode. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary (albeit skipped) even address. Each built-in device has a function of sending an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to set an interrupt process at an arbitrary position in a program. Will be possible. Further, unlike the interrupt mode 1, it is easy to prepare an interrupt process for each interrupt occurrence factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S1b of the initial setting process.

FIG. 16 shows a normal initialization process (step S).
It is a flowchart which shows the process of 3). As shown in FIG. 16, in the initialization process, the RAM is cleared (step S3a). Then, based on the address value of the work area initial setting table, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a payout command storage pointer, etc.) is initialized. An initial value setting process for setting a value (step S3b) is performed. Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S3).
c). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited (see FIG. 15) in the initial setting process (step S1), the interrupt is permitted before the initialization process is completed (step S3d).

Therefore, in this embodiment, the CPU 56
Is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2 ms
Is set to Then, as shown in FIG. 17, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S12).

When the CPU 56 detects in step S9 that the timer interrupt flag has been set, it resets the timer interrupt flag (step S1).
0), a game control process is executed (step S11). According to the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process.
The game control process may be executed by a timer interrupt process.

As described above, in this embodiment, the interrupt mode 2 is set in the CPU 56 having a built-in CTC or PIO in the initial setting process. Accordingly, a periodic timer interrupt process using the built-in CTC can be easily realized. Further, the timer interrupt processing can be set at an arbitrary position on the program. Further, switch detection processing using the built-in PIO can be easily realized by interruption processing. As a result, effects such as simplification of the program configuration and reduction in the number of program development steps can be obtained.

Further, in this embodiment, it is determined whether or not the power supply is restored to the state at the time of power failure based on the presence or absence of backup data. Therefore, when the power is turned on, for example, when the power is restored after a power failure, it is possible to determine whether or not to restore the state at the time of the power failure according to the contents of the backup data storage area.

Further, it is determined whether or not the power is restored to the power-off state according to the state of the backup data. Therefore, when the power is turned on when the power is restored after a power failure or the like, the contents of the backup data storage area are restored. It is possible to determine whether to restore the power-off state according to the state.

FIG. 18 is a flowchart showing the game control processing in step S11. In the game control process,
The CPU 56 firstly receives the gate sensor 12, the starting port sensor 17, and the count sensor 23 through the switch circuit 58.
And the state of the winning opening switches 19a and 24a,
It is determined whether or not there is a prize for each winning port or prize device (switch processing: step S21).

Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

Next, a process for updating each counter indicating a random number for determination, such as a random number for big hit determination used in game control, is performed (step S23). The CPU 56 further includes:
A process for updating a display random number such as a random number for determining the type of stop symbol is performed (step S24).

Further, the CPU 56 performs a special symbol process (step S25). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Also, a normal symbol process is performed (step S26). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

The CPU 56 sets a control command to be sent to the payout control board 37 or the like in a predetermined area of the RAM 55 and sends the control command (command control process: step S27).

Next, the CPU 56 performs a data output process of outputting data such as jackpot information, start information, and probability variation information supplied to the hall management computer (step S29).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in response to the drive command, and brings the variable winning ball device 15 or the open / close plate 20 into an open state or a closed state.

Further, the CPU 56 sets the number of prize balls based on the detection output of the switches 17, 23, 19a and 24a for detecting a winning in each winning opening (step S31). Specifically, a payout control command is output to the payout control board 37 in response to the winning detection. Dispensing control board 37
The payout control CPU 371 mounted on the device drives the ball payout device 97 in accordance with the payout control command.

As described above, the main processing includes the processing for determining whether or not to shift to the game control processing.
Since a flag is set to determine whether or not to shift to the game control process in the timer interrupt process based on the timer interrupt that is periodically generated by the 56 internal timers, all the game control processes are reliably executed. Is done. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

Here, the CPU 56 of the main board 31
Is executed in response to a flag set in a timer interrupt process based on a timer interrupt that is periodically generated by an internal timer of the CPU 56, but the signal is periodically (for example, every 2 ms). A hardware circuit which generates the signal may be provided, a signal from the circuit may be introduced to an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control process based on the interrupt signal may be set. Good.

Even in such a configuration, the flag is not determined until all the game control processes have been executed, so that execution of all the processes in the game control process is guaranteed to be completed. You.

FIG. 19 shows a state in which the main board 31 and the payout control board 3
FIG. 9 is an explanatory diagram showing an example of a command form of a payout control command sent to the control unit 7; In this embodiment, the payout control command has a 2-byte configuration, and the first byte is MODE.
(Command classification), and the second byte indicates EXT (command type). The command form shown in FIG. 19 is an example, and another command form may be used.
The first bit (bit 7) of MODE data is always "1"
And the first bit (bit 7) of the EXT data is always "0".

FIG. 20 shows the relationship between an 8-bit control signal (in this case, a payout control signal) and an INT signal (in this case, a payout control signal INT) which constitute a control command for each electric component control means. It is a timing chart. FIG.
As shown in FIG. 0, when a period indicated by A elapses after MODE or EXT data is output to the output port (port 1 in the case of the payout control signal), the CPU 56
Turns on an INT signal which is a signal indicating data output. When the period indicated by B has elapsed therefrom, the INT signal is turned off. Further, when there is data to be transmitted next, that is, after the MODE data is transmitted, the data of the second byte is transmitted to the output port after a period indicated by C. Regarding the data of the second byte, the periods of A and B are the same as the case of the first byte.

The period A is a period for the CPU 56 to prepare for sending a command, that is, a period required for processing for setting a send command in the buffer, and also to a control signal line (a payout control signal line in the case of a payout control signal). This is the period for data stabilization. The period of B is INT
This is a period for signal stabilization. And the period of C is
This is a period in which the electric component control means (the payout control means in the case of the payout control signal) is set so as to be able to reliably take in data. In the period C, the data on the signal line does not change. That is, the data output is maintained until the period C elapses.

As described later, in this embodiment, a payout control command to the payout control board 37, the display control board 8
The display control command to 0, the lamp control command to the lamp control board 35, and the voice control command to the voice control board 70 are transmitted using the same routine (common module). Therefore, the period of C, that is, the period from when the INT signal relating to the first byte is turned off to when the transmission of the second byte data is started, is the reception processing time in the electric component control means which takes the longest time for the command reception processing It is set to be longer than

Each electric component control means changes the state of the INT signal from the on state (high level) to the off state (low level).
Is detected, the process of capturing 1-byte data is started by, for example, an interrupt process.

Since the period C is longer than the reception processing time of the electric component control means which takes the longest time for the command reception processing, the game control means controls the command transmission processing for each electric component control means by the common module. Also, any of the electric component control means can reliably receive the control command from the game control means.

In this embodiment, the CPU 56 sets (1
1.776 / 2) MHz. Specifically, 138 states (1 state = [2 / 11.776] μs) are applied in the period A, 82 states are applied in the period B, and 251 states are applied in the period C. Therefore, the period of C is longer than the period of A. That is, the CPU 56 is ready to transmit the next data after a predetermined period has elapsed after executing the INT signal output processing, but during the predetermined period (period C), the CPU 56 transmits data before the INT signal output processing. It is longer than the period (period A) from when the output of the INT signal is started. As described above, the period A is a stabilization period of the command signal line, and the period C is a period for securing the time required for the receiving side to capture data. Therefore, by making the period A shorter than the period C, it is possible to obtain the effect that the receiving-side electric component control means can reliably receive the command, and it is necessary to complete the transmission of one command. There is also an effect that the period is shortened.

FIG. 21 is an explanatory diagram showing an example of the content of the payout control command. In the example shown in FIG.
Command F of ODE = FF (H) and EXT = 00 (H)
F00 (H) is a payout control command for specifying a payable state. MODE = FF (H), EXT = 01
The command FF01 (H) of (H) is a payout control command for specifying a payout stop state. MODE = F0
The command F0XX (H) of (H) is a payout control command for specifying the number of winning balls. "XX" which is EXT indicates the number of payouts.

When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout control means stops the prize ball payout and the ball lending.
When the payout control command of (H) is received, it becomes possible to pay out prize balls and lend a ball. Further, when a payout control command specifying the number of winning balls is received, prize ball payout control according to the number specified by the received command is performed.

Note that the payout control command is sent only once so that the payout control means can recognize it. Recognizable means that the INT signal is in the ON state in this example, and is transmitted only once so that it can be recognized. In this example, the INT signal is sent to the first and second bytes of the payout control signal. Accordingly, the INT signal is turned on only once.

Since one command (command information) has a 2-byte structure, the influence of noise can be reduced. In other words, when one command is composed of one byte of command data, even if data is garbled due to noise, it may be received as it is and erroneous control may be performed. If so, the control based on the command is started only when both are correctly received, so that the possibility of malfunction can be reduced as compared with the case of the 1-byte configuration.

FIG. 22 is an explanatory diagram showing an example of the contents of the display control command. Display control commands are MODE and E
This is a 2-byte configuration of XT. In the example shown in FIG.
Commands 8000 (H) to 8022 (H), 8100
(H) to 8122 (H) are display control commands for specifying a variation pattern of the special symbol in the variable display section 9 for variably displaying the special symbol. Note that the command for designating the variation pattern also serves as the variation start instruction. Command 88
XX (X = arbitrary value of 4 bits) is a display control command related to a variation pattern of a normal symbol variably displayed on the variable display 10. The command 89XX is a display control command for designating a stop symbol of a normal symbol. Command 8
AXX (X = arbitrary value of 4 bits) is a display control command for instructing to stop variable display of a normal symbol.

Commands 91XX, 92XX and 93X
X is a display control command for designating a left middle right stop symbol of a special symbol. The command A0XX is a display control command for instructing to stop the variable display of the special symbol.
The command BXXX is a display control command sent from the start of the big hit game to the end of the big hit game. The commands C000 and EXXXX are display control commands relating to the display state of the variable display unit 9 irrespective of the fluctuation of special symbols and the jackpot game. Display control board 80
When receiving the above-mentioned display control command from the game control means of the main board 31, the display control means changes the display state of the variable display section 9 and the variable display 10 according to the contents shown in FIG.

FIG. 23 is an explanatory diagram showing an example of the contents of the lamp control command. Lamp control command is also MODE
And EXT. In the example shown in FIG. 23, commands 8000 (H) to 8022 (H), 810
0 (H) to 8122 (H) are lamp control commands for designating a lamp / LED display control pattern corresponding to a special symbol variation pattern on the variable display unit 9. The command A0XX (X = any value of 4 bits) is
This is a lamp control command for instructing a lamp / LED display control pattern when stopping the variable display of a special symbol. The command BXXX is a lamp control command for instructing a lamp / LED display control pattern from the start of the big hit game to the end of the big hit game. And the command C000 is
This is a lamp control command for instructing a lamp / LED display control pattern during a customer waiting demonstration.

The commands 8XXX, AXXX, BX
XX and CXXX are ramp control commands sent from the game control means according to the progress of the game. Upon receiving the above-described lamp control command from the game control means on the main board 31, the lamp control means changes the display state of the lamp / LED according to the contents shown in FIG.

The command E0XX is the start storage display 18
Is a lamp control command indicating the number of lights. For example,
The lamp control means operates the "X
The number of indicators specified by "X" is turned on. The command E1XX is a lamp control command indicating the number of lighting of the gate passage storage display 41. For example, the lamp control means turns on the number of indicators designated by “XX” in the gate passage storage indicator 41.
That is, these commands are commands for instructing control of the light emitter provided for notifying the information of the number of held units. In addition, the command regarding the lighting number of the start storage display 18 and the gate passage storage display 41 may be configured to indicate the increase or decrease of the lighting number.

Commands E200 and E201 are lamp control commands relating to the display state of the prize ball lamp 51, and commands E300 and E301 are lamp control commands relating to the display state of the ball out lamp 52. The ramp control means sends “E2” from the game control means of the main board 31.
01 ”when the lamp control command is received.
The display state of No. 1 is a predetermined display state where there is a prize ball remaining, and when a lamp control command of “E200” is received, the display state of the prize ball lamp 51 is a display state where there is no prize ball remaining. State. Further, when the lamp control command of “E300” is received from the game control means of the main board 31, the display state of the out-of-ball lamp 52 is changed to a display state in which a ball is present, and when the “E301” lamp control command is received, the out-of-ball lamp 52 Is set to the display state in which the ball is out. That is, the command E20
0 and E201 are commands indicating that a light emitting body provided for notifying a player or the like that there is a game ball of a non-winning ball is controlled, and commands E300 and E201 are provided.
Reference numeral 301 denotes a command indicating that a light emitter provided for notifying a player or a game clerk that the supply ball has run out is controlled.

The command E400 is issued when the gaming machine is turned on or when a specific game state (high-probability state or time-saving state, in this example, high-probability state) changes to a normal state (low-probability state or non-time-saving state, in this example, low-probability state). This is a lamp control command for instructing a lamp / LED display control pattern at the time of transition to (state). The command E401 is a lamp / LED display at the time of transition from a normal state (low-probability state or non-time-saving state, in this example, low-probability state) to a specific game state (high-probability state or time-saving state, in this example, high-probability state). This is a lamp control command for instructing a control pattern. Command E402 is
This is a lamp control command for instructing a lamp / LED display control pattern when an error generated during the big hit game is released. The command E403 is a lamp control command for instructing a lamp / LED display control pattern when an error occurs in the count switch 23.
That is, those commands are commands instructing that the gaming state is notified by the light emitting body. In this embodiment, when the lamp control means receives a command instructing to notify the gaming state, the decoration lamp 25,
Game effect LED 28a and game effect lamp 28b, 2
Lighting / extinguishing control for notifying the gaming state is performed using a part or all of 8c. Decorative lamp 2
5. Game effect LED 28a and game effect lamp 28
Each of b and 28c may be constituted by a group of a plurality of light emitters. In this case, the gaming state is notified by using a part of the decorative lamp 25, the game effect LED 28a, and the game effect lamps 28b and 28c. To do is to
For example, it also means that a part of the plurality of light emitters constituting the decorative lamp 25 may be used.

FIG. 24 is an explanatory diagram showing an example of the content of the voice control command. Voice control commands are MODE and E
This is a 2-byte configuration of XT. In the example shown in FIG.
The command 8XXX (X = arbitrary value of 4 bits) is a voice control command for designating a sound generation pattern during the fluctuation period of the special symbol. The command BXXX (X = arbitrary value of 4 bits) is a voice control command for designating a sound generation pattern from the start of the big hit game to the end of the big hit game. Other commands are voice control commands that are not related to special symbol fluctuations and big hit games. When the voice control means of the voice control board 70 receives the above-described voice control command from the game control means of the main board 31, FIG.
The audio output state is changed according to the contents shown in FIG.

FIG. 25 is a flowchart showing an example of a special symbol processing program executed by the CPU 56. The special symbol process shown in FIG.
Is a specific process of step S25 in the flowchart of FIG. When performing the special symbol process, the CPU 56 performs any one of steps S300 to S309 illustrated in FIG. 25 according to the internal state after performing the variation reduction timer subtraction process (step S310).

In the variation reduction timer subtraction process of step S310, it is determined whether or not a condition for shortening the variation time of the special symbol is satisfied (for example, a predetermined time from when the start winning is detected to when the process based on the starting winning is executed). Is performed to decrement the fluctuation reduction timer for confirming whether or not the time has elapsed. Then, steps S300 to S309
In each of the above processes, the following processes are executed.

Special symbol change waiting process (step S30)
0): The start winning port 14 (in this embodiment, the winning port of the variable winning ball device 15) is hit and the start port sensor 17 is turned on. When the starting port sensor 17 is turned on, the starting winning memory number is increased by + if the starting winning memory number is not full.
1 and a random number for jackpot determination is extracted.

Special symbol determination processing (step S301):
When the state in which the variable display of the special symbol can be started, the number of start winning prize stored is confirmed. If the starting prize memory number is not 0,
It is determined whether to make a big hit or an out according to the value of the extracted big hit determining random number.

Stop symbol setting processing (step S302):
The stop symbol of the left and right middle symbols is determined.

Reach operation setting processing (step S30)
3): Whether or not to perform the reach operation is determined according to the value of the reach determination random number, and the fluctuation period at the time of reach is determined according to the value of the reach type determination random number.

All symbols change start processing (step S30)
4): In the variable display section 9, control is performed so that all symbols start to change. At this time, with respect to the display control board 80,
A control command for instructing the final left and right middle stop symbol and the variation mode is transmitted. Upon completion of the processing, the internal state (process flag) is updated so as to shift to step S305.

All symbols stop waiting processing (step S30)
5): Control is performed so that all symbols displayed on the variable display section 9 are stopped after a predetermined time has elapsed. And
If the stop symbol is a combination of big hit symbols, the internal state (process flag) is updated so as to shift to step S306. If not, the internal state is updated to shift to step S300.

Opening process of opening the special winning opening (step S30)
6): Control for opening the special winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening. Also, a big hit flag (a flag indicating that a big hit is being made) is set. Upon completion of the process, the internal state (process flag) is updated so as to shift to step S307.

Processing during opening of the special winning opening (step S30)
7): Control for transmitting display control command data for the special winning opening round display to the display control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. When the final closing condition of the special winning opening is satisfied, the internal state is updated to shift to step S308.

Specific area effective time processing (step S30)
8): The presence or absence of passage of the V count switch 22 is monitored, and a process of confirming that the big hit game state continuation condition is satisfied is performed. If the condition of the jackpot game state continuation is satisfied and there is still a remaining round, the internal state is changed to step S30.
Update to move to 6. If the big hit game state continuation condition is not satisfied within the predetermined effective time, or if all rounds have been completed, the internal state is updated to shift to step S309.

Big hit end processing (step S309): A display for notifying the player that the big hit gaming state has ended is performed. When the display is completed, the internal state is updated so as to shift to step S300.

As described above, when a ball is hit in the starting winning opening 14, the CPU 56 determines whether or not to make a big hit or a miss, a stop symbol, a reach mode, a probable change in the special symbol process. However, a control command such as a display control command according to the determination is transmitted to an electric component control unit such as a display control unit. For example, in the display control means, display control of the variable display unit 9 is performed according to a display control command from the main board 31. In addition, control commands are sent to the display control board 80, the lamp control board 35, and the voice control board 70 in accordance with the progress of the game. The command transmission method is as described above.

FIG. 26 is a flowchart showing a portion related to the winning ball control of the switch process (step S21) in the game control process shown in FIG. In the switch processing, the CPU 56 sets an out-of-ball state flag when the out-of-ball switch is detected by the out-of-ball switch 187 (steps S121 and S122). When it is detected that the ball is not out of ball by the out-of-ball switch 187, the out-of-ball flag is reset (steps S121 and S12).
3).

Next, when the lower tray full level is detected by the full level switch 48, the full level flag is set (steps S124 and S125). When it is detected that the lower plate is not full by the full tank switch 48, the full tank flag is reset (steps S124 and S126).

Further, when it is detected that the count switch 23 is turned on, the 15 counter is incremented by 1 (steps S131 and S132), and the winning opening switches 19a and 24a are set.
Is detected, the ten counters are incremented by one (steps S133 and S134). When the start port switch 17 is detected to be on, the six counters are incremented by one (steps S135 and S136).

In this embodiment, 15 prize balls are paid out for a prize passing through the special winning opening, and 6 prize balls are paid out for a prize passed through the starting winning opening 14. It is assumed that ten prize balls are paid out for the prize through the prize ball device 24 and the prize ball device. The 15 counter is a counter for counting the number of winnings to the special winning opening, the 10 counter is a counter for counting the number of winnings to the normal winning opening, and the 6 counter is a winning for the starting winning opening. This is a counter for counting the number.

FIG. 27 is a flowchart showing an example of the winning ball signal processing (step S31) in the game control processing shown in FIG. In this example, in the winning ball signal processing, the CPU 56 first checks whether or not the payout is stopped (step S201). The withdrawal stop state is
This is the state after the command to specify the payout stop state is sent to the payout control board 37. If you are not in the withdrawal state,
It is confirmed whether or not the above-mentioned ball-out state flag or full tank flag has been turned on (step S202).

When either of them changes to the ON state,
The command transmission table for the payout stop state designation is set (step S203). The command transmission table will be described later in detail. Step S202
In, when one of the flags is already in the ON state and the other flag is in the ON state, the command transmission table is not set (step S203).

If the payout is stopped, it is checked whether both the out-of-ball state flag and the full tank flag have been turned off (step S204). When both are turned off, a command transmission table relating to the payout stop release designation is set (step S205).

Next, the CPU 56 controls to set a payout control command relating to the number of winning balls according to the winning in the command transmission table. First, the values of the 15 counters are checked (step S211). As mentioned above, 1
The five counters are counted up when the game ball wins the big winning opening and the count switch 23 is turned on. Fifteen
If the value of the number counter is not 0, a command transmission table relating to the fifteen winning ball number instructions is set (step S212). Further, the value of the 15 counters is decremented by one (step S213).

If the value of the 15 counter is 0, the value of the 10 counter is checked (step S215). As described above, the ten counters are counted up when a game ball wins a winning opening and the winning opening switches 19a and 24a are turned on. If the value of the ten counter is not 0, the command transmission table for the ten winning ball number instructions is set (step S216). Further, the value of the 15 counter is decremented by one (step S217).

If the value of the ten counter is 0, the value of the six counter is checked (step S221). As described above, the six counters are counted up when the game ball wins the starting winning port and the starting port switch 17 is turned on. If the value of the six counter is not 0, the command transmission table for the six winning ball number instructions is set (step S222). Also, the value of the six counters is-
1 (step S223).

As described above, when the payout control command is to be output from the game control means to the payout control board 37, the command transmission table is set. FIG.
(A) is an explanatory view showing a configuration example of a command transmission table. One command transmission table is composed of three bytes, and INT data is set in the first byte. In the command data 1 of the second byte, MODE data of the first byte of the payout control command is set. In the command data 2 of the third byte, EXT data of the second byte of the payout control command is set.

Although the EXT data itself may be set in the command data 2 area, the command data 2
May be set to data for specifying an address of a table in which EXT data is stored. In this embodiment, bit 7 of command data 2
If (work area reference bit) is 0, it indicates that the EXT data itself is set in the command data 2. Such EXT data is data in which bit 7 is 0. If the work area reference bit is 1, the other 7 bits indicate an offset for specifying an address of a table in which EXT data is stored.

In this embodiment, a plurality of command transmission tables are prepared, and the command transmission table to be used is designated by a pointer. Also, a plurality of command transmission tables are used as a ring buffer. Therefore, CP
U56 sets the INT data, the command data 1 and the command data 2 in the command transmission table pointed to by the write pointer in the winning ball signal processing. Then, the value of the write pointer is updated. Since one command transmission table has a 3-byte configuration, specifically, the write pointer value is +3.

In the process shown in FIG. 27, only one command transmission table setting process relating to one payout control command is performed in one process. However, since a plurality of command transmission tables are provided, a plurality of command transmission tables are provided. You may comprise so that a table setting process may be performed. For example, when a plurality of winnings are stored in the 15 counter, the 10 counter, and the 6 counter, a plurality of command transmission table setting processes may be performed by one winning ball signal processing.

Although the payout control command will be described here, the display control command, the lamp control command, and the voice control command are also transmitted in FIG.
INT data, command data 1 and command data 2 are set in a command transmission table as shown in FIG. At that time, the INT data, the command data 1 and the command data 2 are set in the command transmission table pointed to by the write pointer.

FIG. 28B is an explanatory diagram showing an example of the configuration of INT data. Bit 0 in the INT data indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that a payout control command should be sent. Therefore, the CPU 56
In the winning ball signal processing, "01" is added to the INT data.
(H) ”is set.

The bits 1, 2, 3 of the INT data
Are bits indicating whether or not to transmit a display control command, a lamp control command, and a voice control command, respectively. When it is time to transmit those commands, the CPU 56 performs special symbol process processing or the like. The INT data, command data 1 and command data 2 are set in the command transmission table indicated by the pointer. When these commands are transmitted, the corresponding bit of the INT data is set to "1", and MODE data and EX data are added to command data 1 and command data 2.
T data is set.

FIG. 29 is a flowchart showing an example of the command control process (step S27) in the game control process shown in FIG. The command control process is a process including a command output process and an INT signal output process. In the command control process, the CPU 56 first
The address of the command transmission table (contents of the read pointer) is saved in a stack or the like (step S231). Then, the INT data of the command transmission table pointed to by the read pointer is loaded into the argument 1 (step S23).
2). Argument 1 is input information for a command transmission process described later. Further, the address indicating the command transmission table is incremented by 1 (step S233). Therefore, the address indicating the command transmission table matches the address of the command data 1.

Then, the CPU 56 sets the command data 1
Is read and set as argument 2 (step S234).
The argument 2 also becomes input information for a command transmission process described later. Then, a command transmission processing routine is called (step S235).

FIG. 30 is a flowchart showing a command transmission routine. In the command transmission routine,
First, the CPU 56 sets the data set in the argument 1, that is, the INT data, in the work area determined as the comparison value (step S <b> 251). Then
The number of transmissions = 4 is set in the work area determined as the number of processes (step S252). Then, port 1 for outputting the payout control signal (output port 571)
Is set to the IO address (step S2).
53).

Next, the CPU 56 shifts the comparison value one bit to the right (step S254). It is determined whether or not the carry bit has become 1 as a result of the shift processing (step S255). The fact that the carry bit has become 1 means that the rightmost bit in the INT data is “1”.
It means that it was. In this embodiment, four shift processes are performed. For example, when it is specified that a payout control command should be sent, the carry bit becomes 1 in the first shift process.

When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (that is, MODE data) is output to the address set as the IO address (step S2
56). When the first shift processing is performed, since the address of port 1 (output port 571) is set in the IO address, MODE data of the payout control command is output to port 1 after all.

Next, the CPU 56 sets the IO address to 1
While adding (step S257), 1 is subtracted from the number of processes (step S258). If port 1 is indicated before the addition, the address of port 2 (output port 572) is set as the IO address by the addition processing for the IO address. Port 2 (output port 572)
Is a port for outputting a display control command.
Then, the CPU 56 checks the value of the number of processes (step S259). If the value is not 0, the process proceeds to step S2.
Return to 54. The shift process is performed again in step S254.

In the second shift processing, the value of bit 1 in the INT data is pushed out, and the carry flag becomes "1" or "0" according to the value of bit 1. Therefore,
A check is made as to whether it is specified that a display control command should be sent. Similarly, in the third and fourth shift processes, it is checked whether or not it is specified that the ramp control command and the voice control command should be transmitted. As described above, when each shift process is performed, the IO address corresponding to the command (payout control command, display control command, lamp control command, voice control command) set by the shift process is set in the IO address. Have been.
Therefore, when the carry flag becomes "1", a control command is sent to the corresponding output port (port 1 to port 4). That is, with one common module,
Transmission processing of a control command to each electric component control means can be performed.

In this way, since it is determined which control control unit should output the control command only by the shift processing, it is determined which control control unit should output the control command. Processing has been simplified.

Next, the CPU 56 reads the contents of the argument 1 storing the INT data before the start of the shift processing (step S260), and transfers the read data to the port 0.
(Output port 570) (step S26).
1). For the INT data, steps S251 to S259
Control commands (payout control commands,
The bit corresponding to the output bit of the INT signal according to the display control command, the lamp control command, and the voice control command is “1”. Therefore, port 1 to port 4
The INT signal corresponding to the control command (payout control command, display control command, lamp control command, voice control command) output to any of the above is turned on.

Next, the CPU 56 sets a predetermined value in the weight counter (step S262), and decrements by one until the value becomes 0 (steps S263, S26).
4). This process is a process for setting the period B shown in FIG. When the value of the wait counter becomes 0, clear data (00) is set (step S26).
5), and outputs the data to port 0 (step S2)
66). Therefore, the INT signal is turned off. Then, a predetermined value is set in the weight counter (step S2).
62), and decrement by 1 until the value becomes 0 (steps S268 and S269). This process is a process for setting the period C shown in FIG.

Therefore, the value set in the wait counter in step S267 is such that the period of C is a period long enough for all the electric component control means to receive the control command to reliably execute the command receiving process. Value. The value set in the wait counter is such that the period of C is
This value is longer than the time required for the processing in steps S251 to S259.

As described above, the MODE data of the first byte of the control command is transmitted. Therefore, CPU5
No. 6 adds 1 to the value indicating the command transmission table in step S236 shown in FIG. Therefore, the area of the command data 2 in the third byte is specified. The CPU 56
The content of the indicated command data 2 is loaded into the argument 2 (step S237). Further, it is confirmed whether the value of bit 7 (work area reference bit) of the command data 2 is “0” (step S239). If it is not 0, the start address of the command extension data address table is set in the pointer (step S239), and the address is calculated by adding the value of bit 6 to bit 0 of the command data 2 to the pointer (step S240). Then, the data of the area indicated by the address is loaded into the argument 2 (step S241).

In the command extension data address table, EXT data that can be transmitted to the electric component control means is sequentially set. Therefore, if the value of the work area reference bit is “1” by the above processing, the EXT data in the command extension data address table corresponding to the content of the command data 2 is loaded into the argument 2 and the work area reference bit is set. If the value is “0”, the content of the command data 2 is loaded as it is into the argument 2. Even when EXT data is read from the command extension data address table, bit 7 of that data is “0”.

Next, the CPU 56 calls a command transmission routine (step S242). Therefore, MOD
The EXT data is transmitted at the same timing as the transmission of the E data. Thereafter, the CPU 56 restores the address of the command transmission table (step S243), and updates the value of the read pointer pointing to the command transmission table (step S244). Since one command transmission table has a 3-byte configuration, specifically, the value of the read pointer is +3.

As described above, the 2-byte control command (dispensing control command, display control command, lamp control command, voice control command) is transmitted to the corresponding electric component control means. INT in the electrical component control means
When the falling of the signal is detected, the control command fetching process is started. Regardless of the electric component control means, a new signal from the game control means is output to the signal line before the fetching process is completed. Never. That is, a reliable command receiving process is performed in each electric component control unit. In addition, each electric component control means is I
The control command fetch process may be started at the rise of the NT signal. Also, the polarity of the INT signal may be reversed from that shown in FIG.

Further, in this embodiment, a plurality of command transmission tables are used as ring buffers, and FIG.
In the command control process shown in FIG. 9, command output control is performed for the command transmission table pointed to by the read pointer, and in the process of setting data in the command transmission table, for example, in the winning sphere signal process shown in FIG. The command setting process is performed on the command transmission table indicated by the embedded pointer. Therefore, even if a plurality of command transmission requests occur at the same time, the command output process based on those requests is executed without any problem.

Next, a command receiving process in the electric component control means will be described. Here, a command receiving process and the like in the payout control means will be described.

FIG. 31 is a block diagram showing an example of a configuration around the payout control CPU 371. As shown in FIG. 31, the voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) is supplied to the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the buffer circuit 960.
It is connected to the. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of various DC power supplies used by the gaming machine and detects a drop in the power supply voltage. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value falls below a predetermined value, a low-level voltage drop signal is generated. VSL
Is the largest DC voltage used in gaming machines, and is +30 V in this example. Therefore, the payout control CPU 371 can confirm the occurrence of power interruption by the interrupt processing.

Payout control C used in this embodiment
The PU 371 also has a PI like the CPU 56 of the main board 31.
O and CTC are built in. However, in this embodiment, no built-in PIO is used. In that case, for example, all ports are set to the input mode, and all ports are connected to the ground level.

Further, similarly to the CPU 56 of the main board 31,
The payout control CPU 371 can also be set to any of the interrupt modes 0 to 2, and the CTC can operate in a timer mode or a counter mode as described below.
Also, CTC has four channels. Specifically, four timer counter registers CLK / TRG0 to
3 (counters for channels 0 to 3). The operation mode can be set for each channel.

Each timer counter register CLK / TRG
The values of 0 to 3 are counted down according to the clock signal input to the corresponding CLK / TRG terminal, and when the count value becomes 0, an interrupt can be generated. Therefore,
Each of the channels 0 to 3 of the CTC can be an interrupt generation unit. The priority of the channel 0 is the highest, and then the priority sequentially decreases. That is, the count values of the plurality of timer counter registers CLK / TRG are simultaneously set to 0.
, The channel with the lower number has priority,
If those channels are set to generate an interrupt, an interrupt from a channel with a lower number is accepted first.

In this embodiment, channel 3 of the built-in CTC is used in the timer mode, and channel 2 is used in the counter mode. Channel 3 is used as a timer interrupt source, and channel 2 is used for receiving a payout control command.

Counter mode: payout control CPU 371
When the rising or falling edge of the clock signal is input to the CLK / TRG terminal, the count value is decremented by one. If interrupt generation permission is set for the channel, an interrupt is generated when the count value reaches 0,
Reload the initial value into the counter. If the interrupt vector has been set, the interrupt vector is sent out on the internal data bus when the count value becomes zero.

Timer mode: The count value is decremented by 1 based on a clock signal obtained by dividing the system clock (internal clock) by 1/16 or 1/256. If interrupt generation permission is set for that channel,
When the count value becomes 0, an interrupt is generated, and the initial value is reloaded into the counter. If the interrupt vector has been set, the interrupt vector is sent out on the internal data bus when the count value becomes zero.

CLK / TRG of payout control CPU 371
An INT signal (payout control signal INT) from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the payout control CPU 371
Timer / counter register CLK / TR built in
The value of G2 (CTC channel 2 counter) is down-counted. When the register value becomes 0, an interrupt occurs. Therefore, as shown in FIG. 32, if the initial value of the timer counter register CLK / TRG2 is set to “1”, the register value becomes 0 in response to the input of the INT signal and an interrupt occurs. Become.

The payout control board 37 is also equipped with a system reset circuit 975. In this embodiment,
The system reset circuit 975 also functions as a second power supply monitoring circuit (second power supply monitoring unit). That is, when the power is turned on, the reset IC 976 sets the output to a low level for a predetermined time determined by the capacity of an external capacitor, and sets the output to a high level after the predetermined time has elapsed. The reset IC 976 monitors the power supply voltage of VSL, which is the same as the power supply voltage monitored by the first power supply monitoring circuit mounted on the power supply board 910, and the voltage value becomes equal to or less than a predetermined value (for example, +9 V). Then, a low level voltage drop signal is generated. Therefore, when the power is turned off, the reset IC 976
When the voltage drop signal from the CPU goes low, the payout control CPU 371 is reset. Note that, as shown in FIG. 31, the voltage drop signal is the same output signal as the reset signal.

Although the predetermined value for the reset IC 976 to detect the power-off is lower than the normal voltage, the payout control C
This is a voltage at which the PU 371 can operate for a while. Further, since the reset IC 976 is configured to monitor a voltage higher than the voltage (+5 V in this example) required by the payout control CPU 371, the payout control CPU 371
The monitoring range can be extended for the voltage required by the 371. Therefore, more precise monitoring can be performed.

While power is not supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting a backup power supply supplied from the power supply board to the backup terminal. The contents are saved even if the power is turned off. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to the normal operation state. At that time, since the necessary data has been backed up,
Upon recovery from a power failure or the like, it is possible to return to the gaming state at the time of the power failure.

As described above, in this embodiment, the first power supply monitoring circuit mounted on the power supply board 910 monitors the highest voltage of the power supply VSL among the DC voltages used in the gaming machine. Then, when the voltage of the power supply falls below a predetermined value, a voltage drop signal (power-off detection signal) is generated. At the timing when the power-off detection signal is output, the IC drive voltage is
The voltage value is still enough to drive various circuit elements. Therefore, the payout control board 37 operated by the IC drive voltage
The operation time for the payout control CPU 371 to perform the predetermined power supply stop processing is secured.

Note that, also here, the first power supply monitoring circuit
Highest power supply VSL among DC voltages used in gaming machines
The power supply cutoff detection signal is generated at a timing such that the operation time for the electric component control means operating at the IC drive voltage to perform a predetermined power supply stop processing is secured. If it is timing, the monitoring target voltage need not be the highest voltage of the power supply VSL. That is, if at least the voltage higher than the IC drive voltage is monitored, the power-off detection signal can be generated at a timing such that the operation time for the electric component control means to perform the predetermined power supply stop processing is secured. it can.

In this case, as described above, since the voltage to be monitored is +12 V supplied to various switches of the gaming machine such as the prize ball count switch 301A, it is possible to prevent erroneous switch-on detection when the power is turned off. Is also a voltage that can be expected. That is, it is preferable that the voltage drop can be detected before the + 12V power supply voltage, which is the voltage (switch voltage) supplied to the switch, starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

In the configuration shown in FIG. 31, when the power is turned on, the system reset circuit 975 outputs a low level for a period determined by the capacity of the capacitor, and then outputs a high level. That is, the reset release timing is only once. However, the main substrate 31 shown in FIG.
As in the case of the above, a circuit configuration that generates a plurality of reset release timings may be used.

FIG. 33 is a flowchart showing the main processing of the payout control CPU 371. In the main processing,
The payout control CPU 371 first performs necessary initial settings (step S701).

FIG. 34 is a flowchart showing the initial setting process in step S701. In the initial setting process, the payout control CPU 371 first sets interrupt prohibition (step S701a). Next, the payout control CPU
The control unit 371 sets the interrupt mode to the interrupt mode 2 (step S701b), and sets a stack pointer designation address in the stack pointer (step S701c). Further, the payout control CPU 371 initializes the built-in device register (step S701d), and after initializing CTC and PIO (step S701e),
The RAM is set in an accessible state (step S70)
1f).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the internal device register setting process of step S701d and the process of step S701e, register setting for setting the channel to be used to the timer mode;
Register setting for permitting interrupt generation and register setting for setting an interrupt vector are performed. And
The interrupt by the channel is used as the timer interrupt described above. If a timer interrupt is to be generated every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set for the channel set in the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt processing. Specifically, the start address of the timer interrupt processing is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, the timer interrupt flag is set, and when it is detected in the main process that the timer interrupt flag is set, the payout control process is executed. That is, in the timer interrupt process, a setting for executing the payout control process, which is an example of the electrical component control process, is performed.

Another channel of the built-in CTC (channel 2 in this embodiment) is used as a channel for generating an interrupt for receiving a payout control command from the game control means. Is used in the counter mode. Therefore, in the internal device register setting process of step S701d and the process of step S701e, the register setting for setting the channel to be used to the counter mode, the register setting for permitting the occurrence of interrupt, and the interrupt vector are set. Is set.

The interrupt vector set for the channel (channel 2) set to the counter mode corresponds to the head address of the command reception interrupt process described later. Specifically, the start address of the command reception interrupt processing is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
At 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on the count-up of C can be used. Further, it is possible to set an interrupt processing start address according to the interrupt vector transmitted by the CTC.

The interrupt based on the count up of the channel 2 (CH2) of the CTC is an interrupt generated when the value of the timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S701e, the initial value “1” is set in the timer counter register CLK / TRG2 as the specific register. Also,
The interrupt based on the count up of the channel 3 (CH3) of the CTC is an interrupt generated when the register value becomes “0” after counting down the internal clock (system clock) of the CPU, and a 2 ms timer interrupt described later. Used as Specifically, the register value of CH3 is subtracted in 1/256 cycle of the system clock. In step S701e, a value corresponding to 2 ms is set as an initial value in the register of CH3. In this embodiment, the interrupt address for CH2 is 0074H, and the interrupt address for CH3 is 0076H.

As described above, the interrupt based on the count-up of CH2 of CTC has a higher priority than the interrupt based on the count-up of CH3. Therefore, when the count-up occurs at the same time, an interrupt based on the count-up of CH2, that is, an interrupt that triggers execution of a command reception interrupt process described later has priority.

The payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S70).
2). That is, for example, similarly to the processing of the CPU 56 of the main board 31, it is determined whether or not backup data exists by determining whether or not a backup flag that is set when the power is turned off is in a set state. If the backup flag is set, it is determined that there is backup data. If it is determined that there is no backup data, it means that there was no unpaid game ball when the power was last turned off, and there is no need to return the internal state to the state when the power was turned off. Accordingly, the payout control CPU 371
An initialization process that is performed when the power is turned on, not when the power is restored, is executed (steps S702 and S703).

When the backup data exists in the backup RAM area, the payout control CPU 371
Performs a data check (parity check in this example) of the backup RAM area (step S704).
If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power failure, the initialization processing executed at the time of power-on without power recovery is executed (steps S705 and S70).
3).

If the check result is normal, the payout control CPU 371 performs a payout state restoring process for returning the internal state to the state at the time of power-off (step S706). Then, the process returns to the address indicated by the PC (program counter) stored in the backup RAM area (step S707).

Execution of normal initialization processing (step S70)
After 3), the main process executed by the payout control CPU 371 shifts to a loop process in which the timer interrupt flag is monitored (step S708).

Note that, in this embodiment, step S7
02, the presence or absence of backup data is checked, and if backup data exists, the backup area is checked in step S704. Conversely, it is confirmed that the backup area check result is normal. The confirmation of the presence or absence of the backup data may be performed later. Further, it may be configured to determine whether or not to execute the power failure recovery process by confirming whether or not there is backup data or checking the backup area.

Also, for example, a parity check for determining whether or not to execute the power failure recovery processing (step S70)
In the case of 4) or the like, that is, when it is determined whether or not the gaming state is to be restored, the gaming machine is in the standby state for payout (not in the middle of payout) due to the number of payout game balls in the stored RAM data. If it is confirmed that there is, the initialization processing may be executed without performing the payout state restoration processing.

In the normal initialization process, as shown in FIG. 35, the register and RAM are cleared (step S9).
01) is performed, and a predetermined initial value is set (step S902). Then, the initial setting process (step S7)
01a), the interrupt is prohibited, so the interrupt is permitted before the initialization process is completed (step S90).
3).

In this embodiment, the payout control CPU 3
CH3 71 is set to repeatedly generate a timer interrupt. The repetition period is set to 2 ms. Then, as shown in FIG. 36, when a timer interrupt occurs, the payout control CPU 371 sets a timer interrupt flag (step S711). Note that FIG. 36 also clearly indicates that the interrupt is permitted (step S
710) In the 2 ms timer interrupt processing, first, the interrupt permission state is set. That is, the interrupt is permitted during the 2 ms timer interrupt process.

The payout control CPU 371 determines in step S7
If it is detected at 08 that the timer interrupt flag has been set, the timer interrupt flag is reset (step S709), and a payout control process is executed (step S710). According to the above control, in this embodiment, the payout control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt processing, and the payout control processing is executed in the main processing. However, the payout control processing may be executed in the timer interrupt processing.

At the time of power-on, the payout control CPU 371 can determine whether to perform the normal initialization processing or restore the payout state only by checking the data in the backup RAM area. That is, with a simple judgment,
The payout process can be restarted for unpaid game balls. Further, in this embodiment, as in the case of the game control on the main board 31, the storage contents are reliably stored by the parity check code.

FIG. 37 is an explanatory diagram showing an example of use of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number storage (for example, 2 bytes) and a rental ball number storage are formed. The total number storage stores the total number of payouts instructed from the main board 31 side. The rental ball number storage stores the number of unpaid ball rentals.

FIG. 38 is an explanatory diagram showing an example of the configuration of a receiving buffer for storing the payout control command received from the main board 31. In this example, a ring buffer type receiving buffer capable of storing six payout control commands having a 2-byte configuration is used. Therefore, the reception buffer is constituted by a 12-byte area of the fixed command buffers 1 to 12. Then, a command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11.

FIG. 39 is a flowchart showing a payout control command receiving process by the interrupt process. An INT signal for payout control from the main board 31 is supplied to a payout control CPU 371.
Are input to the CLK / TRG2 terminal. Therefore, when the INT signal from the main board 31 is turned on, the value of the timer counter register CLK / TRG2, which has been set to “1” as the initial value, becomes 0, and the payout control CPU 3
At 71, an interrupt occurs. Then, the payout control command receiving process shown in FIG. 38 is started. The start address of the payout control command receiving process is an address determined by the interrupt vector output from the built-in CTC and the value set in the I register. Also, the timer counter register CLK
When the value of / TRG2 becomes 0, that value is automatically returned to the initial value ("1" in this example).

In the processing of receiving the payout control command, the payout control CPU 371 first saves each register in the stack (step S850). Note that when an interrupt occurs, the CPU 371 automatically sets the interrupt prohibition state. However, when a CPU that does not automatically enter the interrupt prohibition state is used, the interrupt prohibition is performed before the execution of the process of step S850. It is preferable to issue an instruction (DI instruction). Next, data is read from the input port 372a assigned to the input of the payout control command data (step S851). Then, it is confirmed whether or not this is the first byte of the payout control command having the 2-byte structure (step S).
852). Whether it is the first byte or not is confirmed by whether or not the first bit of the received command is “1”. The first bit should be “1” in the MODE byte (first byte) of the payout control command having a 2-byte configuration (see FIG. 19). Therefore, if the first bit is “1”, the payout control CPU 371 determines that the valid first byte has been received, and stores the received command in the confirmed command buffer indicated by the command reception number counter in the reception buffer area (step S85
3).

If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not the data has already been received is confirmed based on whether or not valid data is set in the reception buffer (fixed command buffer).

If the first byte has already been received,
It is checked whether the first bit of the received 1 byte is “0”. And if the first bit is “0”,
Assuming that the valid second byte has been received, the received command is stored in the fixed command buffer indicated by the command reception number counter +1 in the reception buffer area (step S855). The first bit should be “0” in the EXT byte (the second byte) of the payout control command having the two-byte configuration (see FIG. 19). If it is determined in step S854 that the first byte has already been received, the process ends if the first bit of the data received as the second byte is not “0”.

In step S855, when the command data of the second byte is stored, 2 is added to the command reception number counter (step S856). Then, it is checked whether or not the command reception counter is 12 or more (step S857), and if it is 12, the command reception number counter is cleared (step S858). After that, the saved register is restored (step S859),
Interrupt permission is set (step S859).

During the command reception interruption processing, interruption is prohibited. As described above, the interrupt is permitted during the 2 ms timer interrupt process. Therefore, if a command reception interrupt occurs during the 2 ms timer interrupt, the command reception interrupt process is executed with priority. You. Further, even if a 2 ms timer interrupt occurs during the command reception interrupt process, the interrupt process is kept waiting. As described above, in this embodiment, the processing priority of the command reception processing from the main board 31 is high. Further, since no other interrupt processing is executed during the command reception processing, the maximum time required for the command reception processing is determined. It is difficult to estimate the longest time required for the command receiving process if the configuration is such that another interrupt process can be executed during the command receiving process. Since the maximum time required for the command receiving process is determined, a period C in the command sending process of the game control means (see FIG. 20)
Can be accurately determined.

The payout control command has a 2-byte structure, and includes a first byte (MODE) and a second byte (EX).
T) is configured to be immediately distinguishable on the receiving side.
In other words, the receiving side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. Therefore, as described above, it can be easily determined whether or not appropriate data has been received.

FIG. 40 is a flowchart showing the payout control processing in step S710. In the payout control processing, the payout control CPU 371 first determines whether or not the prize ball count switch 301A and the ball lending count switch 301B input to the input port 372b via the relay board 72 are turned on (switch processing: Step S7
51).

Next, the payout control CPU 371 performs processing such as checking the signal input state from a sensor (for example, a motor position sensor for detecting the number of revolutions of the payout motor 289) and judging the state of the sensor (for example). Input determination processing: Step S752). The payout control CPU 371 further analyzes the received payout control command and executes processing according to the analysis result (command analysis execution processing: step S75).
3).

Next, the payout control CPU 371 sets the payout stop state if the payout stop command is received from the main board 31, and cancels the payout stop state if the payout start instruction command is received (step S754). ).
Further, a prepaid card unit control process is performed (step S755).

Next, the payout control CPU 371 performs control to pay out the lent ball in response to the ball lending request (step S756). Further, the payout control CPU 371 performs a prize ball control process of paying out the prize balls of the number stored in the total number storage (step S757). And payout control C
The PU 371 includes the output port 372c and the relay board 72.
A drive signal is output to the payout motor 289 in the payout mechanism portion of the ball payout device 97 through the step S75.
A payout motor control process of rotating the payout motor 289 by the number of revolutions set in the ball lending control process of No. 6 or the prize ball control process of step S757 is performed (step S758).

In this embodiment, the delivery motor 2
A stepping motor is used as 89, and a 1-2-phase excitation method is used to control the payout motor 289. Therefore, specifically, in the payout motor control processing, eight types of excitation pattern data are repeatedly output to the payout motor 289. In this embodiment, each excitation pattern data is output for 4 ms.

Next, error detection processing is performed, and a predetermined display is made on the error display LED 374 according to the result (error processing: step S759). For example, the following eight types of errors are detected.

Prize ball path error: When the prize ball payout operation is completed, or when the payout motor 289 makes one rotation, no prize ball count switch 301A detects the passage of a game ball. “0” is displayed on the error display LED 374.

Ball lending path error: When the ball lending payout operation is completed, or when the payout motor 289 makes one revolution, the ball lending count switch 301B does not detect any passage of the game ball. “1” is displayed on the error display LED 374.

Prize ball count switch ball clogging error: when the prize ball count switch 301A detects ON for 0.5 seconds or more. “2” is displayed on the error display LED 374.

Ball lending count switch Ball clogging error:
When the ball lending count switch 301B detects ON for 0.5 seconds or more. “3” is displayed on the error display LED 374.

Discharge motor ball biting error: Dispense motor 28
When 9 does not rotate normally. Specifically, when the payout motor position sensor has been on for a predetermined period or more, or has been turned off for a predetermined period or more. “4” is displayed on the error display LED 374. Note that when a payout motor ball biting error occurs, the payout control CPU 371 sets the time to 50 ms.
After the reference excitation phase is output, four types of excitation pattern data of the excitation pattern data of the 1-2 phase excitation are
The output motor 289 repeats the reverse rotation and the normal rotation by outputting the output every ms.

Prepaid card unit not connected error:
When the off of the VL signal is detected. Error display LED3
“5” is displayed at 74.

Prepaid card unit communication error: When it is detected that a signal is output from the prepaid card unit 50 at a timing other than the prescribed timing. Error display LE
“6” is displayed in D374.

Dispensing stop state: When a dispensing control command indicating dispensing stop is received from main board 31. Error display LE
“7” is displayed in D374. When a payout control command indicating the start of payout is received from the main board 31,
After 2002 ms from that point, the state returns from the payout stop state to the payable state.

Further, processing for controlling an information signal output from an external connection terminal (not shown) is performed (output processing: step S760). The information signal is a signal that is turned on for a predetermined period of time for each unit of payout of a lent ball (for example, 25 pieces), and subsequently, is output as off for a predetermined period.

FIG. 41 is a flowchart showing an example of the switch processing in step S751. In the switch processing, the payout control CPU 371 checks whether or not the award ball count switch 301A indicates the ON state (step S751a). If it indicates the ON state, the payout control CPU 371 increments the winning ball count switch ON counter by one (step S751b). The prize ball count switch on counter includes the prize ball count switch 30.
This is a counter for counting the number of times the 1A ON state is detected.

Then, the value of the prize ball count switch on counter is checked (step S751c). If the value is 2, it is determined that one prize ball has been paid out. When determining that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball non-payout counter (the number of prize balls stored in the total number storage) (step S751d).

If it is confirmed in step S751a that the prize ball count switch 301A is not on, the payout control CPU 371 clears the prize ball count switch on counter (step S751e). In this embodiment, the ball rental count switch 3
It is checked whether 01B indicates the ON state (step S751f). If it indicates the ON state, the payout control CPU 371 increments the ball lending count switch ON counter by one (step S751g). The ball rental count switch on counter is a ball rental count switch 301
This is a counter for counting the number of times the ON state of B is detected.

Then, the value of the ball lending count switch on counter is checked (step S751h), and if the value is 2, it is determined that one ball has been paid out. If it is determined that one loaned ball has been paid out, the payout control CPU 371 determines the number-of-lent-ball-unpaid-number counter (number of loaned balls stored in the number-of-lent-ball storage).
Is decremented by 1 (step S751i).

If it is determined in step S751f that the ball lending count switch 301B is not on, the payout control CPU 371 clears the ball lending count switch on counter (step S751j).

FIG. 42 is a flowchart showing an example of the command analysis execution processing in step S753. In the command analysis execution processing, the payout control CPU 371
It is checked whether there is a received command in the confirmed command buffer area (step S753a). If there is a received command, it is checked whether the received payout control command is a payout number instruction command (step S753).
b). If there are a plurality of received commands in the confirmed command buffer area, whether or not the received payout control command is the payout number instruction command is checked for the earliest received received command. Will be

If the received payout control command is the payout number instruction command, the number specified by the payout number instruction command is added to the total number storage (step S753).
c). That is, the payout control CPU 371 is connected to the main board 3
The number of prize balls included in the number-of-payouts instruction command sent from the first CPU 56 is stored in the backup RAM area (total number storage).

It is to be noted that the payout control CPU 371 performs a command decrement of the command reception number counter and a received command shift process in the confirmed command buffer area, if necessary.

FIG. 43 is a flowchart showing an example of the payout stop state setting process in step S754. In the payout stop state setting process, the payout control CPU 371
It is checked whether there is a received command in the confirmed command buffer area (step S754a). If there is a received command in the confirmed command buffer area, it is checked whether or not the received payout control command is a payout stop instruction command (step S754b). If the command is the payout stop instruction command, the payout control CPU 371 sets the payout stop state (step S754c).

If it is determined in step S754b that the received command is not a payout stop command, it is checked whether the received payout control command is a payout start command (step S754d). If the command is a payout start instruction command, the payout stop state is released (step S7).
54e).

FIG. 44 is a flowchart showing an example of the prepaid card unit control processing in step S755. In the prepaid card unit control process, the payout control CPU 371 checks whether or not the VL signal input from the card unit control microcomputer has been detected (step S755a). If the VL signal has not been detected, the VL signal non-detection counter is incremented by 1 (step S755b). The payout control CPU 37
1 checks whether the value of the VL signal non-detection counter is 125 in this example (step S755c). If the value of the VL signal non-detection counter is 125, the payout control CP
U371 stops the emission control signal output to the emission control board 91 and stops the drive motor 94 (step S7).
55d).

By the above processing, 125 times (2 ms ×
(125 = 250 ms) If the OFF of the VL signal is detected continuously, the state is set to the ball firing prohibited state.

If the VL signal has been detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the output of the firing control signal has been stopped (step S755f), the payout control CPU 371 starts outputting the firing control signal to the firing control board 91 to make the drive motor 94 operable (step S755g). .

FIGS. 45 and 46 show steps S756 and S756.
It is a flowchart which shows an example of the ball lending control process.
In this embodiment, the maximum value of the number of consecutive payouts is one unit of the lending ball (for example, 25), but the maximum value of the number of consecutive payouts may be another number.

In the ball lending control process, the payout control CP
The U371 checks whether or not the ball is being paid out (step S511). If the ball is being paid out, the process shifts to the ball lending process shown in FIG. Whether or not the ball is being paid out is determined based on the state of a ball lending process flag described later. If the ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S512). Whether or not a prize ball is being paid out is determined by the state of a prize ball processing flag described later.

If neither a loaned ball is being paid out nor a prize ball is being paid out, the payout control CPU 371 checks whether or not a ball lending request has been issued from the card unit 50 (step S5).
13). If there is a request, the ball lending process flag is turned on (step S514), and 25 (the number of ball lending units: 100 yen here) is set in the lending ball number storage in the backup RAM area (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the distributing solenoid 310 is driven to set the ball distributing member 311 below the ball dispensing device 97 to the ball lending side (step S517). Further, the payout motor 289 is turned on (step S51).
8) The process proceeds to the ball lending process shown in FIG.

The turning on of the payout motor 289 is
Strictly speaking, the BRQ signal is turned off to indicate that the card unit 50 has recognized the reception. The ball lending processing flag is set in the backup RAM area.

FIG. 46 is a flowchart showing processing during lending a ball in the payout control processing by the payout control CPU 371. In the ball lending process, if the payout motor 289 is not on, it is turned on. In this embodiment,
In the switch processing in step S751, it is checked whether or not the game balls have been paid out based on the detection output of the ball lending count switch 301B. Therefore, in the ball lending control processing, the subtraction of the storage of the number of lending balls is not performed. In the ball lending control process, the payout control CPU 371 confirms whether or not the ball lending pass time is being passed (step S519). If it is not during the lending ball passage waiting time, the lending ball is paid out (step S520), and it is determined whether or not the driving of the payout motor 289 should be terminated (whether one unit of the dispensing operation has been completed) (step S521). ). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. The rotation corresponding to the predetermined number of payouts is monitored by the output of the payout motor position sensor. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522),
The waiting time for passing a rental ball is set (step S52).
3).

[0279] In the ball lending process in step S520, the on / off state of the payout motor position sensor is monitored by a timer. It is determined that a ball biting error has occurred.

If it is determined in step S519 that the waiting time for passing a ball is being passed, the payout control CPU 371 checks whether or not the waiting time for passing a ball is completed (step S52).
4). The lending ball passing waiting time is the time from when the last payout ball is paid out by the payout motor 289 to when it passes through the ball lending count switch 301B. When confirming the end of the waiting time for passing a lending ball, since all lending balls for lending have been paid out, it is necessary to indicate to the card unit 50 that the next lending ball lending request can be accepted. The EXS signal is turned off (step S525). In addition, the distribution solenoid is turned off (step S5).
26), the ball lending processing flag is turned off (step S5)
27). If the last payout ball has not passed through the ball lending count switch 301B before the lending ball passage waiting time has elapsed, a ball lending path error is determined. Also,
In this embodiment, the prize ball and the ball lending are performed by the same payout device.

After the EXS signal indicating the acceptance of the ball lending request is turned off and the BRQ signal, which is the ball lending request signal, is turned on again within a predetermined period, the ball lending without turning off the sorting solenoid and the payout motor is performed. The processing may be continued. That is, a predetermined unit (100 yen unit in this example)
Instead of performing the ball lending process every time, the ball lending process may be performed continuously.

[0282] The contents of the stored number of lent balls are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the payout control CPU 371 can continue the ball lending process based on the contents of the lending ball number storage.

FIGS. 47 and 48 show steps S757.
It is a flowchart which shows an example of the award ball control processing. In this example, the maximum value of the number of continuous payouts is the same as one unit of the lending ball (for example, 25), but the maximum value of the number of continuous payouts may be another number.

In the prize ball control processing, the payout control CPU
The 371 checks whether or not the rental ball is being paid out (step S531). Whether or not the ball is being paid out is determined based on the state of the ball lending process flag. If the ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S).
532) If the prize ball is being paid out, the processing shifts to the processing during the prize ball shown in FIG. Whether or not a prize ball is being paid out is determined by a state of a prize ball processing flag described later.

If neither the loaned ball is paid out nor the prize ball is paid out, the payout control CPU 371 checks whether or not there is a ball lending preparation request from the card unit 50 (step S).
533). Whether or not there is a ball lending preparation request is performed by confirming whether the BRDY signal input from the card unit 50 is on (requested) or off (no request).

If there is no ball lending preparation request from the card unit 50, the payout control CPU 371 checks whether or not the number of awarded balls (the number of unpaid awarded balls) stored in the total number memory is not zero (see FIG. 4). Step S534). If the number of award balls stored in the total number memory is not 0, the award ball control CP
U371 turns on the award ball processing flag (step S5).
35) It is checked whether or not the value of the total number storage is 25 or more (step S536). The award ball processing flag is set in the backup RAM area.

The number of award balls stored in the total number storage is 2
If it is 5 or more, the payout control CPU 371 sets a 25 payout operation to output a drive signal to the payout motor 289 so as to rotate the payout motor 289 until 25 game balls are paid out. (Step S53)
7). If the number of prize balls stored in the total number memory is not 25 or more, the payout control CPU 371 drives the payout motor 289 to rotate the payout motor 289 until all game balls stored in the total number memory are paid out. Is set to output the total number payout operation (step S53).
8). Next, the payout motor 289 is turned on (step S538). Since the distribution solenoid is off, the ball distribution member below the ball payout device 97 is set to the winning ball side. Then, the processing shifts to a processing during payout of the winning ball in the winning ball control processing shown in FIG. 47.

FIG. 47 is a flowchart showing an example of processing during a winning ball in the payout control processing by the payout control CPU 371. In the prize ball control processing, the payout motor 289
Turn on if is not on. In the present embodiment, in the switch processing of step S751, it is determined whether or not the payout of the game ball has been performed based on the detection output of the prize ball count switch 301A. Is not done. In the processing during the prize ball, the payout control CPU 371 checks whether or not the prize ball passage waiting time is in progress (step S540). If it is not during the waiting time for passing a prize ball, a prize ball is paid out (step S
541), should the drive of the payout motor 289 be terminated (2
It is determined whether or not a predetermined number of payout operations of 5 or less than 25 have been completed (step S542). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. The rotation corresponding to the predetermined number of payouts is monitored by the output of the payout motor position sensor. When the rotation corresponding to the predetermined number of payouts is completed, the payout control C
The PU 371 stops driving the payout motor 289 (Step S543), and sets a winning ball passage waiting time (Step S544). The prize ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 to when it passes through the prize ball count switch 301A.

If it is determined in step S540 that the waiting time for passing a prize ball is in progress, the payout control CPU 371 checks whether or not the waiting time for passing a prize ball has ended (step S545).
The point in time when the waiting time for passing the prize ball ends is determined in step S537.
Alternatively, all the prize balls set in step S538 have been paid out. Therefore, the payout control CPU 371
Turns off the award ball processing flag (step S54).
6). If the last payout ball has not passed through the prize ball count switch 301A before the prize ball passage waiting time has elapsed, it is determined that a prize ball path error has occurred.

In this embodiment, step S5
11. Although the ball lending is given priority over the prize ball processing by the determination in step S531, the prize ball processing may be given priority over the ball lending.

[0291] The contents of the total number storage and the number of lent balls storage are such that the power supply board 910 is maintained for a predetermined period even if the power of the gaming machine is turned off.
Saved by backup power. Therefore, when the power is restored during the predetermined period, the payout control CPU 371
Can continue the payout process based on the contents of the total number storage.

The payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the prize ball number storage, but for each prize ball number (for example, 15, 10 or 6).
). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the prize ball payout corresponding to the number counter is performed, the number counter is decremented by one (in this case, the subtraction processing is performed in the payout control processing).
Also in this case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the payout control CPU 371
Can continue the award ball payout process based on the content of each number counter.

FIG. 48 is a flowchart showing an example of the power failure occurrence NMI process executed in response to the NMI based on the voltage change signal from the power supply monitoring circuit of the power supply board 910. In this embodiment, the NMI interrupt address is 00
66H. In the power failure occurrence NMI process, the payout control CPU 371 first stores the contents of the interrupt prohibition flag in the parity flag (step S801). Then
The interrupt is prohibited (step S802). Power failure occurred N
In the MI process, in this example, as in the process executed on the main board 31, a process of generating a checksum for ensuring the storage of the RAM content is performed. If another interrupt process is performed during that process, the voltage may drop to a level at which the payout control CPU 371 cannot operate before the checksum generation process is completed. Are set so that other interrupts do not occur. In addition,
Steps S804 to S81 in the power failure occurrence NMI process
0 is an example of the power supply stop processing.

When a CPU having a specification such that another interrupt does not occur during the interrupt processing is used, the processing in step S802 is unnecessary.

Next, the payout control CPU 371 checks whether or not the backup flag has already been set (step S803). If the backup flag has already been set, no further processing is performed. If the backup flag is not set, the following power supply stop processing is executed. That is, the processing from step S804 to step S810 is executed.

First, the contents of each register are backed up by R
It is stored in the AM area (step S804). After that, a backup flag is set (step S805).
Then, an appropriate initial value is set in the backup check data area of the backup RAM area (step S80).
6) The exclusive OR is sequentially calculated for the initial value and the data in the backup RAM area and then inverted (step S807), and the final operation value is set in the backup parity data area (step S808). Also, RA
The M access is prohibited (step S809). When the power supply voltage decreases, the levels of various signal lines may become unstable and the contents of the RAM may be corrupted. However, if the RAM access is prohibited in this manner, the data in the backup RAM may be corrupted. There is no.

Further, the payout control CPU 371 has all output ports (in this embodiment, output ports 372
c, 372g, 372e, and I / O port 372f
Output port portion). Therefore, all output ports are turned off by the clear signal (step S810).

Next, the payout control CPU 371 enters a loop process. That is, no processing is performed. Therefore, before the operation is disabled from the outside by the system reset signal from the reset IC 976 shown in FIG. 31, the operation is internally stopped. Therefore, the operation of the payout control CPU 371 is reliably stopped when the power is turned off. As a result, due to the above-described RAM access prohibition control and the operation stop control, the value of R due to the abnormal operation that may occur as the power supply voltage decreases.
Destruction of the contents of the AM can be reliably prevented.

In this embodiment, the power failure occurrence NM
In I processing, the program was looped in the last part,
It may be configured to issue a HALT instruction.

The backup flag set after storing the contents of the register in the RAM area is, as described above, whether or not there is backup data to be restored when the power is turned on (whether or not to recover from a power failure). Used to judge. Also, steps S801 to S810
Is completed before the payout control CPU 371 receives the system reset signal from the system reset circuit 975. In other words, to complete before receiving the system reset signal from the system reset circuit 975,
The detection voltage of the voltage monitoring circuit is set.

In this embodiment, the backup flag is checked at the start of the power supply stop processing. If the backup flag has already been set, the power supply stop processing is not executed. As mentioned above,
The backup flag is a flag indicating that the backup of necessary data has been completed and then the power supply stop processing has been completed. Therefore, for example, even if the NMI occurs again for some reason in the reset waiting loop state, the power supply stop processing will not be repeatedly executed.

[0302] However, when a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the determination in step S803 is unnecessary.

Also, in this embodiment, the payout control C
PU 371 is a non-maskable external interrupt terminal (NMI terminal)
, The NMI interrupt signal from the power supply board (NMI interrupt signal from the power supply monitoring means) is detected, but the NMI interrupt signal may be introduced to a maskable interrupt interrupt terminal (INT terminal). In that case, the power failure occurrence NMI process shown in FIG. 49 is executed by the INT process. Further, an NMI interrupt signal may be detected through an input port. In that case, the input port is monitored in the main process executed by the payout control CPU 371.

FIG. 50 is an explanatory diagram for describing an example of a backup parity data creating method. However,
In the example shown in FIG. 50, the size of the data in the backup data RAM area is 3 bytes for simplicity. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 50, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, an exclusive OR of the result and “DFH” is obtained. Then, a value (“C6H” in this example) obtained by inverting the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, a parity diagnosis is performed in the power failure recovery processing. If all the data in the backup area is stored as it is, the data as shown in FIG. 49 is set in the backup area when the power is turned on again.

In the processing of step S704, the payout control CPU 371 performs the same processing as the processing executed in steps S806 and S807 in FIG. That is, initial data (00H in this example) is set in the backup check data area, and "00H"
And "F0H" are exclusive ORed, and the result is "1"
6H "is exclusive-ORed. Further, an exclusive OR of the result and “DFH” is obtained. Then, a final operation result obtained by inverting the result (“39H” in this example) is obtained. If all data in the backup area is stored as it is, the final calculation result matches “C6H”, that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final operation result does not become “C6H”.

[0307] Therefore, the payout control CPU 371 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, the payout control means is provided with the storage means (backup RAM in this example) which is backed up for a predetermined period even if the power of the gaming machine is turned off. At the time of insertion, payout control CPU
371 (specifically, a program executed by the payout control CPU 371) is configured to perform a payout state restoration process (step S706) for restoring the payout state based on the backup data if the storage unit is in the backup state. .

[0309] Hereinafter, the payout state restoration processing will be described. FIG. 51 is a flowchart showing an example of the payout state restoration processing shown in step S706 of FIG. In this example, the payout control CPU 371 sets the backup R
The value stored in the AM is restored to the register (step S861). Then, based on the data stored in the backup RAM, a process for recovering the payout state at the time of the power failure is performed. For example, a flag during processing of a prize ball is set.

When the payout state is restored, in this embodiment, the payout control CPU 371 returns the backup R to restore the interrupt permission / prohibition state at the time of the previous power-off.
The value of the parity flag stored in the AM is checked (step S862). If the parity flag is clear, interrupt permission setting is performed (step S863). on the other hand,
If the parity flag is on, the process proceeds to step S
The payout state restoring process is terminated (with the interrupt prohibited state set in 701a).

Here, the payout state restoring processing program is configured to return to the payout control main processing when the payout state restoring processing is completed, but the stack pointer stored in the power supply stop processing points out. It is also possible to return to the address stored in the stack area (in the backup RAM area) (the address that was being executed when the NMI interrupt occurred when the power was turned off).

As described above, in this embodiment, when the value of the timer counter register CLK / TRG2 of the CTC as the specific register becomes a predetermined value (0 in this example), the command reception processing is performed by the payout control CPU 371. It takes an interrupt. The CTC is easy to perform priority management with other interrupts. By using the CTC, a command reception processing method that easily has a high priority and that can easily set an interrupt trigger is realized. be able to.

In each of the embodiments, the payout control means has been described as an example. However, other electric component control means, for example,
The display control means, the voice control means, the lamp control means and the like can also reliably and quickly receive the control command from the game control means by the above-described processing. The display control unit, the sound control unit, the lamp control unit, and the like are also configured to perform the above-described power supply monitoring control, and output a clear signal in the power failure occurrence NMI process to be controlled by the respective electric component control units. The operation of the electric component may be stopped. With such a configuration, the operation of each of the electric components can be stopped before the stop state, and the power can be restored in an appropriate stop state.

In the above embodiment, the power supply monitoring circuit is provided on the power supply board 910. However, the power supply monitoring circuit may be provided on the electric component control boards such as the main board 31 and the payout control board 37. . When an electric component control board on which a power supply circuit is mounted is configured, the power supply board includes
No power monitoring circuit is installed.

The pachinko gaming machine 1 of each of the above embodiments
Is a first-class pachinko gaming machine in which a predetermined game value can be given to a player when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a start winning prize is a predetermined symbol combination. However, if there is a prize in a predetermined area of the electric accessory that is opened based on a winning start, a second-type pachinko gaming machine that can give a predetermined game value to a player, or is variably displayed based on a starting prize. The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize for a predetermined electric accessory which is opened when a symbol combination of a predetermined symbol is released.

Further, the present invention is not limited to the pachinko gaming machine, but can be applied to a slot machine or the like in a case where an electric component which performs some operation is provided.

[0317]

As described above, according to the present invention, the electric machine control means executes the predetermined periodical interrupt processing in response to the interrupt generated at the predetermined cycle, and the game control means. To execute a command receiving process for receiving a command output by the game control means in response to an interrupt based on an input of a capture signal from the CPU, and to execute the command receiving process in preference to the periodic interrupt process With this configuration, the electric component control unit has an effect that the command from the game control unit can be reliably received.

If the electric component control means is configured not to permit an interrupt until the command reception processing is completed, no other processing is performed during the command reception processing, and The command from the control means can be received without fail.

When an interruption based on the input of the fetch signal occurs during the execution of the periodic interrupt processing, the electric component control means is configured to interrupt the periodic interrupt processing and execute the command receiving processing. In this case, the command receiving process is started immediately even during another interrupt process, so that the command from the game control means can be received without fail.

In the case where the periodic interrupt processing is configured to be executed in the interrupt enabled state, if a capture signal is input during the execution of the periodic interrupt processing, the command reception processing based on the signal can be started. , The command from the game control means can be received without fail.

If the electric component control means is configured to execute processing related to electric component control in response to an interrupt generated at a predetermined cycle, the electric component control is executed at regular intervals. There is no bias in the execution of the processing.

The priority of each interrupt generating unit can be set, and the priority of the interrupt generating unit that generates the interrupt for the command reception interrupt is determined by the interrupt for the periodic interrupt processing. If the configuration is such that the priority is set higher than the priority of the interrupt generating unit to be generated, it is possible to easily realize a configuration in which the command receiving process is executed with priority over the periodic interrupt process. .

[0323] The electric component control means includes updating means for updating the value of the specific register in response to the input of the fetch signal from the game control means. When configured to execute a command receiving process for receiving the command output by the control unit, the electric component control unit can easily and quickly receive the command. Further, since the execution timing of the command receiving process can be created only by setting the initial value in the specific register, the development of the electric component control means is easy, and as a result, the development of the gaming machine is facilitated.

When the electric component control means is configured to set an initial value in a specific register in the initial setting process, it is possible to easily set the execution trigger of the command receiving process.

If the electrical component control means is configured to be able to store a plurality of input command data simultaneously, the received command data is lost even if the control processing in the electrical component control means is delayed. The electric component control means can surely perform the processing based on the received command.

When the command receiving process is configured to include a command determining process for determining whether or not the input command data is proper command data, a command receiving error of the electric component control means is determined. Can be prevented,
This prevents erroneous control from being executed.

When one piece of command information sent to the electric component control means is composed of two pieces of command data, for example, the command information is divided into a command classification and a command type to simplify the command reception processing. This makes it possible to perform a received command check based on the mutual relationship between two command data, and perform an appropriate command information transmission / reception process.

If the game control means is configured to be able to output the first command data and the next command data in an identifiable manner, each electric component control means checks the received command. It can be done easily.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a front view showing a configuration around an intermediate base unit installed on a mechanism plate.

FIG. 5 is an exploded perspective view showing a ball payout device.

FIG. 6 is a block diagram showing a circuit configuration of a game control board (main board).

FIG. 7 is a block diagram showing a circuit configuration in a display control board.

FIG. 8 is a block diagram showing a circuit configuration in the lamp control board.

FIG. 9 is a block diagram showing a circuit configuration in the audio control board.

FIG. 10 is a block diagram showing components related to a prize ball, such as components of a payout control board and a ball payout device.

FIG. 11 is a block diagram showing a configuration example around a CPU for power supply monitoring and power supply backup.

FIG. 12 is a block diagram illustrating a configuration example of a power supply board.

FIG. 13 is a flowchart illustrating an example of a main process executed by a CPU on a main board.

FIG. 14 is an explanatory diagram showing an example of a method for determining whether or not to execute a game state restoration process.

FIG. 15 is a flowchart illustrating an example of an initial setting process.

FIG. 16 is a flowchart illustrating an example of an initialization process.

FIG. 17 is a flowchart illustrating an example of a 2 ms timer interrupt process.

FIG. 18 is a flowchart illustrating an example of a game control process.

FIG. 19 is an explanatory diagram showing a configuration example of a payout control command.

FIG. 20 is a timing chart showing a relationship between a control signal and an INT signal.

FIG. 21 is an explanatory diagram showing an example of the content of a payout control command.

FIG. 22 is an explanatory diagram showing an example of the content of a display control command.

FIG. 23 is an explanatory diagram showing an example of the contents of a lamp control command.

FIG. 24 is an explanatory diagram showing an example of the content of a voice control command.

FIG. 25 is a flowchart showing a special symbol process process.

FIG. 26 is a flowchart showing a switch process.

FIG. 27 is a flowchart showing winning ball signal processing.

FIG. 28 is an explanatory diagram showing a configuration of a command transmission table.

FIG. 29 is a flowchart showing a command control process.

FIG. 30 is a flowchart showing a command transmission process.

FIG. 31 is a block diagram showing a configuration example around a payout control CPU for power supply monitoring and power supply backup.

FIG. 32 is an explanatory diagram for describing generation of an interrupt based on input of an INT signal.

FIG. 33 is a flowchart illustrating an example of main processing executed by a payout control CPU.

FIG. 34 is a flowchart illustrating an example of an initial setting process of a payout control CPU.

FIG. 35 is a flowchart illustrating an example of initialization processing of a payout control CPU.

FIG. 36 is a flowchart illustrating an example of a timer interruption process of a payout control CPU.

FIG. 37 is an explanatory diagram showing one configuration example of a RAM in the payout control means.

FIG. 38 is an explanatory diagram illustrating a configuration example of a reception buffer.

FIG. 39 is a flowchart illustrating an example of a command receiving process of the payout control CPU.

FIG. 40 is a flowchart illustrating an example of a payout control process executed by a payout control CPU.

FIG. 41 is a flowchart illustrating an example of a switch process.

FIG. 42 is a flowchart illustrating an example of a command analysis execution process.

FIG. 43 is a flowchart illustrating an example of a payout stop state setting process.

FIG. 44 is a flowchart showing an example of a prepaid card unit control process.

FIG. 45 is a flowchart illustrating an example of a ball lending control process.

FIG. 46 is a flowchart illustrating an example of a ball lending control process.

FIG. 47 is a flowchart illustrating an example of a winning ball control process.

FIG. 48 is a flowchart illustrating an example of a winning ball control process.

FIG. 49 is a power outage occurrence NM executed by a payout control CPU.
It is a flowchart which shows the example of I processing.

FIG. 50 is an explanatory diagram for describing an example of a backup parity data creation method.

FIG. 51 is a flowchart illustrating an example of a payout state restoration process executed by a payout control CPU.

[Explanation of symbols]

 1 Pachinko gaming machine 31 Main board 37 Payout control board 53 Basic circuit 56 CPU 371 Payout control CPU 570 Output port (Output port 0) 571 Output port (Output port 1) 572 Output port (Output port 2) 573 Output port (Output) Port 3) 574 output port (output port 4) 902 power supply monitoring IC 910 power supply board

Claims (12)

[Claims] 1. A game machine in which a player can play a predetermined game, a game control means for controlling the progress of the game, and an electric component control process for controlling an electric component provided in the game machine. The game control means executes a command output process for outputting command data and a capture signal designating capture of command data to the electrical component control means, The electric component control means executes a predetermined periodic interrupt process in response to an interrupt generated in a predetermined cycle, and the game control means responds to an interrupt based on an input of a capture signal from the game control means. A gaming machine, comprising: executing a command receiving process for receiving an output command; and executing the command receiving process with priority over the periodic interrupt process. 2. The gaming machine according to claim 1, wherein the electric component control means does not permit the interruption until the command receiving process is completed. 3. An electric component control means for interrupting a periodic interrupt process and executing a command receiving process when an interrupt based on an input of a capture signal occurs during the execution of the periodic interrupt process. The gaming machine according to claim 2. 4. The gaming machine according to claim 1, wherein the periodic interruption processing is executed in an interruption permission state. 5. The gaming machine according to claim 1, wherein the electric component control means executes a process related to electric component control in response to an interrupt generated in a predetermined cycle. 6. The electric component control means includes a plurality of interrupt generating units capable of generating an interrupt, wherein the priority order of each of the interrupt generating units can be set, and 6. The gaming machine according to claim 1, wherein the priority of the interrupt generating unit that generates the interrupt is set higher than the priority of the interrupt generating unit that generates the interrupt for the periodic interrupt processing. . 7. The electric component control means includes updating means for updating a value of a specific register in response to an input of a capture signal from the game control means, and in response to the value of the specific register reaching a predetermined value. And executing a command receiving process for receiving a command output by said game control means.
A gaming machine according to claim 6. 8. The electric component control means includes:
The gaming machine according to claim 7, wherein an initial value is set in the specific register. 9. The gaming machine according to claim 1, wherein the electric component control means can simultaneously store a plurality of input command data. 10. The gaming machine according to claim 1, wherein the command receiving process includes a command determining process for determining whether the input command data is proper command data. 11. The gaming machine according to claim 1, wherein one piece of command information sent to the electric component control means is composed of two pieces of command data. 12. The game machine according to claim 11, wherein the game control means can output the first command data and the next command data in an identifiable manner.