JP2001314611A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the pattern of sensing or receiving signals between a switch, a display device and a dispensing demand processor in a player's operation of demanding for the dispensing of game media. SOLUTION: A card balance display signal and a ball dispensable display signal from a card unit 50 indicating the balance of a prepaid card pass through a payout control substrate 37 but are transmitted to a balance display substrate 74 through none of a CPU 371 for payout control. A ball dispensing switch signal and a return switch signal fed from the balance display substrate 74 are also transmitted to the card unit 50 through none of the CPU 371 for payout control. As a result, the payout control substrate 37 serves as relay substrate but this leads to no complication of signals in the payout control substrate 37.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine, a coin game machine, a slot machine, etc., in which a game is played in accordance with a player's operation. A gaming machine in which a game is played in accordance with a game machine.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is fired into a game area by a launching device, and when a game medium wins in a winning area such as a winning opening provided in the game area, a predetermined number of prize balls Some values are paid out to players. The payout of the game medium is performed by a payout mechanism.

The payout mechanism is generally controlled by prize ball control means mounted on a payout control board. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means and transmitted to the payout control board.

[0004] Further, a player borrows a game medium and plays a game using the borrowed game medium and the game medium paid out according to a prize. At this time, a request for lending a game medium from a player is once received by a lending request processing device such as a card unit, and the lending control means of the gaming machine receives a lending request from the player by communicating with the lending request processing device. A gaming machine lends a game medium in response to a lending request from a player. In many cases, the prize ball control means and the lending control means are constituted by an integrated payout control means. Generally, the payout control means includes a payout control microcomputer.

[0005] The gaming machine is provided with a switch or the like for a player to input a game medium lending request. Further, a display unit or the like for displaying a lending available amount or the like according to the remaining amount of the prepaid card inserted in the lending request processing device such as a card unit is also provided. Generally, switches and indicators are mounted on a board installed in a gaming machine. Therefore,
A signal line is wired between the board and the lending request processing device.

[0006]

The switches and indicators are:
It is often installed on the front side of the gaming machine, such as near the operation handle, so that the player can easily operate and visually recognize it. Therefore, a board on which a switch and a display are mounted is also installed in the vicinity. Accordingly, since the distance from the board to the lending request processing device is relatively large, a relay board is often provided between them. Then, since the relay board needs to be installed, the cost of the gaming machine increases. In addition, connectors are provided on the input side and output side for signal input to such a relay board, but since there are already many connectors inside the gaming machine, the number of connectors further increases, so wiring errors (connector insertion) Mistakes) are also likely to occur.

[0007] Therefore, the present invention simplifies the form of signal exchange between a switch or display for allowing a player to perform a game medium lending request operation and a lending request processing device, thereby reducing the cost of a gaming machine. It is another object of the present invention to provide a gaming machine capable of reducing wiring errors.

[0008]

A gaming machine according to the present invention comprises:
A game machine in which a player can perform a predetermined game, wherein a game control board on which game control means for controlling the progress of the game is mounted, and a game medium in accordance with establishment of a payout condition relating to the game. Game medium payout mechanism to pay out to the player, a lending mechanism to pay out game media to be lent to the player, and a payout to control the prize game medium payout mechanism and the lending mechanism to perform processing related to the payout of game media. A payout control board equipped with control means, and an operation board equipped with an electric component for detecting an operation in which a player borrows a game medium,
Signal transmission between the operation board and the lending request processing device that receives a game medium lending request of the player is performed via the payout control board.

The signal transmission between the operation board and the lending request processing device may pass through the payout control board without passing through the payout control means.

[0010] The operation board is installed on the front side of the gaming machine, for example, inside the gaming machine, and has a configuration in which at least detecting means for detecting an operation of the player is mounted.

The payout control means controls the prize game medium payout mechanism based on the number of game media notified from the game control means to perform prize game medium payout processing and can store the number of unpaid prize game media. And controlling the lending mechanism unit based on a request from the lending request processing device to perform a game medium lending process and to store the number of unpaid loaned game media, wherein each unpaid number is a payout control unit. May be configured to be stored in backup storage means capable of storing the stored contents even when power supply to the power supply is stopped.

The payout control means can continuously perform a predetermined unit of game medium lending processing a plurality of times based on a request from the lending request processing device, and the unpaid number of game media is related to a predetermined unit of lending. The remaining number may be configured.

A prize game medium supply state detecting means for detecting a state of the game medium supplied to the prize game medium payout mechanism, and a rental game medium for detecting a state of the game medium supplied to the rental mechanism. Supply state detecting means, and the prize game medium supply state detecting means can detect whether or not the predetermined number of game media that can be paid out by the prize game medium payout mechanism section is equal to or more than one unit of the prize payout. At a position where the lending game medium supply state detecting means can detect whether or not the required number of game media that can be paid out by the lending mechanism unit is equal to or more than one unit of the game medium lending process. It may be configured as provided.

The predetermined number relating to the prize game medium payout process may be different from the required number relating to the game medium lending process.

[0015]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as viewed from the front. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing storage balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6. Although not shown in FIG. 1, a frequency display LED for lending a ball via the card unit 50 is provided on the upper surface side of the hit ball supply tray 3.
A ball lending switch and a return switch are provided.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In addition, a pass storage display (ordinary symbol storage display) 41 including four LEDs is provided below the variable display 10. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In the passage between the passage gate 11 and the ball exit 13, there is a gate switch 12 for detecting a hit ball passing through the passage gate 11. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6 and is turned on by the starting port switch 17.
Is detected by In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14.
The variable winning ball device 15 is opened by the solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the game balls to the respective winning ports 19 and 24 is determined by correspondingly provided winning port switches 19a and 19a.
24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. Also, on the upper left and right sides outside the game area 7,
Two speakers 27 that emit sound effects are provided.
A game effect LED 28a and game effect lamps 28b and 28c are provided on the outer periphery of the game area 7.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a premium ball is paid out, and a ball out lamp 52 which is lit up when the supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming table 1 and enables lending of a ball by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is usable. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols accompanied by a probability change, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, each board disposed on the back of the pachinko gaming machine 1 will be described. As shown in FIG. 2, on the back surface of the pachinko gaming machine 1, a ball storage tank 38 is provided above the mechanism plate in the frame 2A, and above the pachinko gaming machine 1 installed on the gaming machine installation island. The game ball is supplied to the ball storage tank 38 from. The game balls in the ball storage tank 38 pass through a guiding gutter 39 to reach a ball payout mechanism (not shown).

On the back side of the gaming machine, a variable display control unit 29 for controlling the variable display section 9 and a game control board (main board) 31 on which a game control microcomputer and the like are mounted are installed. A payout control board 37 on which a payout control microcomputer or the like for performing ball payout control is mounted;
And a hit ball launching device that launches a hit ball into the game area 7 using the rotational force of a motor. Furthermore, the decoration lamp 25, the game effect LED 28a, the game effect lamp 28
b, 28c, a lamp control board 35 for sending signals to the prize ball lamp 51 and the ball out lamp 52, a voice control board 70 for controlling the generation of voice from the speaker 27, and a launch control for controlling the hit ball launching device. A substrate 91 is also provided. Note that an error display LED 374 is also mounted on the payout control board 37.

Further, DC30V, DC21V, DC1
A power supply board 910 on which a power supply circuit for generating 2V and 5V DC is mounted is provided, and a terminal board 1 provided with terminals for outputting various information to the outside of the gaming machine is provided above.
60 are installed. The terminal board 160 has at least a ball-cutting terminal for introducing and outputting the output of a ball-out detection switch 167 described later, a prize-ball terminal for externally outputting a prize-ball number signal, and a ball lending number signal. Ball lending terminals for external output. In the vicinity of the center, an information terminal board (external information output device) 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed. In FIG. 2, signals from the lamp control board 35 and the sound control board 70 are transmitted to the game effect LEDs 28 provided on the frame side.
a, an illuminated relay board A for supplying to the game effect lamps 28b and 28c, the prize ball lamp 51 and the ball cut lamp 52
77 and balance display board 7 equipped with frequency display LED and the like
Although 4 is shown, other relay boards may be provided as needed for signal relay.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine 1 as viewed from the rear. The balls stored in the ball storage tank 38 pass through the guiding gutter 39 and reach the ball payout mechanism 97. The game balls paid out from the ball payout mechanism 97 are supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls are paid out based on the prize, and the hitting ball supply tray 3 becomes full. Finally, after the game balls reach the contact port 45, the game balls are further paid out. It is led to the ball tray 4. When the game balls are further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In that state, the ball payout mechanism 97
The rotation of the stepping motor of the prize ball dispensing device (not shown) stops, the operation of the prize ball dispensing device stops, and the driving of the hit ball firing device 34 also stops.

Next, the structure of the intermediate base unit installed on the mechanism plate 36 will be described. The intermediate base unit is provided with a ball payout mechanism 97 and a ball passing path above it. In this embodiment, as described later,
In the ball payout mechanism 97, a prize ball payout device and a ball rental payout device are provided independently. FIG. 4 is a configuration diagram showing a configuration of a prize ball payout device and a ball passing path above the device.

At the upper part of the intermediate base unit, a passage body 184A serving as a prize ball path is provided. A winning ball payout device 97A is fixed to a lower portion of the passage body 184A. The passage body 184A is divided into four rows by the curve gutter 174 (see FIG. 3), and the payout ball paths 186a and 186a for letting down two rows of game balls of which the downflow direction is changed to the left and right.
186b. On the upstream side of the dispensing ball passages 186a and 186b, ball disconnection switches 187a and 187b are provided. The ball out switches 187a and 187b detect the presence or absence of game balls in the payout ball passages 186a and 186b. When the ball out switches 187a and 187b stop detecting game balls, the prize balls in the prize ball payout device 97A. The rotation of the motor (not shown in FIG. 4) is stopped, and the prize ball payout is immobilized.

Note that the ball out switches 187a, 187b
Is locked by a locking piece 188A at a position where it can be detected that about 27 to 28 game balls are present in the payout ball paths 186a and 186b. That is, the ball out switches 187a and 187b are installed at positions where it can be confirmed that the maximum payout amount of one unit of the prize ball (15 in this embodiment) is secured.

The central portion of the passage body 184A is formed to have a shape curved left and right so as to reduce the ball pressure of the game ball flowing down inside. Although the passage body 184A is fixed to the intermediate base unit, the positioning of the passage body 184A can be performed by a locking projection 185A provided on the intermediate base unit.

Below the passage body 184A, the ball stopping device 1 that supplies game balls to the prize ball dispensing device 97A and stops the supply of game balls to the prize ball dispensing device 97A in the event of a failure or the like.
90A is provided. The prize ball dispensing device 97A installed below the ball stopping device 190A has a rectangular parallelepiped case 1.
98A. Protrusions are provided at four places on the left and right of the case 198A. The lower end of the case 198A is fitted into an elastic engagement piece provided at a lower portion of the intermediate base unit with each projection being related to a positioning projection provided on the intermediate base unit.

FIG. 5 is an exploded perspective view of the prize ball payout device 97A. The configuration and operation of the winning ball payout device 97A will be described with reference to FIG. The prize ball payout device 97A in this embodiment includes a stepping motor (prize ball motor) 28.
9A rotates the screw 288 to pay out pachinko balls one by one.

As shown in FIG. 5, the prize ball payout device 97A
Has two cases 198a and 198b. Engagement protrusions 280 are provided at two positions on the left and right of each of the cases 198a and 198b, which are in contact with positioning protrusions provided above the installation position of the winning ball payout device 97A. Also,
In each case 198a, 198b, the ball supply path 2
81a and 281b are formed. Ball supply path 281
a, 281b have curved surfaces 282a, 282b, and ball feed horizontal paths 284a, 284b are formed below the ends of the curved surfaces 282a, 282b. Further, the ball discharge horizontal path 284a, 284b at the end of the ball discharge path 283a,
283b are formed.

The ball supply paths 281a and 281b, the ball feed horizontal paths 284a and 284b, and the ball discharge paths 283a and 283b.
Are formed in front of partition walls 295a and 295b that partition the cases 198a and 198b forward and backward, respectively.
Further, in front of the partition walls 295a and 295b, the ball pressure buffering member 285 is sandwiched between the cases 198a and 198b. The ball pressure buffering member 285 distributes the game balls supplied to the prize ball payout device 97A to the left and right sides, and
1a and 281b.

Below the ball pressure buffer member 285, a winning ball motor position sensor including a light emitting element (LED) 286 and a light receiving element (not shown) is provided. Light emitting element 2
86 and the light receiving element are provided at a predetermined interval. The distal end of the screw 288 is inserted into the space. The ball pressure buffer member 28
When the cases 198a and 198b are attached to each other, the case 5 is completely stored and fixed therein.

The ball feed horizontal paths 284a and 284b have a screw 2 rotated by a prize ball motor 289A.
88 are arranged. The prize ball motor 289A is fixed to a motor fixing plate 290, and the motor fixing plate 290 is fixed to a fixing groove 291 formed behind the partition walls 295a and 295b.
a, 291b. Payout motor 2 in that state
Since the motor shaft 89 protrudes forward of the partition walls 295a and 295b, the screw 288 is fixed in front of the protruding walls. On the outer periphery of the screw 288, a prize ball motor 28
The spiral projection 2 for moving the game balls placed on the ball feed horizontal paths 284a and 284b forward by the rotation of 9A.
88a are provided.

A recess is formed at the tip of the screw 288 so as to house the light emitting element 286, and two notches 292 are formed 180 degrees apart from each other on the outer periphery of the recess. Therefore, while the screw 288 makes one rotation, the light from the light emitting element 286 is
Is detected twice by the light receiving element via the.

That is, the prize ball motor position sensor including the light emitting element 286 and the light receiving element is for stopping the screw 288 at a fixed position and detecting that the prize ball payout operation has been performed. is there. The light emitting element 28
6. The wiring from the light receiving element and the prize ball motor 289A
They are put together and pulled out to the outside through drawer holes formed below the rear part of the case 198a, 198b and connected to the connector.

A game ball is a ball feeding horizontal path 284a, 284b.
When the prize ball motor 289A rotates in the state of being placed on the game ball, the game ball moves forward on the ball feed horizontal paths 284a and 284b by the spiral projection 288a of the screw 288. And finally, the ball discharge horizontal paths 284a, 284b from the end of the ball discharge path 283a, 28
3b. At this time, left and right ball feed horizontal paths 284
a, 284b fall alternately. That is,
Each time the screw 288 makes a half turn, one game ball falls from one side. Therefore, every time one game ball falls,
Light from the light emitting element 286 is detected by the light receiving element.

As shown in FIG. 4, below the prize ball payout device 97A, a prize ball count switch 3 by a proximity switch is provided.
01A is provided. The payout control means can determine the number of paid out prize balls from the detection output of the prize ball count switch 301A.

In this embodiment, a prize ball payout device 97A in which game balls are paid out by rotation of a stepping motor is used as a ball payout device for paying out game balls by driving an electric drive source. A ball payout device having a structure in which game balls are sent out by another drive source may be used, or a payout device having a structure in which a stopper is removed by driving an electric drive source and payout is performed by the weight of the game balls may be used.

FIG. 6 is a configuration diagram showing a configuration of a ball lending and dispensing device and a ball passing path above the device. A rental ball dispensing device 97B is fixed to a lower portion of a passage body 184C serving as a rental ball route. The passage body 184B has payout ball passages 186c and 186d through which two rows of game balls flow down. On the upstream side of the payout ball passages 186c and 186d, a ball out switch 1
87c and 187d are provided. Ball switch 1
87c and 187d detect the presence or absence of a game ball in the payout ball passages 186c and 186d. When the ball out switch 187c or 187d stops detecting the game ball, the ball lending motor in the lending ball payout device 97B (FIG. The rotation of the rental ball is immobilized by stopping the rotation (not shown in FIG. 6).

Note that the ball cut switches 187c, 187d
Is locked by a locking piece 188C at a position where it can be detected that about 27 to 28 game balls exist in the payout ball paths 186c and 186d. That is, the ball out switches 187c and 187d are installed at positions where it is possible to confirm that the maximum payout amount of one unit of ball lending (25 in this embodiment) or more is secured.

The central portion of the passage body 184C is formed in a shape curved right and left so as to reduce the ball pressure of the game ball flowing down inside. Although the passage body 184C is fixed to the intermediate base unit, it is also possible to position the passage body 184C by a locking projection 185C provided on the intermediate base unit. Note that the rental ball dispensing device 97
C may be installed beside the prize ball payout device 97A or, if the installation space is insufficient, the prize ball payout device 9
It may be installed so as to be overlaid on 7A.

Below the passage body 184C, there is provided a ball stopping device 190C for supplying game balls to the rental ball dispensing device 97C and stopping the supply of game balls to the rental ball dispensing device 97C in the event of a failure or the like. I have. The rental ball dispensing device 97C installed below the ball stopping device 190C is housed inside a rectangular parallelepiped case 198C.

The structure of the rental ball payout device 97C may be the same as the configuration of the prize ball payout device 97A shown in FIG. That is, a stepping motor (ball lending motor) 289C having the same configuration as the prize ball motor 289A rotates the screw 288 to pay out pachinko balls one by one. Further, the ball lending motor position sensor including the light emitting element 286 and the light receiving element is used for stopping the screw 288 at a fixed position and for detecting that the ball lending payout operation has been performed. A ball lending count switch 301B using a proximity switch is provided below the ball lending device 97C. The payout control means, based on the detection output of the ball lending count switch 301B,
It is possible to ascertain the actual number of loaned balls.

The dispensing mechanism can be configured as shown in FIG. In the configuration example shown in FIG.
The distance between 7c, 187d and the lending ball payout device 97C is longer than the distance between the ball out switches 187a, 187b and the prize ball payout device 97A. Then, for example, the ball out switches 187c and 187d are connected to the payout ball passage 186.
c, 186d are locked at positions where it is possible to detect the presence of about 27 to 28 game balls, and the ball cut-out switches 187a, 187b are used to pay out ball paths 186a, 186b.
Is locked at a position where it can be detected that about 17 to 18 game balls exist. In other words, the remaining number when the running out of balls for the prize ball is detected is different from the remaining number when the running out of balls for the ball lending is detected. Since the number of game balls in each unit is different, it is reasonable to configure the payout mechanism to make the remaining numbers different.

The other structure is the same as the structure shown in FIGS. In addition, the rental ball dispensing device 97
C may be installed beside the prize ball payout device 97A or, if the installation space is insufficient, the prize ball payout device 9
It may be installed so as to be overlaid on 7A.

Further, the payout mechanism may be configured as shown in FIG. In the configuration example shown in FIG. 8, the ball passage on the upper side of the prize ball dispensing device 97A and the ball passage on the upper side of the rental ball dispensing device 97C are one. Therefore, the game ball flowing down in one line is divided into two lines in the payout mechanism.
And before the ball is split into two sections, the ball switch 1
87 are installed. In this case, the same detector detects a broken ball for award balls and a broken ball for lending. Therefore, the configuration and control for detecting a broken ball can be simplified.

The distance between the out-of-ball switch 187 and the rental ball payout device 97C is longer than the distance between the out-of-ball switch 187 and the prize ball payout device 97A. Then, for example, the out-of-ball switch 187 is connected to the payout ball passage 186c,
It is possible to detect that about 27 to 28 game balls exist in 186d, and to add 17 game balls to payout ball paths 186a and 186b.
It is locked at a position where it can be detected that about 18 game balls exist. Other configurations are shown in FIGS.
Is the same as the configuration shown in FIG.

FIG. 9 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 9 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
And a switch circuit 58 for giving signals from the gate switch 12, the starting port switch 17, the V count switch 22, the count switch 23, the winning port switches 19a and 24a, and the prize ball count switch 301A to the basic circuit 53. And a solenoid circuit 59 for driving the solenoid 16 for opening and closing the variable winning ball device 15 and the solenoid 21 for opening and closing the opening and closing plate 20 in accordance with a command from the basic circuit 53.

According to the data supplied from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display on the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to the program, and an I / O port unit 5.
7 inclusive. In this embodiment, the ROM 54 and the RAM 5
5 is built in the CPU 56. That is, the CPU 5
Reference numeral 6 denotes a one-chip microcomputer. In addition, 1
The chip microcomputer has at least the RAM 55
And the ROM 54 and the I / O port unit 57 may be external or internal. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 includes a system reset circuit 65 for resetting the basic circuit 53 when the power is turned on, and an I / O port unit 57 which decodes an address signal supplied from the basic circuit 53 and decodes the address signal. I /
An address decode circuit 67 for outputting a signal for selecting the O port is provided. Note that the ball payout device 9
There is also switch information input to the main board 31 from 7,
In FIG. 9, they are omitted.

A hit ball launching device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 is used to display the start storage display 18, the gate passage storage display 41 and the decoration lamp 25 provided on the game board. Controls the game and the game effect lamp / LED 28 provided on the frame side.
a, 28b, and 28c, display control of the award ball lamp 51, and the ball out lamp 52 are performed. The display control of the variable display unit 9 for variably displaying special symbols and the variable display 10 for variably displaying ordinary symbols is performed by display control means mounted on the display control board 80.

FIG. 10 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 10, the detection signal from the full tank switch 48 is input to the I / O port 57 of the main board 31 via the relay board 71. The full tank switch 48 is a switch that detects whether the excess ball tray 4 is full. In addition, detection signals from the ball cut switches 187a and 187b are also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. Here, it is assumed that the payout mechanism has a configuration in which a winning ball payout mechanism as shown in FIG. 4 and a ball lending mechanism as shown in FIG. 6 are provided independently.

The CPU 56 of the main board 31 pays out when the detection signals from the ball out switches 187a and 187b indicate that the ball is out, or the detection signal from the full switch 48 indicates the full state. A payout control command for prohibition is transmitted. When receiving the payout control command instructing the payout prohibition, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. The prize ball count switch 301A is provided below the prize ball payout device 97A, and detects a prize ball payout ball actually paid out.

When there is a prize, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
, A payout control command indicating the number of winning balls is input. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal). The payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371
A payout control command is input via the / O port 372a, and the ball payout device 97 is driven in accordance with the payout control command to perform award ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and has at least a RAM.

In the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside 70 and 571. As the buffer circuits 620 and 68A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal inputted from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 is connected to the output port 3
A ball lending number signal indicating the lending ball number is output to the terminal board 160 via the 72g and the information output circuit 377,
The buzzer drive signal is output to the buzzer board 75. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the payout control board 37
72b, through the relay board 72, the ball out switch 1
87c and 187d, detection signals from the award ball count switch 301A and the ball lending count switch 301B are input. The ball lending count switch 301B is provided at a lower portion of the ball lending device 97C, and detects a ball lending actually paid out. Drive signals from the payout control board 37 to the prize ball motor 289A and the ball lending motor 289B are
It is transmitted to the prize ball motor 289A and the ball lending motor 289B via the output port 372c and the relay board 72.

The card unit 50 is provided with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the operation of the player, a ball lending switch signal and a return switch signal are given via the payout control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connection state / non-connection state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the payout control board 37. The payout control CPU 3 of the payout control board 37
When the EXS signal to the card unit 50 rises and the falling of the BRQ signal from the card unit 50 is detected, the ball rental motor 289B is driven to pay out a predetermined number of rental balls to the player. When the payout is completed, the payout control CPU 371 sets the card unit 50
EXS signal is dropped. Thereafter, if the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed.

As described above, the signal from the card unit 50 is input to the payout control board 37 directly connected to the card unit 50. Therefore,
Regarding ball lending control, the card unit 50 sends the main board 3
No signal is input to 1, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31.

The card balance display signal indicating the balance of the prepaid card and the ball lending permission display signal are transmitted to the balance display board 74 without passing through the payout control CPU 371. The ball lending switch signal and the return switch signal sent from the balance display board 74 are also transmitted to the payout control CPU 371.
Is transmitted to the card unit 50 without going through.

As shown in FIG. 10, in this embodiment, the output of the prize ball count switch 301A is
The output of the ball rental count switch 301B is output only to the payout control board 37. Therefore, the main substrate 31
Can be confirmed based on the output of the prize ball count switch 301A that the prize balls to be paid out have been reliably paid out.

The payout control means mounted on the payout control board 37 determines whether or not the required number of game balls have been paid out from the card unit 50 based on the output of the ball lending count switch 301B. Can be confirmed, and various abnormalities related to the ball lending mechanism can be detected. Further, in this embodiment,
The output of the prize ball count switch 301A is the payout control board 3
7, the payout control means can confirm various abnormalities related to the winning ball mechanism based on the output of the winning ball count switch 301A.

In this embodiment, the case where the card unit 50 is installed separately from the gaming machine and adjacent to the gaming machine is described as an example, but the card unit 50 is integrated with the gaming machine. You may. Also, the present invention can be applied to a case where a gaming machine rents a game ball corresponding to the amount of money when a coin is inserted.

In this embodiment, at least the main substrate 3
1 and the RAM in the payout control board 37 are backed up by a backup power supply. That is, even if the power supply to the gaming machine is stopped, the contents of the RAM are stored for a predetermined period. When detecting a drop in the power supply voltage, each CPU performs a predetermined process, and then enters a power recovery wait state. When the power is turned on, each CPU
If the data is stored in the memory, the state before the power is turned off is restored based on the stored data.

As described above, the payout control board 3
7. The main board 31 for sending commands to the display control board 80, the lamp control board 35, and the voice control board 70
An INT signal is output from each output port (output port 0) 570 to each electric component control board. In this case, for example,
The output port 570 has an 8-bit configuration, where bit 0 is an INT signal to the payout control board 37, bit 1 is an INT signal to the display control board 80, and bit 2 is a lamp control board 3
The INT signal to bit 5, bit 3 is the I signal to voice control board 70
Used for outputting the NT signal.

FIG. 11 is a block diagram showing an example of the configuration around the CPU 56. As shown in FIG. 11, a voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) is output to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56.
It is connected to the. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of various DC power supplies used by the gaming machine and detects a drop in the power supply voltage. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value falls below a predetermined value, a low-level voltage drop signal is generated. VSL
Is the largest DC voltage used in gaming machines, and is +30 V in this example. Therefore, the CPU 56
Can confirm the occurrence of power interruption by interrupt processing. In this embodiment, the first power supply monitoring circuit is mounted on a power supply board described later.

FIG. 11 also shows a system reset circuit 65, but in this embodiment, the system reset circuit 65 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, the reset IC 651
When the power is turned on, the output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level after the predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage of VSL, which is the same power supply voltage as the power supply voltage monitored by the first power supply monitoring circuit, and sets the voltage value to a predetermined value (the first power supply monitoring circuit outputs a voltage drop signal). When the voltage falls below the power supply voltage value), a low-level voltage drop signal is generated. Accordingly, the CPU 56 performs a predetermined power supply stop processing in response to the voltage drop signal from the first power supply monitoring circuit, and then performs a system reset. In this embodiment, the reset signal and the voltage drop signal from the second power supply monitoring circuit are the same signal.

As shown in FIG. 11, the reset IC 651
Is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. When the input to the clear terminal goes low, the counter IC 941 counts the clock signal from the oscillator 943.
The Q5 output of the counter IC 941 is output to the NOT circuit 9
45, 946 and input to the NAND circuit 947. The Q6 output of the counter IC 941 is input to a clock terminal of a flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The other input of the OR circuit 949 is connected to the NAND circuit 9.
The output of 47 is introduced via NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, two reset signals (low-level signals) are supplied to the reset terminal of the CPU 56 when the power is turned on.
Starts operation reliably.

Then, for example, the detection voltage of the first power supply monitoring circuit (the voltage at which the voltage drop signal is output) is set to +
22 V, and the detection voltage of the second power supply monitoring circuit is +9 V. In such a configuration, since the first power supply monitoring circuit and the second power supply monitoring circuit monitor the voltage of the same power supply VSL, the timing at which the first voltage monitoring circuit outputs the voltage drop signal The difference between the timings at which the second voltage monitoring circuit and the second voltage monitoring circuit output the voltage drop signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop processing in response to the voltage drop signal from the first power supply monitoring circuit until the power supply stop processing is completely completed.

In this example, the first detection condition that the first power supply monitoring means outputs a detection signal is that the +30 V power supply voltage has dropped to +22 V, and the second power supply monitoring means outputs the detection signal. The second detection condition to be output is that the +30 V power supply voltage has dropped to +9 V.
However, the voltage value used here is an example,
Other values may be used.

However, although the monitoring range is narrowed, the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit is +
It is also possible to use a 5V power supply voltage. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

While power is not supplied from the + 5V power supply which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are maintained even if the power supply to the gaming machine is cut off. Is saved. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to the normal operation state. At that time, since the necessary data is stored in the backup RAM, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

In FIG. 11, when the power is turned on, the CPU 5
6 shows a configuration in which a reset signal (low-level signal) is applied twice to the reset terminal. However, in the case of using a CPU in which reset is surely released even if the reset signal rises only once, , Reference numerals 941 to 9
The circuit element indicated by 49 is unnecessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

CPU 56 used in this embodiment
Incorporates an I / O port (PIO) and a timer / counter circuit (CTC). PIO is PB0-PB
It has a port of 3 4 bits and 1 byte of PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set for both input and output. However, in this embodiment, no built-in PIO is used. In that case, for example, all ports are set to the input mode, and all ports are connected to the ground level. When power is turned on, P
IO is automatically set to input mode.

FIG. 12 is a block diagram showing a configuration example of a power supply board 910 of a gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the audio control board 70, the lamp control board 35, and the payout control board 37, and each of the electric component control boards in the gaming machine and Generates voltages used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21
V, + 12V DC and + 5V DC. Also,
The capacitor 916 serving as a backup power supply is DC + 5
V, that is, charged from a power supply line for driving an IC or the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 22V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
5 is connected to, for example, a relay board, from which electric power of a voltage required for each electric component control board and mechanism components is supplied. A power switch 918 for stopping and starting power supply to the gaming machine is provided on the input side of the transformer 911.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is provided with an electric power so as to be able to hold a storage state in a backup RAM (power-backed-up RAM, that is, storage means that can be in a storage state) when the power supply to the gaming machine is cut off. Backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Note that a battery that can be charged from a + 5V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 has the first
The power supply monitoring IC 902 constituting the power supply monitoring circuit of FIG. The power supply monitoring IC 902 detects the occurrence of power interruption by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), a voltage drop signal is output assuming that power supply is cut off. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after conversion from AC to DC, is used. The voltage drop signal from the power supply monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Therefore, the monitoring range can be extended for the voltage required by the CPU. Therefore,
More precise monitoring can be performed. Furthermore, when VSL (+30 V) is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, when monitoring the voltage of the + 30V power supply,
The drop can be detected at a stage before + 12V generated after the generation of 0V starts to fall. Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state where the switch output is not detected.

Since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the first power supply monitoring circuit supplies a voltage drop signal to the plurality of electric component control boards. Can be. Regardless of how many electric component control boards require a voltage drop signal, it is sufficient that only one first power supply monitoring means is provided, so that each electric component control means in each electric component control board performs a return control described later. Doing so does not add much to the cost of the gaming machine.

In the configuration shown in FIG. 12, the detection output (voltage drop signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control) via the buffer circuits 918 and 919. Transmitted to the board 37). For example, one detection output is transmitted to the relay board,
The same signal may be distributed from the relay board to each electric component control board. Further, a buffer circuit may be provided according to the number of substrates requiring a voltage drop signal.

FIG. 13 is a block diagram showing an example of the configuration of the information output circuit 64 on the main board 31 shown in FIG. In this example, the information output circuit 64 includes an amplifying circuit 64a for amplifying a starting port information signal output from the CPU 56 via the I / O port 57, an amplifying circuit 64b for amplifying the symbol determination number information 1 signal, and the jackpot information 1 Amplifying circuit 64c for amplifying the signal, amplifying circuit 6 for amplifying the probability variation information signal
4d, an amplifying circuit 64e for amplifying two jackpot information signals, an amplifying circuit 64f for amplifying two symbol determination number information signals, and an amplifying circuit 64g for amplifying the accessory number signal. In addition,
Each output of the amplifier circuits 64a to 64g is connected to the information terminal board 34.

The symbol determination frequency information 2 signal is transmitted to the variable display 1
The information on the normal symbol displayed at 0 is the information on the number of occasions of the accessory, and the information on the number of times the variable winning ball device 15 is opened.

Further, an amplifying circuit 64h for amplifying the award ball number signal, a photocoupler 642 which is rendered conductive by the output of the amplifying circuit 64h, and the output terminals are cut off or short-circuited according to the output of the photocoupler 642. Diode bridge 643 is provided. The output of the diode bridge 643 is
Connected to 0. The photocoupler 642 is composed of a light emitting diode and a phototransistor.
At 42, a resistor is connected to one output of the phototransistor. Further, as the amplifier circuit 64h, an IC circuit or a transistor may be used. Further, the prize ball number information may be configured to be output at a voltage level, like the big hit information 1 signal and the like. Note that the amplifier circuit prevents the CPU 56 from malfunctioning due to an overcurrent.

FIG. 14 shows a state in which the main terminal board 31 and the information terminal board 3
4 is a timing chart showing an example of the output timing of each signal externally output through the terminal board 4 or the terminal board 160. FIG.
In this example, as shown in FIG. 14A, the symbol determination frequency signal, the big hit information 1 signal, the big hit information 2 signal, and the probability variation information signal are output as negative logic signals. In this example, when the special symbol displayed on the variable display section 9 stops changing, the symbol determination frequency signal is set to the low level for 0.5 seconds. Also, when 1.5 seconds have elapsed after the change of the special symbol has stopped, the big hit information 1 signal and the big hit information 2 signal are set to the low level, and the big winning opening (in this embodiment, by opening the opening / closing plate 20). When 10.8 seconds have passed since the last closing, the big hit information 1 signal and the big hit information 2 signal are turned off (high level).

At the time of the high probability, the big hit information 2 signal continues to be on even if the big hit game ends. In the high probability state, the probability fluctuation information signal is turned on. Note that the example shown in FIG. 14A is an example in which the probability variation state ends when a symbol other than the specific symbol (probable variation symbol) is hit during the probability variation.

As shown in FIG. 14B, the starting port information signal is also output as a signal of negative logic. In this example, when there is a start winning, the starting winning information signal is set to a low level for 0.5 seconds and then set to a high level for 0.5 seconds. That is, “ON” is output for 0.5 seconds, and subsequently “OFF” is output for 0.5 seconds. In this embodiment, a prize ball number signal indicating the number of game balls paid out according to the winning is also output from the main board 31. And FIG.
As shown in (C), every time the number of payouts reaches 10, the prize ball number signal is set to the low level for 0.1 second, and then to the high level for 0.1 second. That is, for every ten prize balls, "ON" is output for 0.1 second, and subsequently, "OFF" is output for 0.1 second. As described above, by securing the period during which the signal is on and the period during which the signal is off, even if the winning detection and the prize ball detection are continuous within the signal on period, the signal corresponding to the detection is detected. Is reliably output.

Next, the operation of the gaming machine will be described. FIG.
5 is a flowchart showing the main processing executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56
First, necessary initial settings are performed (step S1).

Then, it is confirmed whether or not the data protection processing of the backup RAM area (for example, the power failure occurrence NMI processing such as the addition of parity data) has been performed when the power is turned off (step S2). In this embodiment, when an unexpected power failure occurs, a process for protecting data in the backup RAM area is performed. The case where such protection processing has been performed is regarded as backup. After confirming that there is no backup, the CPU 56 executes an initialization process (steps S2 and S3). In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off.
For example, if "55H" is set in the backup flag area, it means that there is a backup (on state),
If a value other than “55H” is set, it means that there is no backup (off state). “55H” set in the backup flag area is data set when the data protection processing of the backup RAM area is completed in the power failure occurrence NMI processing.
This is a parity code based on the data of the area.

If there is backup data in the backup RAM area, the CPU 56
A data check (for example, a parity check) of the M area is performed (step S4). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power-off, the initialization processing executed at the time of power-on, not at the time of restoration from power failure, is executed (steps S5 and S3).

If the check result is normal, the CPU 56
Performs a game state restoring process for returning the internal state to the state when the power is turned off (step S6). As shown in FIG.
When the value of the backup flag is set to “55H” and the check result is normal, the game state restoring process of step S6 is executed. Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the program returns to the address (step S7).

Execution of normal initialization processing (step S3)
Is completed, the process shifts to a loop process in which the monitoring of the timer interrupt flag (step S9) is confirmed in the main process. In the loop, a display random number update process (step S8) is also performed.

In this embodiment, step S2
The backup area is checked in step S4 after the backup data is checked in step S4 if the backup data exists. However, after the backup area check result is confirmed to be normal in step S4. ,
The presence or absence of backup data may be confirmed. Alternatively, whether to execute the power failure recovery process may be determined by confirming whether there is backup data or checking the backup area.

Also, for example, at the time of the parity check (step S4) when determining whether or not to execute the power failure recovery process, that is, when determining whether or not to restore the gaming state, the RAM data stored at the time of the parity check is determined. According to the special process flag, etc. and the data of the number of memorized start winnings in the game machine, the game machine is in the game standby state (the symbol is not fluctuating,
If it is confirmed that the game is not being changed reliably and that there is no start winning memory, the initialization process may be executed without performing the game state restoration process.

FIG. 17 is a flowchart showing the initial setting process in step S1. In the initial setting process, C
The PU 56 first sets interrupt prohibition (step S1).
a). When the interrupt is set to be prohibited, the CPU 56 sets the interrupt mode to the interrupt mode 2 (step S1b), and sets the stack pointer designated address to the stack pointer (step S1c). Then, the CPU 56 initializes the built-in device register (step S1d). In addition, CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits)
Is initialized (step S1e), and the RAM is set in an accessible state (step S1f).

CPU 5 used in this embodiment
6 has the following three types of modes as maskable interrupt (INT) modes. When an interrupt that can be masked occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

Interrupt mode 0: The built-in device that has issued the interrupt request receives an RST instruction (1 byte) or a CALL instruction (3 bytes).
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. Upon reset, CPU 56 automatically switches to interrupt mode 0
become. Therefore, when it is desired to set the mode to the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the mode to the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
In this mode, the camera always jumps to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is the interrupt address. Mode. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary (albeit skipped) even address. Each built-in device has a function of sending an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to set an interrupt process at an arbitrary position in a program. Will be possible. Further, unlike the interrupt mode 1, it is easy to prepare an interrupt process for each interrupt occurrence factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S1b of the initial setting process.

FIG. 18 shows a normal initialization process (step S).
It is a flowchart which shows the process of 3). As shown in FIG. 18, in the initialization processing, the RAM is cleared (step S3a). Then, based on the address value of the work area initial setting table, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a payout command storage pointer, etc.) is initialized. An initial value setting process for setting a value (step S3b) is performed. Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S3).
c). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited (see FIG. 17) in the initial setting process (step S1), the interrupt is permitted before the initialization process is completed (step S3d).

Therefore, in this embodiment, the CPU 56
Is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2 ms
Is set to Then, as shown in FIG. 19, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S12).

When the CPU 56 detects in step S9 that the timer interrupt flag has been set, it resets the timer interrupt flag (step S1).
0), a game control process is executed (step S11). According to the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process.
The game control process may be executed by a timer interrupt process.

As described above, in this embodiment, the interrupt mode 2 is set in the CPU 56 having the built-in CTC and PIO in the initial setting process. Accordingly, a periodic timer interrupt process using the built-in CTC can be easily realized. Further, the timer interrupt processing can be set at an arbitrary position on the program. Further, switch detection processing using the built-in PIO can be easily realized by interruption processing. As a result, effects such as simplification of the program configuration and reduction in the number of program development steps can be obtained.

Further, in this embodiment, it is determined whether or not the power supply is restored to the state at the time of power failure based on the presence or absence of backup data. Therefore, when the power is turned on, for example, when the power is restored after a power failure, it is possible to determine whether or not to restore the state at the time of the power failure according to the contents of the backup data storage area.

Further, since it is determined whether or not the power is restored to the power-off state according to the state of the backup data, the contents of the backup data storage area are restored when the power is turned on when the power is restored after a power failure. It is possible to determine whether to restore the power-off state according to the state.

FIG. 20 is a flowchart showing the game control processing in step S11. In the game control process,
The CPU 56 firstly receives the gate sensor 12, the starting port sensor 17, and the count sensor 23 through the switch circuit 58.
And the state of the winning opening switches 19a and 24a,
It is determined whether or not there is a prize for each winning port or prize device (switch processing: step S21).

Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and if necessary, an alarm is issued according to the result (error process: step S22).

Next, a process of updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S23). The CPU 56 further includes:
A process for updating a display random number such as a random number for determining the type of stop symbol is performed (step S24).

Further, the CPU 56 performs a special symbol process (step S25). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Also, a normal symbol process is performed (step S26). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

The CPU 56 sets a control command to be sent to the payout control board 37 or the like in a predetermined area of the RAM 55 and sends the control command (command control processing: step S27).

Next, the CPU 56 performs a data output process of outputting data such as jackpot information, start information, and probability variation information supplied to the hall management computer (step S29).

The CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in response to the drive command, and brings the variable winning ball device 15 or the open / close plate 20 into an open state or a closed state.

Further, the CPU 56 sets the number of prize balls based on the detection output of the switches 17, 23, 19a and 24a for detecting a winning in each winning opening (step S31). Specifically, a payout control command is output to the payout control board 37 in response to the winning detection. Dispensing control board 37
The payout control CPU 371 mounted on the CPU drives the prize ball payout device 97A according to the payout control command.

As described above, the main processing includes the processing for determining whether or not to shift to the game control processing.
Since a flag is set to determine whether or not to shift to the game control process in the timer interrupt process based on the timer interrupt that is periodically generated by the 56 internal timers, all the game control processes are reliably executed. Is done. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

Here, the CPU 56 of the main board 31
Is executed in response to a flag set in a timer interrupt process based on a timer interrupt that is periodically generated by an internal timer of the CPU 56, but the signal is periodically (for example, every 2 ms). A hardware circuit which generates the signal may be provided, a signal from the circuit may be introduced to an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control process based on the interrupt signal may be set. Good.

Even in such a configuration, the flag is not determined until all the game control processes have been executed, so that execution of all the processes in the game control process is guaranteed to be completed. You.

FIG. 21 shows a state in which the main board 31 controls the payout control board 3.
FIG. 9 is an explanatory diagram showing an example of a command form of a payout control command sent to the control unit 7; In this embodiment, the payout control command has a 2-byte configuration, and the first byte is MODE.
(Command classification), and the second byte indicates EXT (command type). The command form shown in FIG. 21 is an example, and another command form may be used.
The first bit (bit 7) of MODE data is always "1"
And the first bit (bit 7) of the EXT data is always "0".

FIG. 22 shows a relationship between an 8-bit control signal (in this case, a payout control signal) and an INT signal (in this case, a payout control signal INT) which constitute a control command for each electric component control means. It is a timing chart. FIG.
As shown in FIG. 2, when the period indicated by A elapses after the MODE or EXT data is output to the output port (port 1 in the case of the payout control signal), the CPU 56
Turns on an INT signal which is a signal indicating data output. When the period indicated by B has elapsed therefrom, the INT signal is turned off. Further, when there is data to be transmitted next, that is, after the MODE data is transmitted, the data of the second byte is transmitted to the output port after a period indicated by C. Regarding the data of the second byte, the periods of A and B are the same as the case of the first byte.

The period A is a period for the CPU 56 to prepare for sending a command, that is, a period required for processing for setting a send command in the buffer, and also to a control signal line (a payout control signal line in the case of a payout control signal). This is the period for data stabilization. The period of B is INT
This is a period for signal stabilization. And the period of C is
This is a period in which the electric component control means (the payout control means in the case of the payout control signal) is set so as to be able to reliably take in data. In the period C, the data on the signal line does not change. That is, the data output is maintained until the period C elapses.

In this embodiment, a payout control command to the payout control board 37, a display control command to the display control board 80, a lamp control command to the lamp control board 35, and a voice control command to the voice control board 70 are: It is sent using the same routine (common module). Therefore, the period of C, that is, the period from when the INT signal relating to the first byte is turned off to when the transmission of the second byte data is started, is the reception processing time in the electric component control means which takes the longest time for the command reception processing It is set to be longer than For example, when each of the CPUs in the payout control board 37, the display control board 80, the lamp control board 35, and the audio control board 70 is configured to receive a control command from the game control means by an interrupt having the highest priority. When the operation clock of the payout control CPU 371 in the payout control board 37 is the latest, the time is set to be longer than the reception processing time of the payout control CPU 371. Also, if the number of clocks required for processing is different even if the operation clocks of the CPUs are the same, the setting is made to be longer than the reception processing time of the CPU requiring the largest number of clocks.

Each electric component control means changes the state of the INT signal from the on state (high level) to the off state (low level).
Is detected, the process of capturing 1-byte data is started by, for example, an interrupt process.

Since the period C is longer than the reception processing time of the electric component control means which takes the longest time for the command reception processing, the game control means controls the command transmission processing for each electric component control means by the common module. Also, any of the electric component control means can reliably receive the control command from the game control means.

FIG. 23 is an explanatory diagram showing an example of the contents of the payout control command. In the example shown in FIG.
Command F of ODE = FF (H) and EXT = 00 (H)
F00 (H) is a payout control command for specifying a payable state. MODE = FF (H), EXT = 01
The command FF01 (H) of (H) is a payout control command for specifying a payout stop state. MODE = F0
The command F0XX (H) of (H) is a payout control command for specifying the number of winning balls. "XX" which is EXT indicates the number of payouts.

When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout control means stops the prize ball payout and the ball lending.
When the payout control command of (H) is received, it becomes possible to pay out prize balls and lend a ball. Further, when a payout control command specifying the number of winning balls is received, prize ball payout control according to the number specified by the received command is performed.

The payout control command is sent only once so that the payout control means can recognize it. Recognizable means that the INT signal is in the ON state in this example, and is transmitted only once so that it can be recognized. In this example, the INT signal is sent to the first and second bytes of the payout control signal. Accordingly, the INT signal is turned on only once.

FIG. 24 is a flowchart showing a portion related to the winning ball control of the switch process (step S21) in the game control process shown in FIG. In the switch processing, the CPU 56 sets the ball out switch 187a,
If a ball break for a winning ball is detected by 187b, a ball break state flag is set (steps S121 and S12).
2). When it is detected that the ball is not out of ball by the ball out switches 187a and 187b, the ball out state flag is reset (steps S121 and S123).

Next, when the lower plate full level is detected by the full level switch 48, a full level flag is set (steps S124 and S125). When it is detected that the lower plate is not full by the full tank switch 48, the full tank flag is reset (steps S124 and S126).

Further, when detecting that the count switch 23 is turned on, the 15 counter is incremented by 1 (steps S131 and S132), and the winning opening switches 19a and 24a are set.
Is detected, the ten counters are incremented by one (steps S133 and S134). When the start port switch 17 is detected to be on, the six counters are incremented by one (steps S135 and S136).

In this embodiment, 15 prize balls are paid out for a prize passing through the special winning opening, and 6 prize balls are paid out for a prize passed through the starting winning opening 14. It is assumed that ten prize balls are paid out for the prize through the prize ball device 24 and the prize ball device. The 15 counter is a counter for counting the number of winnings to the special winning opening, the 10 counter is a counter for counting the number of winnings to the normal winning opening, and the 6 counter is a winning for the starting winning opening. This is a counter for counting the number.

FIGS. 25 to 27 are flowcharts showing an example of the winning ball signal processing (step S31) in the game control processing shown in FIG. In this example, in the winning ball signal processing, the CPU 56 first checks whether or not the payout is stopped (step S201). The payout stop state is a state after a payout stop state designation command is sent to the payout control board 37. If it is not the payout stop state, it is checked whether the above-mentioned ball out-of-ball state flag or the full tank flag is turned on (step S20).
2).

When either of them changes to the ON state,
The command transmission table for the payout stop state designation is set (step S203). The command transmission table will be described later in detail. Step S202
In, when one of the flags is already in the ON state and the other flag is in the ON state, the command transmission table is not set (step S203).

If the payout is stopped, it is checked whether both the out-of-ball state flag and the full state flag have been turned off (step S204). When both are turned off, a command transmission table relating to the payout stop release designation is set (step S205).

Next, it is checked whether or not the timer T1 has timed out (step S211). The timer T1 is a timer for determining whether or not an unrecoverable error has occurred. If the accumulated number of errors exceeds a predetermined number at the time of timeout, an error that cannot be recovered is obtained. If the cumulative error count is equal to or less than the predetermined count, the operation is continued. Timer T
If 1 has not been set, or if a timeout has not occurred even if set, the process proceeds to step S221.

If the timer T1 has timed out, the value of the winning ball error counter is checked (step S212). If the value of the winning ball error counter has exceeded a predetermined value, an error state is entered (step S21).
7). In the error state, the CPU 56 is stopped.
For example, a loop state (jump to the same address) is set.

If the value of the winning ball error counter does not exceed a predetermined value when the timer T1 times out, the winning ball error counter is initialized (step S213), and the timer T1 is started again (step S214).

The value of the winning ball error counter is counted up when an error such as an excessive number of winning balls is detected. Therefore, if a prize ball excess error exceeding a predetermined number occurs within a predetermined time (within the count-up time of the timer T1), 2
Even if it is restarted by the ms interrupt, it will not be released. In this way, if the system is configured not to be in the halt state immediately when the excess prize ball error occurs but to be in the stop state when the prize ball excess error occurs frequently, an error that occurs temporarily and naturally recovers may occur. Then, the gaming machine does not become inoperable. In addition, when the prize ball excess error frequently occurs, an inspection or the like is often required. In such a case, the gaming machine can be made inoperable.

Next, the CPU 56 performs control to set a payout control command relating to the number of winning balls according to the winning in the command transmission table. First, the values of the 15 counters are checked (step S221). As mentioned above, 1
The five counters are counted up when the game ball wins the big winning opening and the count switch 23 is turned on. Fifteen
If the value of the number counter is not 0, a command transmission table relating to the fifteen winning ball number instructions is set (step S222). Further, the value of the 15 counters is decremented by one (step S223). Further, 15 is added to the payout command number cumulative value (step S224).

If the value of the 15 counter is 0, the value of the 10 counter is checked (step S225). As described above, the ten counters are counted up when a game ball wins a winning opening and the winning opening switches 19a and 24a are turned on. If the value of the ten counter is not 0, the command transmission table for the ten winning ball number instructions is set (step S226). Further, the value of the ten counters is decremented by one (step S227). Further, 10 is added to the cumulative number of payout commands (step S).
228).

If the value of the ten counter is 0, the value of the six counter is checked (step S231). As described above, the six counters are counted up when the game ball wins the starting winning port and the starting port switch 17 is turned on. If the value of the six counter is not 0, the command transmission table for the six winning ball number instructions is set (step S232). Also, the value of the six counters is-
1 (step S233). Further, 6 is added to the payout command number cumulative value (step S234).

As described above, when the payout control command is to be output from the game control means to the payout control board 37, the command transmission table is set. When the command transmission table is set,
The award ball paying flag is turned on (step S235). If the award ball paying flag is on, the process shifts to step S241 (step S236).

Next, the CPU 56 checks whether or not the error display flag is turned on (step S241).
If it is on, the process moves to step S257. In addition,
The error display flag will be described later. If the error display flag is not turned on, the prize ball count switch 3
Wait for 01A to turn on (step S242). When detecting that the prize ball count switch 301A is turned on, it waits for the prize ball count switch 301A to be turned off (step S24).
2) When turned off, the payout command cumulative number is decremented by one (step S244). Also, the award ball number signal output processing subroutine is started (step S245). And the timer T
2 is started (step S246).

The paid out prize balls pass through the prize ball count switch 301A one by one. As described above, by detecting ON and OFF of the prize ball count switch 301A, the passage of the game ball is reliably detected. Is done. And
When the passage of the game ball is detected, it is determined that there is one prize ball, and the payout command cumulative number is decremented by one.

If the cumulative value of the number of payout commands, which is added when the payout control command is transmitted and is decremented by one when the prize ball count switch 301A is turned on, does not become 0 when the timer T2 times out, the prize balls are excessive or the prize balls are insufficient. Is determined to have occurred. Therefore, the timer T2 is started or restarted every time the output of the prize ball count switch 301A is turned off after being turned on.

If the award ball count switch 301A is not turned on in step S242, it is checked whether or not the timer T2 is operating (step S247). Timer T2
Is operating, the CPU 56 checks whether or not the timer T2 has timed out (step S250). If the timeout has not occurred, the process ends.

The value of the timer T2 (the time from the start to the time-out) is a payout cycle (a period from when the prize ball count switch 301A is turned on to when it is turned on next time) when payout is normally performed. ) Is set longer. Therefore, when the payout is normally performed, the next winning ball count switch 301A is turned on (step S242) before the timer T2 times out, except for the last payout. That is, when the payout is normally performed, the timer T2 times out only after the last payout is performed.

In some cases, an interval time is provided between prize ball payouts in continuous payout (the prize ball payout for a certain prize and the prize ball payout for the next prize are successively performed). Is that the value of the timer T2 is set longer than the interval time. That is, when the continuous payout is performed, the time-out occurs only after the last payout is performed.

When the timer T2 times out in step S250, the CPU 56 checks whether or not the payout command number accumulated value is 0 (step S25).
1). When a corrected payout, which will be described later, is performed, it is checked whether or not the stored value of the corrected number is 0. The payout command number cumulative value is added by the number of prize balls when a prize is won, and the prize ball count switch 301 for detecting that there is a prize ball.
Since the value is decremented by 1 when A is turned on, the value is 0 when the payout is completed normally. Therefore, if the value is 0, the prize ball payout flag is turned off and the process ends (step S252).

If the payout command number accumulation value or the corrected number storage value is not 0 when the timer T2 times out, it means that the prize balls are excessive or the prize balls are insufficient. Therefore, when the payout command number accumulation value or the corrected number storage value is not 0, the CPU 56 checks whether the value is positive or negative (step S253). When the value is positive, that is, when it is determined that the payout is insufficient, the number to be corrected is set to the stored value of the corrected number (step S
255), a command transmission table relating to the number of corrections is set (step S256).

FIG. 28 is a flowchart showing an example of the error display processing. In the error display process, the CPU
56 first checks whether the timer T3 is operating (step S261). The timer T3 is a timer that is set when an error is detected, and displays an error until a timeout occurs. If timer T3 is not running,
The error display flag is turned on (step S262), and an error display request is set (step S263). Then, the timer T3 is started (step S264). Further, the value of the winning ball error counter is incremented by 1 (step S2).
65).

The value of the winning ball error counter is determined in step S2.
A check is made at step 12, and if the value exceeds a predetermined value within a predetermined time, a complete error state is set in which automatic recovery is not performed. In addition,
When the error display request is set, for example, control is performed so that an error is displayed on the variable display unit 9, or control is performed so that an error notification sound is generated from the speaker 27.

Then, if the game state is the normal state (step S266), a loop state is entered. The normal state is a state other than the big hit gaming state and the state where the variable display is performed on the variable display unit 9.

If the timer T3 is operating in step S261, the CPU 56 checks whether the timer T3 has timed out (step S27).
0). If a timeout has occurred, the error display request is reset (step S271), and the error display flag is turned off (step S272). Further, the award ball payout flag is turned off (step S273). Therefore,
The gaming machine returns to a state where the winning ball detection and the winning ball payout control can be performed again. When the error display flag is on, the game progress is interrupted.

In the error state of step S213 (the value of the winning ball error counter has exceeded a predetermined value within a predetermined period), for example, error display and error notification are performed, and control is performed so as to enter a loop state. .

FIG. 29 shows a prize ball count switch 301A.
Is a flowchart showing a prize ball number signal output processing subroutine (step S245) activated when it is confirmed that one game ball has been paid out (steps S242 to S243). .

In the prize ball number output processing subroutine, the CP
U56 increments the value of the winning ball number counter by +1 (step S281). If the value of the prize ball number counter is a multiple of 10 (step S282), the request for prize ball number output is turned on (step S283). Note that the prize ball number counter is simply incremented, and if the prize ball number counter is a 16-bit counter,
After the value becomes FFFF (H), it returns to 0.

FIG. 30 and FIG. 31 are flow charts showing processing relating to external output of each information of the data output processing in the game control processing shown in FIG. At first,
The timer used will be described.

Ta: a timer for determining the ON period of the award ball number signal (see FIG. 14C). Tb: a timer for determining the ON period of the symbol determination count signal (see FIG. 14A). Tc: Timer for determining ON timing of big hit information 1 and 2 signals (see FIG. 14A). Td: a timer that determines the off timing of the big hit information 1 and 2 signals (see FIG. 14A). Te: A timer for determining the ON period of the starting port information signal (FIG. 1
4 (B)).

In the data output process, the CPU 56 first checks whether or not the Ta timer is operating (whether or not the award ball number signal is on) (step S150). If it is operating, it is checked whether or not a timeout has occurred (step S15).
1). When the timeout occurs, the award ball number signal is turned off (high level) (step S152).

As shown in FIG. 13, the prize ball number signal is logically inverted in the information output circuit 64.
Actually, the ON state is output as “1” from the CPU 56. But for simplicity, here too,
The explanation will proceed assuming that the award ball number signal has negative logic. This is the same for other signals.

Next, the CPU 56 first checks whether or not the Tb timer is operating (whether or not the symbol determination count signal is on) (step S153). If it is operating, it is confirmed whether or not a timeout has occurred (step S154). When timeout occurs, turn off the symbol confirmation count signal (high level)
(Step S155). Further, it is confirmed whether or not the Tc timer is operating (step S156). If it is operating, it is checked whether or not a timeout has occurred (step S15).
7). After the timeout, the big hit information 1 signal and the big hit information 2 signal are turned on (low level) (steps S158 and S159).

Further, it is determined whether or not the Td timer is operating (step S161). If it is operating, it is checked whether or not a timeout has occurred (step S162). When the timeout occurs, the big hit information 1 signal is turned off (high level) (step S163). Here, when the big hit is due to the specific symbol causing the probability variation state (step S164), the probability variation information signal is turned on (low level) (step S543), otherwise,
The big hit information 2 signal is turned off (high level) (step S165). Then, it is confirmed whether or not the Te timer is operating (whether or not the start winning information signal is on) (step S).
166). If it is operating, it is confirmed whether or not a timeout has occurred (step S167). If a timeout occurs, the start port information signal is turned off (high level) (step S
168).

Next, if the prize ball number output request is on (step S171), the CPU 56 resets the prize ball number output request (step S172), and sets the prize ball number signal to the on (low level) state. (Step S
173). Further, a Ta timer is started (step S1).
74). The prize ball number output request is set every time the prize ball payout reaches 10 in the prize ball signal processing (step S283).

When the change of the special symbol in the variable display section 9 is stopped (step S175), the symbol determination number signal is turned on (step S176), and T
The b timer is started (step S177). Then, if the combination of the symbols at the time of stopping causes a big hit (step S178), the Tc timer is started (step S179). Further, when the big hit game state ends (step S180), the Td timer is started (step S181). In addition, the stop of the change of the special symbol, the fixed symbol at the time of the stop, and the end of the big hit game state are notified from the special symbol process process (step S25) in the game control process shown in FIG.

Then, when there is a winning start (step S182), the CPU 56 turns on the starting port information signal (low level) (step S183), and sets the start port information signal to Te.
The timer is started (step S184).

By the above-described processing, the symbol determination frequency signal, the big hit information 1 and 2 signals, the probability fluctuation information signal, the starting opening information signal and the prize ball number signal are output as shown in the timing chart of FIG. Is done. In this embodiment, the prize ball number signal is output directly from the main board 31 on which the game control means is mounted every time ten prize balls are paid out.

That is, when the prize ball is paid out, T
The award ball number signal is turned on for the time created by the a timer. The award ball number signal from the CPU 56 is input to the photocoupler 642 after being inverted by the amplifier circuit 64h in the information output circuit 64 shown in FIG. The light emitting diode in the photocoupler 642 conducts and emits light when “1” is output from the CPU 56. Then
The phototransistor in the photocoupler 642 is turned on. A resistor is connected to the phototransistor inside the photocoupler 642. Therefore, a potential difference appears between the input terminals of the diode bridge 643 connected to the photocoupler 642. Then, diode bridge 6
Each diode at 43 becomes conductive, and the potential between the output terminals of the diode bridge 643 becomes equal. That is, the output terminals are connected (short-circuit state).

When "0" is output from the CPU 56, the output terminals of the diode bridge 643 are open. In an external device such as a hall computer, when the two terminals are connected, it is determined that the award ball number signal is on. Therefore, FIG.
The prize ball number signal is output to the outside as shown in FIG.

In this embodiment, as shown in FIG. 13, in the information output circuit 64 of the main board 31,
The prize ball number signal was output in the form of connection of contacts by an amplifier circuit, a photocoupler, and a diode bridge. However, similarly to the signals to the information terminal board 34, the award ball number signal may be configured to be output in the form of a voltage level.

FIG. 32A is an explanatory diagram showing an example of the configuration of the above-described command transmission table. One command transmission table is composed of 3 bytes.
NT data is set. The command data 1 in the second byte includes the MOD in the first byte of the payout control command.
E data is set. The command data 2 of the third byte includes EXT of the second byte of the payout control command.
The data is set.

Although the EXT data itself may be set in the command data 2 area, the command data 2
May be set to data for specifying an address of a table in which EXT data is stored. In this embodiment, bit 7 of command data 2
If (work area reference bit) is 0, it indicates that the EXT data itself is set in the command data 2. Such EXT data is data in which bit 7 is 0. If the work area reference bit is 1, the other 7 bits indicate an offset for specifying an address of a table in which EXT data is stored.

In this embodiment, a plurality of command transmission tables are prepared, and the command transmission table to be used is specified by a pointer. Also, a plurality of command transmission tables are used as a ring buffer. Therefore, CP
U56 sets the INT data, the command data 1 and the command data 2 in the command transmission table pointed to by the write pointer in the winning ball signal processing. Then, the value of the write pointer is updated. Since one command transmission table has a 3-byte configuration, specifically, the write pointer value is +3.

In the process shown in FIG. 26, only one command transmission table setting process for one payout control command is performed in one process. However, since a plurality of command transmission tables are provided, a plurality of command transmission tables are provided. You may comprise so that a table setting process may be performed. For example, when a plurality of winnings are stored in the 15 counter, the 10 counter, and the 6 counter, a plurality of command transmission table setting processes may be performed by one winning ball signal processing.

Although the payout control command is described here, the display control command, the lamp control command, and the voice control command are also transmitted when the display control command, the lamp control command, and the voice control command are transmitted.
INT data, command data 1 and command data 2 are set in a command transmission table as shown in FIG. At that time, the INT data, the command data 1 and the command data 2 are set in the command transmission table pointed to by the write pointer.

FIG. 32B is an explanatory diagram showing an example of the configuration of INT data. Bit 0 in the INT data indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that a payout control command should be sent. Therefore, the CPU 56
In the winning ball signal processing, "01" is added to the INT data.
(H) ”is set.

The bits 1, 2, 3 of the INT data
Are bits indicating whether or not to transmit a display control command, a lamp control command, and a voice control command, respectively. When it is time to transmit those commands, the CPU 56 performs special symbol process processing or the like. The INT data, command data 1 and command data 2 are set in the command transmission table indicated by the pointer. When these commands are transmitted, the corresponding bit of the INT data is set to "1", and MODE data and EX data are added to command data 1 and command data 2.
T data is set.

FIG. 33 is a flowchart showing an example of the command control process (step S27) in the game control process shown in FIG. The command control process is a process including a command output process and an INT signal output process. In the command control process, the CPU 56 first
The address (contents of the read pointer) of the command transmission table is saved in a stack or the like (step S401). Then, the INT data of the command transmission table pointed to by the read pointer is loaded into the argument 1 (step S40).
2). Argument 1 is input information for a command transmission process described later. Further, the address indicating the command transmission table is incremented by 1 (step S403). Therefore, the address indicating the command transmission table matches the address of the command data 1.

Then, the CPU 56 sets the command data 1
Is read and set as argument 2 (step S404).
The argument 2 also becomes input information for a command transmission process described later. Then, a command transmission processing routine is called (step S405).

FIG. 34 is a flowchart showing a command transmission routine. In the command transmission routine,
First, the CPU 56 sets the data set in the argument 1, that is, the INT data, in the work area determined as the comparison value (step S421). Then
The number of transmissions = 4 is set in the work area determined as the number of processes (step S422). Then, port 1 for outputting the payout control signal (output port 571)
Is set to the IO address (step S4).
23).

Next, the CPU 56 shifts the comparison value one bit to the right (step S424). It is determined whether the carry bit has become 1 as a result of the shift processing (step S425). The fact that the carry bit has become 1 means that the rightmost bit in the INT data is “1”.
It means that it was. In this embodiment, four shift processes are performed. For example, when it is specified that a payout control command should be sent, the carry bit becomes 1 in the first shift process.

When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (ie, MODE data) is output to the address set as the IO address (step S4
26). When the first shift processing is performed, since the address of port 1 (output port 571) is set in the IO address, MODE data of the payout control command is output to port 1 after all.

Next, the CPU 56 sets the IO address to 1
While adding (step S427), the number of processes is decremented by 1 (step S428). If port 1 is indicated before the addition, the address of port 2 (output port 572) is set as the IO address by the addition processing for the IO address. Port 2 (output port 572)
Is a port for outputting a display control command.
Then, the CPU 56 checks the value of the number of processes (step S429), and if the value is not 0, the process proceeds to step S4.
Return to 24. In step S424, the shift process is performed again.

In the second shift processing, the value of bit 1 in the INT data is pushed out, and the carry flag becomes "1" or "0" according to the value of bit 1. Therefore,
A check is made as to whether it is specified that a display control command should be sent. Similarly, in the third and fourth shift processes, it is checked whether or not it is specified that the ramp control command and the voice control command should be transmitted. As described above, when each shift process is performed, the IO address corresponding to the command (payout control command, display control command, lamp control command, voice control command) set by the shift process is set in the IO address. Have been.
Therefore, when the carry flag becomes "1", a control command is sent to the corresponding output port (port 1 to port 4). That is, with one common module,
Transmission processing of a control command to each electric component control means can be performed.

As described above, since it is determined which control control unit should output the control command only by the shift processing, it is determined which control control unit should output the control command. Processing has been simplified.

Next, the CPU 56 reads the contents of the argument 1 storing the INT data before the start of the shift processing (step S430), and transfers the read data to the port 0.
(Output port 570) (step S43).
1). For the INT data, steps S421 to S429
Control commands (payout control commands,
The bit corresponding to the output bit of the INT signal according to the display control command, the lamp control command, and the voice control command is “1”. Therefore, port 1 to port 4
The INT signal corresponding to the control command (payout control command, display control command, lamp control command, voice control command) output to any of the above is turned on.

Next, the CPU 56 sets a predetermined value in the weight counter (step S432), and decrements by one until the value becomes 0 (steps S433 and S43).
4). This process is a process for setting the period B shown in FIG. When the value of the wait counter becomes 0, clear data (00) is set (step S43).
5), and outputs the data to port 0 (step S4)
36). Therefore, the INT signal is turned off. Then, a predetermined value is set in the weight counter (step S4).
32), and decrement by 1 until the value becomes 0 (steps S438 and S439). This process is a process for setting the period C shown in FIG.

Therefore, the value set in the wait counter in step S437 is such that the period of C is a period long enough for all the electric component control means to receive the control command to reliably execute the command receiving process. Value. The value set in the wait counter is such that the period of C is
This value is longer than the time required for the processing in steps S421 to S429.

As described above, the MODE data of the first byte of the control command is transmitted. Therefore, CPU5
No. 6 adds 1 to the value indicating the command transmission table in step S406 shown in FIG. Therefore, the area of the command data 2 in the third byte is specified. The CPU 56
The contents of the indicated command data 2 are loaded into the argument 2 (step S407). Also, it is checked whether the value of bit 7 (work area reference bit) of the command data 2 is “0” (step S409). If it is not 0, the start address of the command extension data address table is set in the pointer (step S409), and the address is calculated by adding the value of bit 6 to bit 0 of the command data 2 to the pointer (step S410). Then, the data of the area indicated by the address is loaded into the argument 2 (step S411).

In the command extension data address table, EXT data that can be transmitted to the electric component control means is sequentially set. Therefore, if the value of the work area reference bit is “1” by the above processing, the EXT data in the command extension data address table corresponding to the content of the command data 2 is loaded into the argument 2 and the work area reference bit is set. If the value is “0”, the content of the command data 2 is loaded as it is into the argument 2. Even when EXT data is read from the command extension data address table, bit 7 of that data is “0”.

Next, the CPU 56 calls a command transmission routine (step S412). Therefore, MOD
The EXT data is transmitted at the same timing as the transmission of the E data. Thereafter, the CPU 56 restores the address of the command transmission table (step S413), and updates the value of the read pointer pointing to the command transmission table (step S414). Since one command transmission table has a 3-byte configuration, specifically, the value of the read pointer is +3.

As described above, a 2-byte payout control command is sent to the payout control board 37. Note that the command control process shown in FIG. 33 is also used when transmitting other control commands (display control command, lamp control command, voice control command). When each electric component control means detects the falling of the INT signal, the control command fetch process is started. However, before any of the electric component control means completes the fetch process, a new signal from the game control means is received. Is not output to the signal line. That is, in each electric component control means,
Reliable command reception processing is performed. Note that each electric component control unit may start the process of capturing a control command at the rising edge of the INT signal. Also, the polarity of the INT signal may be reversed from that shown in FIG.

In this embodiment, a plurality of command transmission tables are used as a ring buffer.
In the command control process shown in FIG. 3, command output control is performed for the command transmission table pointed to by the read pointer, and in the process of setting data in the command transmission table, for example, in the prize sphere signal process shown in FIG. The command setting process is performed on the command transmission table indicated by the embedded pointer. Therefore, even if a plurality of command transmission requests occur at the same time, the command output process based on those requests is executed without any problem.

Next, the operation of the payout control means will be described. FIG. 35 is a block diagram illustrating a configuration example around the payout control CPU 371. As shown in FIG. 35, the voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) is sent to the payout control CPU 3 via the buffer circuit 960.
It is connected to a non-maskable interrupt terminal 71 (XNMI terminal). The first power supply monitoring circuit is a circuit that monitors the voltage of any one of various DC power supplies used by the gaming machine and detects a drop in the power supply voltage. In this embodiment,
The power supply voltage of VSL is monitored, and when the voltage value falls below a predetermined value, a low-level voltage drop signal is generated. VSL is the largest DC voltage used in gaming machines, and is +30 V in this example. Therefore, the payout control CPU 37
1 can confirm the occurrence of power interruption by interrupt processing.

Payout control C used in this embodiment
The PU 371 also has a PI like the CPU 56 of the main board 31.
O and CTC are built in. However, in this embodiment, no built-in PIO is used. In that case, for example, all ports are set to the input mode, and all ports are connected to the ground level.

Also, similarly to the CPU 56 of the main board 31,
The payout control CPU 371 can also be set to any of the interrupt modes 0 to 2, and the CTC can operate in a timer mode or a counter mode as described below.
Also, CTC has four channels. Specifically, four timer counter registers CLK / TRG0 to
3 (counters for channels 0 to 3). The operation mode can be set for each channel.

Each timer counter register CLK / TRG
The values of 0 to 3 are counted down according to the clock signal input to the corresponding CLK / TRG terminal, and when the count value becomes 0, an interrupt can be generated. Therefore,
Each of the channels 0 to 3 of the CTC can be an interrupt generation unit. The priority of the channel 0 is the highest, and then the priority sequentially decreases. That is, the count values of the plurality of timer counter registers CLK / TRG are simultaneously set to 0.
, The channel with the lower number has priority,
If those channels are set to generate an interrupt, an interrupt from a channel with a lower number is accepted first.

In this embodiment, channel 3 of the built-in CTC is used in the timer mode, and channel 2 is used in the counter mode. Channel 3 is used as a timer interrupt source, and channel 2 is used for receiving a payout control command.

Counter mode: payout control CPU 371
When the rising or falling edge of the clock signal is input to the CLK / TRG terminal, the count value is decremented by one. If interrupt generation permission is set for the channel, an interrupt is generated when the count value reaches 0,
Reload the initial value into the counter. If the interrupt vector has been set, the interrupt vector is sent out on the internal data bus when the count value becomes zero.

Timer mode: The count value is decremented by one based on a clock signal obtained by dividing the system clock (internal clock) by 1/16 or 1/256. If interrupt generation permission is set for that channel,
When the count value becomes 0, an interrupt is generated, and the initial value is reloaded into the counter. If the interrupt vector has been set, the interrupt vector is sent out on the internal data bus when the count value becomes zero.

CLK / TRG of payout control CPU 371
An INT signal (payout control signal INT) from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the payout control CPU 371
Timer / counter register CLK / TR built in
The value of G2 (CTC channel 2 counter) is down-counted. When the register value becomes 0, an interrupt occurs. Therefore, as shown in FIG. 32, if the initial value of the timer counter register CLK / TRG2 is set to “1”, the register value becomes 0 in response to the input of the INT signal and an interrupt occurs. Become.

[0212] The payout control board 37 is also provided with a system reset circuit 975.
The system reset circuit 975 also functions as a second power supply monitoring circuit (second power supply monitoring unit). That is, when the power is turned on, the reset IC 976 sets the output to a low level for a predetermined time determined by the capacity of an external capacitor, and sets the output to a high level after the predetermined time has elapsed. The reset IC 976 monitors the power supply voltage of VSL, which is the same as the power supply voltage monitored by the first power supply monitoring circuit mounted on the power supply board 910, and the voltage value becomes equal to or less than a predetermined value (for example, +9 V). Then, a low level voltage drop signal is generated. Therefore, when the power is turned off, the reset IC 976
When the voltage drop signal from the CPU goes low, the payout control CPU 371 is reset. As shown in FIG. 35, the voltage drop signal is the same output signal as the reset signal.

The predetermined value for the reset IC 976 to detect the power-off is lower than the normal voltage, but the payout control C
This is a voltage at which the PU 371 can operate for a while. Further, since the reset IC 976 is configured to monitor a voltage higher than the voltage (+5 V in this example) required by the payout control CPU 371, the payout control CPU 371
The monitoring range can be extended for the voltage required by the 371. Therefore, more precise monitoring can be performed.

While power is not being supplied from the + 5V power supply, at least a part of the internal RAM of the payout control CPU 371 is backed up by connecting a backup power supply supplied from the power supply board to the backup terminal, and the The contents are saved even if the power is turned off. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to the normal operation state. At that time, since the necessary data has been backed up,
Upon recovery from a power failure or the like, it is possible to return to the gaming state at the time of the power failure.

As described above, in this embodiment, the first power supply monitoring circuit mounted on the power supply board 910 monitors the highest voltage of the power supply VSL among the DC voltages used in the gaming machine. Then, when the voltage of the power supply falls below a predetermined value, a voltage drop signal (power-off detection signal) is generated. At the timing when the power-off detection signal is output, the IC drive voltage is
The voltage value is still enough to drive various circuit elements. Therefore, the payout control board 37 operated by the IC drive voltage
The operation time for the payout control CPU 371 to perform the predetermined power supply stop processing is secured.

Note that, also in this case, the first power supply monitoring circuit
Highest power supply VSL among DC voltages used in gaming machines
The power supply cutoff detection signal is generated at a timing such that the operation time for the electric component control means operating at the IC drive voltage to perform a predetermined power supply stop processing is secured. If it is timing, the monitoring target voltage need not be the highest voltage of the power supply VSL. That is, if at least the voltage higher than the IC drive voltage is monitored, the power-off detection signal can be generated at a timing such that the operation time for the electric component control means to perform the predetermined power supply stop processing is secured. it can.

In this case, as described above, the voltage to be monitored is +12 V supplied to various switches of the gaming machine such as the prize ball count switch 301A. Is also a voltage that can be expected. That is, it is preferable that the voltage drop can be detected before the + 12V power supply voltage, which is the voltage (switch voltage) supplied to the switch, starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

In the configuration shown in FIG. 35, when power is turned on, system reset circuit 975 outputs a low level for a period determined by the capacity of a capacitor, and then outputs a high level. That is, the reset release timing is only once. However, the main substrate 31 shown in FIG.
As in the case of the above, a circuit configuration that generates a plurality of reset release timings may be used.

FIG. 36 is a block diagram showing one configuration example of the information output circuit 377 mounted on the payout control board 37. In this example, the information output circuit 377 includes an amplifying circuit 377a that amplifies the ball lending number signal output from the payout control CPU 371 through the I / O port 372g, and a photocoupler 37 that is turned on by the output of the amplifying circuit 377a.
7b, and a diode bridge 377c for cutting off or short-circuiting between output terminals according to the output of the photocoupler 377b. The output of the diode bridge 377c is connected to the terminal board 160. The photocoupler 377b includes a light emitting diode and a phototransistor.
In b, a resistor is connected to one output of the phototransistor.

FIG. 37 is a timing chart showing an example of the output timing of the ball lending number signal externally output from the payout control board 37 via the terminal board 160. In this example, as shown in FIG. 37, every time a ball lending operation for 100 yen (for example, 25 game balls) is performed, the ball lending number signal is set to the low level for 0.1 second.

FIG. 38 is a flowchart showing the main processing of the payout control CPU 371. In the main processing,
The payout control CPU 371 first performs necessary initial settings (step S701).

FIG. 39 is a flowchart showing the initial setting process in step S701. In the initial setting process, the payout control CPU 371 first sets interrupt prohibition (step S701a). Next, the payout control CPU
The control unit 371 sets the interrupt mode to the interrupt mode 2 (step S701b), and sets a stack pointer designation address in the stack pointer (step S701c). Further, the payout control CPU 371 initializes the built-in device register (step S701d), and after initializing CTC and PIO (step S701e),
The RAM is set in an accessible state (step S70)
1f).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the internal device register setting process of step S701d and the process of step S701e, register setting for setting the channel to be used to the timer mode;
Register setting for permitting interrupt generation and register setting for setting an interrupt vector are performed. And
The interrupt by the channel is used as the timer interrupt described above. If a timer interrupt is to be generated every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set for the channel set in the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt processing. Specifically, the start address of the timer interrupt processing is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, the timer interrupt flag is set, and when it is detected in the main process that the timer interrupt flag is set, the payout control process is executed. That is, in the timer interrupt process, a setting for executing the payout control process, which is an example of the electrical component control process, is performed.

Another channel of the built-in CTC (channel 2 in this embodiment) is used as a channel for generating an interrupt for receiving a payout control command from the game control means. Is used in the counter mode. Therefore, in the internal device register setting process of step S701d and the process of step S701e, the register setting for setting the channel to be used to the counter mode, the register setting for permitting the occurrence of interrupt, and the interrupt vector are set. Is set.

The interrupt vector set for the channel (channel 2) set to the counter mode corresponds to the head address of the command reception interrupt process described later. Specifically, the start address of the command reception interrupt processing is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
At 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on the count-up of C can be used. Further, it is possible to set an interrupt processing start address according to the interrupt vector transmitted by the CTC.

The interrupt based on the count up of the channel 2 (CH2) of the CTC is an interrupt generated when the value of the timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S701e, the initial value “1” is set in the timer counter register CLK / TRG2 as the specific register. Also,
The interrupt based on the count up of the channel 3 (CH3) of the CTC is an interrupt generated when the register value becomes “0” after counting down the internal clock (system clock) of the CPU, and a 2 ms timer interrupt described later. Used as Specifically, the register value of CH3 is subtracted in 1/256 cycle of the system clock. In step S701e, a value corresponding to 2 ms is set as an initial value in the register of CH3. In this embodiment, the interrupt address for CH2 is 0074H, and the interrupt address for CH3 is 0076H.

As described above, the interrupt based on the count-up of CH2 of CTC has a higher priority than the interrupt based on the count-up of CH3. Therefore, when the count-up occurs at the same time, an interrupt based on the count-up of CH2, that is, an interrupt that triggers execution of a command reception interrupt process described later has priority.

Then, the payout control CPU 371 checks whether backup data exists in the backup RAM area for payout control (step S70).
2). That is, for example, similarly to the processing of the CPU 56 of the main board 31, it is determined whether or not backup data exists by determining whether or not a backup flag that is set when the power is turned off is in a set state. If the backup flag is set, it is determined that there is backup data. If it is determined that there is no backup data, it means that there was no unpaid game ball when the power was last turned off, and there is no need to return the internal state to the state when the power was turned off. Accordingly, the payout control CPU 371
An initialization process that is performed when the power is turned on, not when the power is restored, is executed (steps S702 and S703).

If the backup data exists in the backup RAM area, the payout control CPU 371
Performs a data check (parity check in this example) of the backup RAM area (step S704).
If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power failure, the initialization processing executed at the time of power-on without power recovery is executed (steps S705 and S70).
3).

If the check result is normal, the payout control CPU 371 performs a payout state restoring process for returning the internal state to the state at the time of power-off (step S706). Then, the process returns to the address indicated by the PC (program counter) stored in the backup RAM area (step S707).

Execution of normal initialization processing (step S70)
After 3), the main process executed by the payout control CPU 371 shifts to a loop process in which the timer interrupt flag is monitored (step S708).

Note that in this embodiment, step S7
02, the presence or absence of backup data is checked, and if backup data exists, the backup area is checked in step S704. Conversely, it is confirmed that the backup area check result is normal. The confirmation of the presence or absence of the backup data may be performed later. Further, it may be configured to determine whether or not to execute the power failure recovery process by confirming whether or not there is backup data or checking the backup area.

Also, for example, a parity check for determining whether or not to execute the power failure recovery processing (step S70)
In the case of 4) or the like, that is, when it is determined whether or not the gaming state is to be restored, the gaming machine is in the standby state for payout (not in the middle of payout) due to the number of payout game balls in the stored RAM data. If it is confirmed that there is, the initialization processing may be executed without performing the payout state restoration processing.

In the normal initialization process, as shown in FIG. 40, the register and RAM are cleared (step S9).
01) is performed, and a predetermined initial value is set (step S902). Then, the initial setting process (step S7)
01a), the interrupt is prohibited, so the interrupt is permitted before the initialization process is completed (step S90).
3).

In this embodiment, the payout control CPU 3
CH3 71 is set to repeatedly generate a timer interrupt. The repetition period is set to 2 ms. Then, as shown in FIG. 41, when a timer interrupt occurs, the payout control CPU 371 sets a timer interrupt flag (step S711). Although FIG. 41 clearly shows that the interrupt is permitted (step S
710) In the 2 ms timer interrupt processing, first, the interrupt permission state is set. That is, the interrupt is permitted during the 2 ms timer interrupt process.

The payout control CPU 371 proceeds to step S7.
If it is detected at 08 that the timer interrupt flag has been set, the timer interrupt flag is reset (step S709), and a payout control process is executed (step S710). According to the above control, in this embodiment, the payout control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt processing, and the payout control processing is executed in the main processing. However, the payout control processing may be executed in the timer interrupt processing.

At the time of power-on, the payout control CPU 371 can determine whether to perform the normal initial setting process or to restore the payout state only by checking the data in the backup RAM area. That is, with a simple judgment,
The payout process can be restarted for unpaid game balls. Further, in this embodiment, as in the case of the game control on the main board 31, the storage contents are reliably stored by the parity check code.

FIG. 42 is an explanatory diagram showing an example of use of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number storage (for example, 2 bytes) and a rental ball number storage are respectively formed.
The total number storage stores the total number of awarded ball payouts instructed from the main board 31 side. The rental ball number storage stores the number of unpaid ball rentals.

FIG. 43 is an explanatory diagram showing an example of the configuration of a receiving buffer for storing the payout control command received from the main board 31. In this example, a ring buffer type receiving buffer capable of storing six payout control commands having a 2-byte configuration is used. Therefore, the reception buffer is constituted by a 12-byte area of the fixed command buffers 1 to 12. Then, a command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11.

FIG. 44 is a flowchart showing a payout control command receiving process by the interrupt process. An INT signal for payout control from the main board 31 is supplied to a payout control CPU 371.
Are input to the CLK / TRG2 terminal. Therefore, when the INT signal from the main board 31 is turned on, the value of the timer counter register CLK / TRG2, which has been set to “1” as the initial value, becomes 0, and the payout control CPU 3
At 71, an interrupt occurs. Then, the payout control command receiving process shown in FIG. 44 is started. The start address of the payout control command receiving process is an address determined by the interrupt vector output from the built-in CTC and the value set in the I register. Also, the timer counter register CLK
When the value of / TRG2 becomes 0, that value is automatically returned to the initial value ("1" in this example).

In the payout control command receiving process, the payout control CPU 371 first saves each register in the stack (step S850). Note that when an interrupt occurs, the CPU 371 automatically sets the interrupt prohibition state. However, when a CPU that does not automatically enter the interrupt prohibition state is used, the interrupt prohibition is performed before the execution of the process of step S850. It is preferable to issue an instruction (DI instruction). Next, data is read from the input port 372a assigned to the input of the payout control command data (step S851). Then, it is confirmed whether or not this is the first byte of the payout control command having the 2-byte structure (step S).
852). Whether it is the first byte or not is confirmed by whether or not the first bit of the received command is “1”. The first bit should be “1” in the MODE byte (first byte) of the payout control command having a 2-byte configuration (see FIG. 21). Therefore, if the first bit is “1”, the payout control CPU 371 determines that the valid first byte has been received, and stores the received command in the confirmed command buffer indicated by the command reception number counter in the reception buffer area (step S85
3).

If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not the data has already been received is confirmed based on whether or not valid data is set in the reception buffer (fixed command buffer).

If the first byte has already been received,
It is checked whether the first bit of the received 1 byte is “0”. And if the first bit is “0”,
Assuming that the valid second byte has been received, the received command is stored in the fixed command buffer indicated by the command reception number counter +1 in the reception buffer area (step S855). The first bit should be “0” in the EXT byte (second byte) of the payout control command having the two-byte structure (see FIG. 21). If it is determined in step S854 that the first byte has already been received, the process ends if the first bit of the data received as the second byte is not “0”.

When the command data of the second byte is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is checked whether or not the command reception counter is 12 or more (step S857), and if it is 12, the command reception number counter is cleared (step S858). After that, the saved register is restored (step S859),
Interrupt permission is set (step S859).

During the command reception interruption processing, interruption is prohibited. As described above, the interrupt is permitted during the 2 ms timer interrupt process. Therefore, if a command reception interrupt occurs during the 2 ms timer interrupt, the command reception interrupt process is executed with priority. You. Further, even if a 2 ms timer interrupt occurs during the command reception interrupt process, the interrupt process is kept waiting. As described above, in this embodiment, the processing priority of the command reception processing from the main board 31 is high. Further, since no other interrupt processing is executed during the command reception processing, the maximum time required for the command reception processing is determined. It is difficult to estimate the longest time required for the command receiving process if the configuration is such that another interrupt process can be executed during the command receiving process. Since the maximum time required for the command receiving process is determined, a period C in the command sending process of the game control means (see FIG. 22).
Can be accurately determined.

The payout control command has a 2-byte structure, and includes a first byte (MODE) and a second byte (EX).
T) is configured to be immediately distinguishable on the receiving side.
In other words, the receiving side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. Therefore, as described above, it can be easily determined whether or not appropriate data has been received.

FIG. 45 is a flowchart showing the payout control processing in step S710. In the payout control processing, the payout control CPU 371 first determines whether or not the prize ball count switch 301A and the ball lending count switch 301B input to the input port 372b via the relay board 72 are turned on (switch processing: Step S7
51).

Next, the payout control CPU 371 controls the sensors (for example, the prize ball motor 289A and the ball lending motor 289B).
(Input position determination process: step S752). Dispensing control CP
The U371 further analyzes the received payout control command and executes a process according to the analysis result (command analysis execution process: step S753).

Next, the payout control CPU 371 sets the payout stop state if the payout stop instruction command is received from the main board 31, and releases the payout stop state if the payout start instruction command is received (step S754). ).
Further, a prepaid card unit control process is performed (step S755).

Next, the payout control CPU 371 performs control to pay out the lent ball in response to the ball lending request (step S756). Further, a drive signal is output to the ball lending motor 289B in the payout mechanism portion of the lending ball payout device 97C via the output port 372c and the relay board 72,
A ball lending motor control process for rotating the ball lending motor 289B by a predetermined number of revolutions is performed (step S757).

Further, the payout control CPU 371 performs a prize ball control process of paying out the prize balls of the number stored in the total number storage (step S758). And output port 3
Prize ball payout device 97A via the relay board 72c and the relay board 72
A drive signal is output to the prize ball motor 289A in the payout mechanism portion of the prize ball motor 289A, and the prize ball motor control processing for rotating the prize ball motor 289A by the number of revolutions set in the prize ball control processing in step S758 is performed (step S759) .

In this embodiment, the prize ball motor 2
A stepping motor is used as 89A and the ball rental motor 289B, and a 1-2 phase excitation method is used to control them. Therefore, specifically, in the ball lending motor control processing and the prize ball motor control processing, eight types of excitation pattern data are repeatedly output to the prize ball motor 289A and the ball lending motor 289B. In this embodiment, each excitation pattern data is output for 4 ms.

Next, error detection processing is performed, and a predetermined display is made on the error display LED 374 according to the result (error processing: step S760). For example, the following ten types of errors are detected.

Prize ball path error: When the prize ball payout operation is completed, or when the payout motor 289 makes one rotation, the prize ball count switch 301A does not detect any passing of the game ball. “0” is displayed on the error display LED 374.

Ball lending path error: When the ball lending payout operation is completed, or when the payout motor 289 has made one rotation, no ball lending count switch 301B has detected the passage of a game ball. “1” is displayed on the error display LED 374.

Prize ball count switch ball clogging error: when the prize ball count switch 301A detects ON for 0.5 seconds or more. “2” is displayed on the error display LED 374.

Ball lending count switch Ball clogging error:
When the ball lending count switch 301B detects ON for 0.5 seconds or more. “3” is displayed on the error display LED 374.

Prize ball motor ball biting error: Prize ball motor 28
When 9A does not rotate normally. Specifically, when the award ball motor position sensor has been on for a predetermined period or more, or has been off for a predetermined period or more. “4” is displayed on the error display LED 374. When a prize ball motor ball biting error occurs, the payout control CPU 371 sets the time to 50 ms.
After the reference excitation phase is output, four types of excitation pattern data of the excitation pattern data of the 1-2 phase excitation are
The reverse rotation and the forward rotation of the prize ball motor 289A by outputting every ms are repeated.

Prepaid card unit not connected error:
When the off of the VL signal is detected. Error display LED3
“5” is displayed at 74.

Prepaid card unit communication error: When it is detected that a signal is output from the prepaid card unit 50 at a timing other than the prescribed timing. Error display LE
“6” is displayed in D374.

Prize ball stop state: when a payout control command indicating stoppage of payout is received from the main board 31. Error display LE
“7” is displayed in D374. When a payout control command indicating the start of payout is received from the main board 31,
After 2002 ms from that point, the state returns from the payout stop state to the payable state.

Ball lending stopped state: Ball out switch 187
c, when 187d detects a broken ball. Error display LED
“8” is displayed at 374.

Ball lending motor ball biting error: When the ball lending motor 289B does not rotate normally. Specifically, when the ball lending motor position sensor has been on for more than a predetermined period, or has been off for more than a predetermined period. Error display LED 37
“9” is displayed in 4. When a ball lending motor ball biting error occurs, the payout control CPU 371 sets
After outputting the reference excitation phase of 0 ms, the ball rental motor 289 outputs four types of excitation pattern data of the excitation pattern data of the 1-2 phase excitation every 8 ms.
The reverse rotation and the forward rotation of B are repeated.

Further, the payout control CPU 371 performs processing for controlling an information signal output from an external connection terminal (not shown) (output processing: step S761). As shown in FIG. 37, the information signal is a signal that is turned on for a predetermined time for each unit of payout of a rental ball (for example, 100 yen: 25 pieces), and subsequently, is output for a predetermined time.

FIG. 46 is a flowchart showing an example of the command analysis execution processing in step S753. In the command analysis execution processing, the payout control CPU 371
It is checked whether there is a received command in the confirmed command buffer area (step S753a). If there is a received command, it is checked whether the received payout control command is a payout number instruction command (step S753).
b). When there are a plurality of received commands in the confirmed command buffer area, whether or not the received payout control command is the payout number instruction command is checked for the most recently received command.

If the received payout control command is the payout number instruction command, the number specified by the payout number instruction command is added to the total number storage (step S753).
c). That is, the payout control CPU 371 is connected to the main board 3
The number of prize balls included in the number-of-payouts instruction command sent from the first CPU 56 is stored in the backup RAM area (total number storage).

Note that the payout control CPU 371 performs, if necessary, decrement of the command reception number counter and reception command shift processing in the confirmed command buffer area.

FIG. 47 is a flowchart showing an example of the payout stop state setting processing in step S754. In the payout stop state setting process, the payout control CPU 371
It is checked whether there is a received command in the confirmed command buffer area (step S754a). If there is a received command in the confirmed command buffer area, it is checked whether or not the received payout control command is a payout stop instruction command (step S754b). If it is a payout stop instruction command, the payout control CPU 371 sets the winning ball payout stop state (step S754c).

If it is determined in step S754b that the received command is not a payout stop instruction command, it is checked whether the received payout control command is a payout start instruction command (step S754d). If it is the payout start instruction command, the award ball payout stop state is released (step S754e).

FIG. 48 is a flowchart showing an example of the switch processing in step S751. In the switch processing, the payout control CPU 371 checks whether or not the award ball count switch 301A indicates the ON state (step S751a). If it indicates the ON state, the payout control CPU 371 increments the winning ball count switch ON counter by one (step S751b). The prize ball count switch on counter includes the prize ball count switch 30.
This is a counter for counting the number of times the 1A ON state is detected.

Then, the value of the winning ball count switch on counter is checked, and if the value is 250 (step S751c), the winning ball clogging flag is set (step S751d). That is, when the ON state of the prize ball count switch 301A continues for a long time, the prize ball clogging flag is set.

When the value of the prize ball count switch on counter has reached 2 (step S751e), it is determined that the prize ball count switch 301A has been turned on without fail.
The award ball count switch on flag is set (step S751f).

If it is confirmed in step S751a that the prize ball count switch 301A is not on, the payout control CPU 371 resets the prize ball count switch on flag (step S751).
h), the award ball count switch on counter is cleared (step S751i). Then, it is determined whether or not the ball lending count switch 301B indicates the ON state (step S751j). If the ON state is indicated, the payout control CPU 371 increments the ball lending count switch ON counter by one (step S751k). The ball lending count switch on counter is a counter for counting the number of times that the ball lending count switch 301B has been turned on.

Then, the value of the ball lending count switch on counter is checked, and if the value is 250 (step S7511), a lending ball jam flag is set (step S751m). That is, when the ball lending count switch 301B has been on for a long period of time, the lending ball clogging flag is set.

When the value of the ball lending count switch-on counter has become 2 (step S751n),
It is determined that the ball lending count switch 301B has been turned on, and the ball lending count switch on flag is set (step S751o).

If it is determined in step S751j that the ball lending count switch 301B is not on, the payout control CPU 371 resets the ball lending count switch on flag (step S75).
1p) The ball lending count switch on counter is cleared (step S751q).

FIG. 49 is a flowchart showing an example of the prepaid card unit control processing in step S755. In the prepaid card unit control process, the payout control CPU 371 checks whether or not the VL signal input from the card unit control microcomputer has been detected (step S755a). If the VL signal has not been detected, the VL signal non-detection counter is incremented by 1 (step S755b). The payout control CPU 37
1 checks whether or not the value of the VL signal non-detection counter is 125 (step S755c). If the value of the VL signal non-detection counter is 125, the payout control CPU 371
Stops the emission control signal output to the emission control board 91 and stops the drive motor 94 (step S755)
d). Further, the VL-off detection flag is set (step S755e).

By the above processing, 125 times (2 ms ×
(125 = 250 ms) If the OFF of the VL signal is detected continuously, the state is set to the ball firing prohibited state.

If the VL signal has been detected in step S755a, the payout control CPU 371 resets the VL off detection flag (step S755).
f), the VL signal non-detection counter is cleared (step S755g). Then, the payout control CPU 371 stops outputting the firing control signal (step S755).
h), output of a firing control signal to the firing control board 91 is started, and the drive motor 94 is made operable (step S7).
55i).

FIG. 50 is a flowchart showing an example of the ball lending control process in step S756. In this embodiment, the maximum value of the number of consecutive payouts is one unit of the lending ball (for example, 25), but the maximum value of the number of consecutive payouts may be another number.

In the ball lending control process, the payout control CP
U371 confirms whether or not the ball lending is suspended (step S501). If stopped, switch 1
Check the states of 87c and 187d (step S50)
2). If both of them indicate that the ball is not out of ball, the ball out flag is reset (step S50).
3) The process proceeds to step S515.

If the ball lending is not stopped, the payout control CP
The U371 checks whether or not the loaned ball is being paid out (step S511). If the ball is being paid out, the process shifts to step S505. Whether or not the ball is being paid out is determined based on the state of a ball lending process flag described later. If the ball is not being paid out, the payout control C
The PU 371 confirms whether or not there has been a ball lending request from the card unit 50 (Step S512). If there is a request, the ball lending process flag is turned on (step S513), and 25 (the number of ball lending units: 100 in this case)
Is set as the number of lent balls in the backup RAM area (step S514). And the payout control CP
The U371 turns on the EXS signal (step S51).
5). Further, the ball lending motor 289B is turned on (step S516).

Strictly, the ball lending motor 289B is turned on after the BRQ signal is turned off to indicate that the card unit 50 has recognized the reception.
The ball lending processing flag is set in the backup RAM area.

[0286] In step S505, the out-of-ball switch 1
The states of 87c and 187d are confirmed, and if at least one of them indicates that the ball is out of ball, a ball out flag indicating that the ball lending is stopped is set (step S506), and the ball lending motor 289B is turned off (step S507). If both of the ball out switches 187c and 187d indicate that there is a ball, the process proceeds to the ball lending process from step S518.

At step S518, the payout control C
The PU 371 confirms whether or not it is during the rental ball passage waiting time (step S518). If it is not during the lending ball passage waiting time, a ball lending sensor (ball lending motor position sensor) is checked (step S519), and a ball lending count switch check process described later is performed (step S520).

In the ball lending sensor check processing in step S519, the ball lending motor position sensor is monitored for ON and OFF by a timer. CPU 371
Determines that a ball lending motor ball biting error has occurred.

Next, the payout control CPU 371 checks whether or not the driving of the ball rental motor 289B should be terminated (whether one unit of the payout operation has been completed) (step S52).
1). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. The rotation corresponding to the predetermined number of payouts is monitored by the output of the ball lending motor position sensor. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 sets the ball rental motor 289B
Is stopped (step S522), and a lending ball passing waiting time is set (step S523).

If it is during the waiting time for passing a ball at step S518, the payout control CPU 371 performs a ball lending count switch check process to be described later (step S524) and determines whether the waiting time for passing a ball for lending has ended. Confirmation is performed (step S525). The lending ball passing waiting time is the time from when the last payout ball is paid out by the ball lending motor 289B to when it passes through the ball lending count switch 301B.

When confirming the end of the waiting time for passing the rented ball,
Since all the lending balls have been paid out, the EXS signal is turned off to indicate to the card unit 50 that the next ball lending request can be accepted (step S526). The ball lending processing flag is turned off (step S527). If the last payout ball has not passed through the ball lending count switch 301B before the lending ball passage waiting time has elapsed, a ball lending path error is determined.

After the EXS signal indicating acceptance of the ball lending request is turned off and the BRQ signal, which is the ball lending request signal, is turned on again within a predetermined period, the ball lending process is performed without turning off the ball lending motor 289B. You may make it continue. That is, instead of performing the ball lending process for each predetermined unit (in this example, 100 yen unit), the ball lending process may be performed continuously.

The contents of the number-of-lended-balls storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the payout control CPU 371 can continue the ball lending process based on the contents of the lending ball number storage.

FIG. 51 shows steps S520 and S52.
9 is a flowchart showing a ball lending count switch check process executed in Step 4. The ball lending count switch check process is a process of monitoring the state of the ball lending count switch 301B and subtracting the lending ball number storage.

In the ball lending count switch check processing, the payout control CPU 371 first checks whether or not the ball lending count switch ON waiting flag is set (step S811). If the ball lending count switch ON waiting flag is set, the system waits until the ball lending count switch ON flag is turned on (step S812). The ball lending count switch-on flag is set in step S751o in the switch processing shown in FIG. If the timer T11 times out before the ball lending count switch on flag is turned on, the ball lending path error flag is set (steps S817 and S818). Ball rental count switch 3
When 01B is turned on, the timer T11 is stopped (step S813), and the ball lending count switch ON waiting flag is reset (step S814). Note that the timer T
Reference numeral 11 denotes a timer for checking whether or not the ball lending count switch 301B is turned on within a predetermined period.

When the ball lending count switch 301B is turned on, a ball lending count switch OFF waiting flag indicating that the ball lending count switch 301B is in a state of waiting to be turned off is set in order to confirm that the ball lending count switch 301B is turned off. Step S815).

Therefore, if the ball lending count switch OFF waiting flag is on (step S821), the payout control CPU 371 waits for the ball lending count switch on flag to be turned off (step S824). When the ball lending count switch on flag is turned off, the ball lending count switch OFF waiting flag is reset (step S825). Then, it is determined that one game ball has been paid out, and the temporary counting counter is incremented by 1 (step S826). Also, a ball lending information output processing subroutine for outputting a ball lending number signal is started (step S827). Next, the rental ball number memory is reduced by -1.
(Step S828).

In step S821, if it is confirmed that the ball lending count switch OFF wait flag is not on, the timer T11 is started (step S821).
822), a ball lending count switch ON waiting flag is set (step S823).

FIG. 52 is a flowchart showing the operation of a ball lending information output processing subroutine (step S827) started when the payout (lending) of one game ball is completed. In the ball lending information output subroutine, the payout control CPU 371 first checks whether the Tf timer is operating (whether the ball lending number signal is on) (step S781). If it is operating, it is checked whether or not a timeout has occurred (step S782). When the timeout occurs, the ball lending number signal is turned off (= 0) (step S783).

If the Tf timer is not operating, it is checked whether the value of the temporary counter is a multiple of N (25 in this example) (step S784). The value of the temporary counter is incremented by one when the payout of one game ball is completed.
N is the number of game balls lent for 100 yen. If the value of the temporary counter is a multiple of N, the ball lending number signal is turned on (= 1) (step S785), and the Tf timer is started (step S78).
6).

With the above processing, when lending a ball for 100 yen is performed, the ball lending number signal is turned on for the time created by the Tf timer. Dispensing control CPU 37
The ball lending number signal from 1 is inverted by the amplification circuit 377a in the information output circuit 377 shown in FIG. 36, and then input to the photocoupler 377b. Photo coupler 3
The light emitting diode at 77b is a payout control CPU3.
When “1” is output from 71, it conducts and emits light.
Then, the phototransistor in the photocoupler 377b is turned on. A resistor is connected to the phototransistor inside the photocoupler 377b. Therefore, a potential difference appears between the input terminals of the diode bridge 377c connected to the photocoupler 377b. Then, each diode in the diode bridge 377c becomes conductive, and the potential between the output terminals in the diode bridge 377c becomes equal. That is, the output terminals are connected (short-circuit state).

When "0" is output from the payout control CPU 371, the output terminals of the diode bridge 377c are open. An external device such as a hall computer determines that the ball lending number signal is ON when the two terminals are in a connected state. Therefore, the ball lending number signal is output to the outside as shown in FIG.

As described above, in this embodiment, the payout control means mounted on the payout control board 37 outputs the ball lending number signal to the external management device, and the game control means mounted on the main board 31 has A gaming machine capable of outputting a winning ball number signal to an external management device is realized.

FIGS. 53 and 54 show steps S758.
It is a flowchart which shows an example of the award ball control processing. In this example, the maximum value of the number of continuous payouts is the same as one unit of the lending ball (for example, 25), but the maximum value of the number of continuous payouts may be another number.

In the prize ball control processing, the payout control CPU
The step 371 checks whether or not the prize ball payout processing has already been started (step S532). If the prize ball is being paid out, the processing shifts to the processing during the prize ball shown in FIG. Whether or not a prize ball is being paid out is determined by a state of a prize ball processing flag described later.

If the prize ball is not being paid out, a payout control CPU
371 checks whether or not the number of prize balls (the number of unpaid prize balls) stored in the total number memory is not 0 (step S5).
34). If the number of prize balls stored in the total number storage is not 0, the prize ball control CPU 371 turns on the prize ball processing flag (step S535), and the value of the total number storage is 2
It is checked whether the number is 5 or more (step S536). The award ball processing flag is set in the backup RAM area.

The number of prize balls stored in the total number storage is 2
If the number is 5 or more, the payout control CPU 371 performs the 25 payout operation to output a drive signal to the prize ball motor 289A so as to rotate the prize ball motor 289A until 25 game balls are paid out. Make settings (step S53)
7). If the number of prize balls stored in the total number storage is not 25 or more, the payout control CPU 371 drives the prize ball motor 289A to rotate until all game balls stored in the total number storage are paid out. In order to output a signal, the setting of the total number payout operation is performed (step S53).
8). Next, the prize ball motor 289A is turned on (step S538). Then, the processing shifts to a processing during payout of the winning ball in the winning ball control processing shown in FIG.

FIG. 54 is a flowchart showing an example of processing during a prize ball in the payout control processing by the payout control CPU 371. In the processing during the prize ball, the payout control C
The PU 371 confirms whether or not the award ball passing waiting time is in progress (step S541). If it is not during the prize ball passage waiting time, the sensor for the prize ball (prize ball motor position sensor) is checked (step S542), and a prize ball count switch check process described later is performed (step S54).
3).

In the check processing of the prize ball sensor in step S542, the ON and OFF of the prize ball motor position sensor are monitored by a timer. The CPU 371 is
It is determined that a winning ball motor ball biting error has occurred.

Then, the payout control CPU 371 determines whether driving of the prize ball motor 289A should be terminated (25 or 2).
It is determined whether or not a predetermined number of payout operations of less than five have been completed (step S544). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed.
The rotation corresponding to the predetermined number of payouts is monitored by the output of the prize ball motor position sensor. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371
Stops driving the prize ball motor 289A (step S5).
45), and set the waiting time for passing the prize ball (step S5).
46). The prize ball passage waiting time is the time from when the last payout ball is paid out by the prize ball motor 289A to when it passes through the prize ball count switch 301A.

If it is determined in step S541 that the game is in the waiting time for passing a prize ball, the payout control CPU 371 performs a prize ball count switch check process described later (step S541).
547) It is checked whether or not the waiting time for award ball passage has ended (step S548). When the prize ball passage waiting time ends, all the prize balls set in step S537 or step S538 have been paid out. Therefore, the payout control CPU 371 turns off the award ball processing flag (step S549). If the last payout ball has not passed through the prize ball count switch 301A before the prize ball passage waiting time elapses, it is determined that a prize ball path error has occurred.

In this embodiment, the loaned ball payout device and the prize ball payout device are provided independently of each other, so that the prize ball payout process and the ball lending process can be executed simultaneously.
The ball lending process may be given priority over the prize ball process. That is, during the ball lending process, the start of the prize ball process may be made to wait. Further, the award ball processing may be prioritized over the ball lending processing.

FIG. 55 shows steps S543 and S54.
7 is a flowchart showing a prize ball count switch check process executed in Step 7. The prize ball count switch check process is a process of monitoring the state of the prize ball count switch 301A and subtracting the total number storage.

In the award ball count switch check processing, the payout control CPU 371 first checks whether or not the award ball count switch ON waiting flag is set (step S831). If the award ball count switch ON waiting flag is set, it waits until the award ball count switch ON flag is turned on (step S83).
2). Note that the prize ball count switch-on flag is
Step S751f in the switch processing shown in FIG.
Set by If the timer T12 times out before the winning ball count switch on flag is turned on, the winning ball path error flag is set (step S837,
S838). When the award ball count switch 301A is turned on, the timer T12 is stopped (step S833), and the award ball count switch ON waiting flag is reset (step S834). The timer T12 is a timer for confirming whether or not the award ball count switch 301A is turned on within a predetermined period.

When the prize ball count switch 301A is turned on, in order to confirm that the prize ball count switch 301A is turned off, a prize ball count switch OFF wait flag indicating a state of waiting for the switch to be turned off is set ( Step S835).

Therefore, if the prize ball count switch OFF waiting flag is on (step S841), the payout control CPU 371 waits for the prize ball count switch on flag to turn off (step S844). When the award ball count switch on flag is turned off, the award ball count switch OFF waiting flag is reset (step S8).
45). Then, the total number storage is decremented by one (step S).
848).

If it is confirmed in step S841 that the award ball count switch OFF wait flag is not on, the timer T12 is started (step S841).
842), the award ball count switch ON waiting flag is set (step S843).

[0318] The contents of the total number storage and the stored number of lent balls storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the payout control CP
U371 can continue the payout process based on the contents of the total number storage and the rental ball number storage.

The payout control CPU 371 manages the number of prize balls instructed from the main board 31 as a total number in the prize ball number storage.
). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the prize ball payout corresponding to the number counter is performed, the number counter is decremented by one (in this case, the subtraction processing is performed in the payout control processing).
Also in this case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the payout control CPU 371
Can continue the award ball payout process based on the content of each number counter.

Next, error processing will be described. FIG.
6 indicates an error type and an error display LED 374 (FIG. 1).
0 (see FIG. 0). FIGS. 57 and 58 are flowcharts showing an example of the error processing in step S760.

In this example, in the error processing, the payout control CPU 371 turns on the error display LED 37 when the winning ball path error flag is turned on (step S601).
4 is displayed as "0" (step S602). When the prize ball path error flag is turned off, the error display LE is displayed.
The display “0” of D374 is deleted (step S60).
3). The winning ball path error flag is set in step S838 shown in FIG. That is, it is set when the award ball count switch 301A is not turned on.

When the ball lending path error flag is turned on (step S604), "1" is displayed on the error display LED 374 (step S605). Also, when the ball lending path error flag is turned off, an error display LED
The display “1” of 374 is deleted (step S606).
The ball lending path error flag is set in step S818 shown in FIG. That is, it is set when the ball lending count switch 301B is not turned on.

If the prize ball clogging flag is turned on (step S607), “2” is displayed on the error display LED 374.
Is displayed (step S608). Further, when the award ball clogging flag is turned off, the display “2” of the error display LED 374 is erased (step S609). The prize ball jam flag is set in step S751d shown in FIG. That is, the prize ball count switch 301
Set when A did not turn off.

When the lending ball clogging flag is turned on (step S610), "3" is displayed on the error display LED 374 (step S611). Further, when the lending ball jam flag is turned off, an error display LED 37 is displayed.
The display “3” of 4 is deleted (step S612). The award ball clogging flag is determined in step S shown in FIG.
It is set at 751 m. That is, it is set when the ball lending count switch 301B has not been turned off.

[0325] If the award ball motor sensor output abnormality is detected (step S613), the error display LED 37
“4” is displayed in 4 (step S614). When the output abnormality of the prize ball motor sensor is released, the display “4” of the error display LED 374 is deleted (step S6).
15). The award ball motor sensor output abnormality is detected in step S542 shown in FIG. 54 when the award ball motor position sensor has been on for a predetermined period or more, or has been off for a predetermined period or more.

If the VL off detection flag is set (step S621), "5" is displayed on the error display LED 374 (step S622). When the VL off detection flag is reset, an error display L is displayed.
The display “5” of the ED 374 is deleted (step S62).
3). The VL off detection flag is set in step S755e shown in FIG.

When communication with the card unit 50 is performed at an irregular timing (step S6).
24) Assuming that a prepaid card unit communication error has occurred, "6" is displayed on the error display LED 374 (step S625). Further, when such an error is resolved, the display “6” of the error display LED 374 is deleted (step S626).

When the winning ball is stopped (step S627), "7" is displayed on the error display LED 374.
Is displayed (step S628). When the winning ball stop state is released, the display “7” of the error display LED 374 is erased (step S629). The winning ball stop state is a state where the winning ball payout stop state is set in step S754e in FIG. That is, when the payout stop is notified from the game control means. However,
Since the game control means notifies the payout stop even when the lower tray is full, it is preferable to check the state of the ball out switches 187a and 187b in step S627.

When the ball lending is stopped (step S630), “8” is displayed on the error display LED 374 (step S631). When the ball lending suspension state is released, the error display LED 374 displays “8”.
Is deleted (step S632). The ball lending stop state is a state after the ball out flag is set in step S503 in FIG.

[0330] If an error is detected in the ball lending motor sensor output (step S633), "9" is displayed on the error display LED 374 (step S63).
4). In addition, when the ball lending motor sensor output abnormality is released, the display “9” of the error display LED 374 is deleted (step S635). In addition, the ball lending motor sensor output abnormality is determined in step S519 shown in FIG.
It is detected when the off state has continued for a predetermined period or more.

As described above, in this embodiment, the error related to the prize ball and the error related to lending the ball are displayed on the error display LED 374 so that they can be identified.
Therefore, even if the rental ball payout device and the prize ball payout device are provided independently, it is possible to easily recognize the abnormality that has occurred in each of them.

FIG. 59 is a flowchart showing an example of the power failure occurrence NMI process executed in response to the NMI based on the voltage change signal from the power supply monitoring circuit of the power supply board 910. In this embodiment, the NMI interrupt address is 00
66H. In the power failure occurrence NMI process, the payout control CPU 371 first stores the contents of the interrupt prohibition flag in the parity flag (step S801). Then
The interrupt is prohibited (step S802). Power failure occurred N
In the MI process, in this example, as in the process executed on the main board 31, a process of generating a checksum for ensuring the storage of the RAM content is performed. If another interrupt process is performed during that process, the voltage may drop to a level at which the payout control CPU 371 cannot operate before the checksum generation process is completed. Are set so that other interrupts do not occur. In addition,
Steps S804 to S81 in the power failure occurrence NMI process
0 is an example of the power supply stop processing.

[0333] If a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the processing in step S802 is unnecessary.

Next, the payout control CPU 371 checks whether or not the backup flag has already been set (step S803). If the backup flag has already been set, no further processing is performed. If the backup flag is not set, the following power supply stop processing is executed. That is, the processing from step S804 to step S810 is executed.

First, the contents of each register are backed up by R
It is stored in the AM area (step S804). After that, a backup flag is set (step S805).
Then, an appropriate initial value is set in the backup check data area of the backup RAM area (step S80).
6) The exclusive OR is sequentially calculated for the initial value and the data in the backup RAM area and then inverted (step S807), and the final operation value is set in the backup parity data area (step S808). Also, RA
The M access is prohibited (step S809). When the power supply voltage decreases, the levels of various signal lines may become unstable and the contents of the RAM may be corrupted. However, if the RAM access is prohibited in this manner, the data in the backup RAM may be corrupted. There is no.

Further, the payout control CPU 371 has all output ports (in this embodiment, output ports 372
c, 372g, 372e, and I / O port 372f
Output port portion). Therefore, all output ports are turned off by the clear signal (step S810).

Next, the payout control CPU 371 enters a loop process. That is, no processing is performed. Therefore, before the operation is disabled from the outside by the system reset signal from the reset IC 976 shown in FIG. 35, the operation is internally stopped. Therefore, the operation of the payout control CPU 371 is reliably stopped when the power is turned off. As a result, due to the above-described RAM access prohibition control and the operation stop control, the value of R due to the abnormal operation that may occur as the power supply voltage decreases.
Destruction of the contents of the AM can be reliably prevented.

In this embodiment, the power failure occurrence NM
In I processing, the program was looped in the last part,
It may be configured to issue a HALT instruction.

The backup flag set after storing the contents of the register in the RAM area is, as described above, whether or not there is backup data to be restored at power-on (whether or not to recover from a power failure). Used to judge. Also, steps S801 to S810
Is completed before the payout control CPU 371 receives the system reset signal from the system reset circuit 975. In other words, to complete before receiving the system reset signal from the system reset circuit 975,
The detection voltage of the voltage monitoring circuit is set.

In this embodiment, the backup flag is checked at the start of the power supply stop processing. If the backup flag has already been set, the power supply stop processing is not executed. As mentioned above,
The backup flag is a flag indicating that the backup of necessary data has been completed and then the power supply stop processing has been completed. Therefore, for example, even if the NMI occurs again for some reason in the reset waiting loop state, the power supply stop processing will not be repeatedly executed.

However, in the case where a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the determination in step S803 is unnecessary.

Also, in this embodiment, the payout control C
PU 371 is a non-maskable external interrupt terminal (NMI terminal)
, The NMI interrupt signal from the power supply board (NMI interrupt signal from the power supply monitoring means) is detected, but the NMI interrupt signal may be introduced to a maskable interrupt interrupt terminal (INT terminal). In this case, the power failure occurrence NMI process shown in FIG. 59 is executed by the INT process. Further, an NMI interrupt signal may be detected through an input port. In that case, the input port is monitored in the main process executed by the payout control CPU 371.

FIG. 60 is an explanatory diagram for describing an example of a backup parity data creating method. However,
In the example shown in FIG. 60, the size of the data in the backup data RAM area is 3 bytes for simplicity. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 60, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, an exclusive OR of the result and “DFH” is obtained. Then, a value (“C6H” in this example) obtained by inverting the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, a parity diagnosis is performed in the power failure recovery processing. If all the data in the backup area is stored as it is, the data as shown in FIG. 60 is set in the backup area when the power is turned on again.

In the processing of step S704, the payout control CPU 371 performs the same processing as the processing executed in steps S806 and S807 in FIG. That is, initial data (00H in this example) is set in the backup check data area, and "00H"
And "F0H" are exclusive ORed, and the result is "1"
6H "is exclusive-ORed. Further, an exclusive OR of the result and “DFH” is obtained. Then, a final operation result obtained by inverting the result (“39H” in this example) is obtained. If all data in the backup area is stored as it is, the final calculation result matches “C6H”, that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final operation result does not become “C6H”.

Therefore, the payout control CPU 371 compares the final calculation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, the payout control means is provided with the storage means (backup RAM in this example) which is backed up for a predetermined period even if the power of the gaming machine is turned off. At the time of insertion, payout control CPU
371 (specifically, a program executed by the payout control CPU 371) is configured to perform a payout state restoration process (step S706) for restoring the payout state based on the backup data if the storage unit is in the backup state. .

[0348] Hereinafter, the payout state restoration processing will be described. FIG. 61 is a flowchart showing an example of the payout state restoring process shown in step S706 of FIG. In this example, the payout control CPU 371 sets the backup R
The value stored in the AM is restored to the register (step S861). Then, based on the data stored in the backup RAM, a process for recovering the payout state at the time of the power failure is performed. For example, a flag during processing of a prize ball is set.

For example, when the power is restored, the backup RA
If the number of unpaid prize balls or the number of unpaid lending balls or both of them are stored in the M area, the payout process is restarted based on the stored numbers.

When the payout state is restored, in this embodiment, the payout control CPU 371 returns to the backup R in order to restore the interrupt permission / prohibition state at the time of the previous power-off.
The value of the parity flag stored in the AM is checked (step S862). If the parity flag is clear, interrupt permission setting is performed (step S863). on the other hand,
If the parity flag is on, the process proceeds to step S
The payout state restoring process is terminated (with the interrupt prohibited state set in 701a).

Here, the payout state restoring processing program is configured to return to the payout control main processing when the payout state restoring processing is completed, but the stack pointer stored in the power supply stop processing points out. It is also possible to return to the address stored in the stack area (in the backup RAM area) (the address that was being executed when the NMI interrupt occurred when the power was turned off).

Although the ball lending number signal and the prize ball number signal are transmitted to an external device such as a hall computer via the terminal board 160, in the above embodiment,
The ball lending number signal is transmitted from the payout control board 37 to the terminal board 160, and the prize ball number signal is transmitted from the main board 31 to the terminal board 160. The wiring between the boards is generally connected to the board by a connector.
In particular, the terminal board 1
At 60, the connection between the ball lending number signal and the prize ball number signal may be interchanged.

In order to prevent such a connection error, the number of the ball lending number signal and the winning ball number signal may be reduced to one. In the following embodiment, the ball lending number signal and the prize ball number signal are transmitted from the payout control board 37 to the terminal board 1.
60 can be wired.

FIG. 62 is a block diagram showing a payout control board 37 for outputting a ball lending number signal and a prize ball number signal, and components related thereto. As shown in FIG.
In this embodiment, the information output circuit 377A of the payout control board 37 outputs a winning ball number signal to the terminal board 160.

FIG. 63 is a block diagram showing a configuration example of the information output circuit 377A. As shown in the figure, the information output circuit 377A includes, in addition to an amplifier circuit 377a for outputting a ball lending number signal, a photocoupler 377b and a diode bridge 377c, an amplifier circuit 377d for outputting a prize ball number signal, A photocoupler 377e and a diode bridge 377f are provided.

As described above, in the above embodiment, in a gaming machine in which a loaned ball payout device and a prize ball payout device are provided independently, the remaining prize balls (unpaid prize balls) and lending An area for storing the number of remaining balls (the number of unpaid lending balls) is backed up by a power source by a capacitor or the like. Therefore,
Even if a shortage of power or the like occurs, the stored contents are retained for a predetermined period. Then, when the power is restored, if the number of unpaid prize balls or the number of unpaid lending balls or both of them are stored in the backup RAM area, the payout process is restarted based on the stored numbers. Therefore, it is possible to prevent the player from being disadvantaged.

Although the power supply monitoring circuit is provided on the power supply board 910 in the above embodiment, the power supply monitoring circuit may be provided on the electric component control boards such as the main board 31 and the dispensing control board 37. . When an electric component control board on which a power supply circuit is mounted is configured, the power supply board includes
No power monitoring circuit is installed.

In particular, a card balance display signal indicating the balance of the prepaid card and a ball lending permission display signal pass from the card unit 50 as the lending request processing device through the payout control board 37, but not through the payout control CPU 371. The ball lending switch signal and the return switch signal transmitted from the balance display board 74 to the balance display board 74 as an operation board installed on the front side of the gaming machine also pass through the payout control board 37. Dispensing control CPU 371
Is transmitted to the card unit 50 without going through. Therefore,
The payout control board 37 can play the same role as a conventional relay board. That is, even if the relay board for signal transmission is not particularly provided, the same effect as the case where the relay board is provided can be obtained. Furthermore, the card unit 5
A signal line between 0 and the balance display board 74 can be collectively wired to the payout control board 37 together with a signal line for transmitting a signal for ball lending to the payout control CPU 371, thereby reducing wiring errors. You can also.

The pachinko gaming machine 1 of each of the above embodiments
Is a first-class pachinko gaming machine in which a predetermined game value can be given to a player when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a start winning prize is a predetermined symbol combination. However, if there is a prize in a predetermined area of the electric accessory that is opened based on a winning start, a second-type pachinko gaming machine that can give a predetermined game value to a player, or is variably displayed based on a starting prize. The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize for a predetermined electric accessory which is opened when a symbol combination of a predetermined symbol is released.

Further, the present invention is not limited to the pachinko gaming machine, but may be applied to a slot machine or the like in a case where an electric component performing some operation is provided.

[0361]

As described above, according to the present invention, a gaming machine is provided with an operation board on which an electric component for detecting an operation of a player borrowing a game medium is mounted. The transmission of the signal to and from the lending request processing device that receives the game medium lending request is configured to be performed via the payout control board, so that the relay board can be provided without a relay board for signal transmission. The same effect as in the case of providing the game machine can be obtained, and the cost of the gaming machine can be reduced and the wiring error can be reduced.

When the signal transmission between the operation board and the lending request processing device is configured to pass through the payout control board without passing through the payout control means, the signal is input to the payout control board. Also, signals not used by the payout control means are not input to the payout control means, so that the payout control means does not need to perform extra control, and there is no need to provide extra wiring on the payout control board.

When the operation board is installed inside the gaming machine on the front side of the gaming machine, the distance between the operation board and the lending request processing device becomes relatively large, so that the operation board is relayed to the payout control board. It becomes more effective to act as a substrate.

In the case where the payout control means is configured to store each unpaid number in the backup storage means,
Even if a power outage or the like occurs due to a power failure or the like in the gaming machine, there is an effect that the player is not disadvantaged with respect to awarding of prizes and lending of gaming media.

[0365] The payout control means can continuously perform a predetermined unit of game medium lending process a plurality of times based on a request from the lending request processing device, and the unpaid number of game media is related to a predetermined unit of lending. In the case where the remaining number is configured to be the remaining number, for example, in the configuration in which the power supply is backed up, when the remaining number for each predetermined unit is unpaid, the unpaid game medium is used when the power is restored from a power failure or the like. Can be reliably paid out, so that no unexpected disadvantage is given to the player.

[0366] The prize game medium supply state detecting means is provided at a position capable of detecting whether or not the number of game media that can be paid out by the prize game medium payout mechanism is a predetermined number equal to or more than one unit of the prize payout. The lending game medium supply state detecting means may be provided at a position where the lending mechanism can detect whether or not the required number of game media that can be dispensed is at least one unit of the game medium lending process. In this case, the payout process can be performed so that the supply of the game media to the prize game medium payout mechanism and the lending mechanism does not occur in the middle of the payout process of one unit. Does not change.

In the case where the predetermined number related to the prize game medium payout processing and the required number of payouts related to the game medium lending processing are configured to be different from each other, it is possible to appropriately monitor the outage of the game medium supply for each payout processing. There are effects such as being able to do.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an explanatory view showing each substrate provided on the back surface of the pachinko gaming machine.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a configuration diagram showing a configuration of a prize ball payout device and a ball passing path above the device.

FIG. 5 is an exploded perspective view of the prize ball payout device.

FIG. 6 is a configuration diagram showing a configuration of a rental ball dispensing device and a ball passage path above the device.

FIG. 7 is a configuration diagram showing another configuration example of a prize ball payout device and a rental ball payout device.

FIG. 8 is a configuration diagram showing still another configuration example of the prize ball payout device and the rental ball payout device.

FIG. 9 is a block diagram showing a circuit configuration of a game control board (main board).

FIG. 10 is a block diagram showing components related to a prize ball, such as components of a payout control board and a ball payout device.

FIG. 11 is a block diagram showing a configuration example around a CPU for power supply monitoring and power supply backup.

FIG. 12 is a block diagram illustrating a configuration example of a power supply board.

FIG. 13 is a block diagram illustrating a configuration of an information output circuit on a main board.

FIG. 14 is a timing chart showing an example of output timing of each signal externally output from the main board via the information terminal board or the terminal board.

FIG. 15 is a flowchart illustrating an example of a main process executed by a CPU on a main board.

FIG. 16 is an explanatory diagram showing an example of a method for determining whether or not to execute a game state restoration process.

FIG. 17 is a flowchart illustrating an example of an initial setting process.

FIG. 18 is a flowchart illustrating an example of an initialization process.

FIG. 19 is a flowchart illustrating an example of a 2 ms timer interrupt process.

FIG. 20 is a flowchart illustrating an example of a game control process.

FIG. 21 is an explanatory diagram showing a configuration example of a payout control command.

FIG. 22 is a timing chart showing a relationship between a control signal and an INT signal.

FIG. 23 is an explanatory diagram showing an example of the content of a payout control command.

FIG. 24 is a flowchart showing a switch process.

FIG. 25 is a flowchart showing winning ball signal processing.

FIG. 26 is a flowchart showing winning ball signal processing.

FIG. 27 is a flowchart showing winning ball signal processing.

FIG. 28 is a flowchart showing an error display process.

FIG. 29 is a flowchart showing a prize ball number signal output process.

FIG. 30 is a flowchart showing a data output process.

FIG. 31 is a flowchart showing a data output process.

FIG. 32 is an explanatory diagram showing a configuration of a command transmission table.

FIG. 33 is a flowchart showing a command control process.

FIG. 34 is a flowchart showing a command transmission process.

FIG. 35 is a block diagram illustrating a configuration example around a payout control CPU for power supply monitoring and power supply backup.

FIG. 36 is a block diagram illustrating a configuration of an information output circuit in the payout control board.

FIG. 37 is a timing chart showing an example of the output timing of a ball lending number signal externally output from the payout control board via the terminal board.

FIG. 38 is a flowchart illustrating an example of main processing executed by a payout control CPU.

FIG. 39 is a flowchart illustrating an example of an initial setting process of a payout control CPU.

FIG. 40 is a flowchart illustrating an example of initialization processing of a payout control CPU.

FIG. 41 is a flowchart illustrating an example of a timer interruption process of a payout control CPU.

FIG. 42 is an explanatory diagram showing a configuration example of a RAM in the payout control means.

FIG. 43 is an explanatory diagram illustrating a configuration example of a reception buffer.

FIG. 44 is a flowchart illustrating an example of a command receiving process of the payout control CPU.

FIG. 45 is a flowchart illustrating an example of a payout control process executed by a payout control CPU.

FIG. 46 is a flowchart illustrating an example of a command analysis execution process.

FIG. 47 is a flowchart illustrating an example of a payout stop state setting process.

FIG. 48 is a flowchart illustrating an example of a switch process.

FIG. 49 is a flowchart showing an example of a prepaid card unit control process.

FIG. 50 is a flowchart illustrating an example of a ball lending control process.

FIG. 51 is a flowchart illustrating an example of a ball lending count switch check process.

FIG. 52 is a flowchart showing a ball lending information output process.

FIG. 53 is a flowchart illustrating an example of a winning ball control process.

FIG. 54 is a flowchart illustrating an example of a winning ball control process.

FIG. 55 is a flowchart illustrating an example of a winning ball count switch check process.

FIG. 56 is an explanatory diagram showing the relationship between the type of error and the display of the error display LED.

FIG. 57 is a flowchart illustrating an example of error processing.

FIG. 58 is a flowchart illustrating an example of error processing.

FIG. 59 is a power outage occurrence NM executed by a payout control CPU.
It is a flowchart which shows the example of I processing.

FIG. 60 is an explanatory diagram for describing an example of a backup parity data creation method.

FIG. 61 is a flowchart illustrating an example of a payout state restoration process executed by a payout control CPU.

FIG. 62 is a block diagram showing a payout control board having another configuration and components related thereto.

FIG. 63 is a block diagram illustrating another configuration example of the information output circuit.

[Explanation of symbols]

1 Pachinko gaming machine 31 Main board 37 Payout control board 56 CPU 64 Information output circuit 74 Balance display board 97A Prize ball payout device 97B Lending ball payout device 160 Terminal board 187, 187a, 187b, 187c, 187d Ball out detection switch 289A Prize ball Motor 289B Ball lending motor 301A Prize ball count switch 301B Ball lending count switch 371 CPU for payout control 377 Information output circuit

Claims (7)

[Claims] 1. A game machine in which a player can play a predetermined game, wherein a game control board on which game control means for controlling the progress of the game is mounted, and a payout condition relating to the game is established. A prize game medium payout mechanism for paying out game media to a player, a lending mechanism for paying out game media to be lent to the player, and a payout of game media by controlling the prize game medium payout mechanism and the lending mechanism. A payout control board equipped with payout control means for performing processing relating to, and an operation board equipped with an electric component for detecting an operation by which a player borrows a game medium, wherein the operation board and the player A gaming machine wherein transmission of a signal to and from a lending request processing device that receives a gaming medium lending request is performed via the payout control board. 2. The gaming machine according to claim 1, wherein the signal transmission between the operation board and the lending request processing device passes through the payout control board without passing through the payout control means. 3. The gaming machine according to claim 2, wherein the operation board is provided inside the gaming machine on the front side of the gaming machine, and at least a detecting means for detecting an operation of the player is mounted. 4. A payout control means controls a prize game medium payout mechanism based on the number of game media notified from the game control means, performs a prize game medium payout process, and stores an unpaid number of prize game media. It is possible, and based on a request from the lending request processing device, controls the lending mechanism unit to perform a game medium lending process, and can store the unpaid number of the lending game medium, and the respective unpaid numbers are 4. The gaming machine according to claim 1, wherein the contents of the payout control means are stored in a backup storage means capable of storing the contents even when power supply to the payout control means is stopped. 5. The payout control means can continuously execute a predetermined unit of game medium lending process a plurality of times based on a request from the lending request processing device, and the unpaid number of game media is the predetermined number. The gaming machine according to any one of claims 1 to 4, wherein the remaining number is related to lending of a unit. 6. A prize game medium supply state detecting means for detecting a state of a game medium supplied to a prize game medium payout mechanism, and a lending for detecting a state of a game medium supplied to a lending mechanism. Game medium supply state detection means, wherein the prize game medium supply state detection means determines whether the number of game media that can be paid out by the prize game medium payout mechanism is a predetermined number equal to or more than one unit of prize game medium payout. The lending game medium supply state detecting means is provided at a position where it is possible to detect whether or not the required number of game media that can be paid out by the lending mechanism unit is at least one unit of the game medium lending process. The gaming machine according to any one of claims 1 to 5, wherein the gaming machine is provided at a position where the game machine can be detected. 7. The gaming machine according to claim 6, wherein the predetermined number is different from the required number.