JP2001250881A - Mounted substrate of power amplifier - Google Patents
Mounted substrate of power amplifierInfo
- Publication number
- JP2001250881A JP2001250881A JP2000061951A JP2000061951A JP2001250881A JP 2001250881 A JP2001250881 A JP 2001250881A JP 2000061951 A JP2000061951 A JP 2000061951A JP 2000061951 A JP2000061951 A JP 2000061951A JP 2001250881 A JP2001250881 A JP 2001250881A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- power amplifier
- gaas
- fet
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Amplifiers (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、携帯電話に使用さ
れる電力増幅器の実装基板構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting board structure for a power amplifier used in a portable telephone.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
以下のようなものがあった。2. Description of the Related Art Conventionally, techniques in such a field include:
There were the following.
【０００３】図３はかかる従来の電力増幅器の実装基板
組立模式図、図４は図３のＡ−Ａ線断面図、図５は図４
のＢ部の拡大図である。FIG. 3 is a schematic diagram of a conventional power amplifier mounting board assembly, FIG. 4 is a sectional view taken along line AA of FIG. 3, and FIG.
It is an enlarged view of the B section.
【０００４】電力増幅器に使用する電界効果トランジス
タ（以下ＧａＡｓ−ＦＥＴと記す）を実装する場合、Ｇ
ａＡｓ−ＦＥＴ１はガラスエポキシ基板４の放熱が悪い
ため直接半田付けできない。そのため、ヒートシンク２
の上にＡｕＳｎ共晶６を用いて接続し、ＧａＡｓ−ＦＥ
Ｔ１を接続させたヒートシンク２を基板４の下面に接続
された銅板７へ半田５で接続する。その後、ガラスエポ
キシ基板４に形成されるパッド８とＧａＡｓ−ＦＥＴ１
をＡｕワイヤ３を用いて接続するようにしている。When mounting a field effect transistor (hereinafter referred to as a GaAs-FET) used for a power amplifier,
The aAs-FET 1 cannot be directly soldered due to poor heat radiation of the glass epoxy substrate 4. Therefore, heat sink 2
Are connected using AuSn eutectic 6 and GaAs-FE
The heat sink 2 to which T1 is connected is connected to the copper plate 7 connected to the lower surface of the substrate 4 by solder 5. Then, the pad 8 formed on the glass epoxy substrate 4 and the GaAs-FET 1
Are connected using the Au wire 3.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記し
た従来のヒートシンク２を用いる電力増幅器の基板４へ
の電界効果トランジスタの実装方法では、組立時の工数
が増える上、ヒートシンク２の分の部材費がかかる。However, in the above-described method of mounting the field-effect transistor on the substrate 4 of the power amplifier using the heat sink 2, the number of steps required for assembling is increased and the cost of the heat sink 2 is reduced. Take it.
【０００６】本発明は、上記問題点を除去し、組立時の
工数及びコストの低減化を図ることができる電力増幅器
の実装基板を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a mounting board for a power amplifier, which can eliminate the above-mentioned problems and can reduce the number of steps and cost during assembly.
【０００７】[0007]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 〔１〕電力増幅器の実装基板において、凹部が形成され
る基板と、前記凹部に電界効果トランジスタを搭載可能
な面積で、かつ、前記基板厚分の凸部の形状の放熱構造
を有し、かつ、前記基板の下面に導出される導電板を具
備することを特徴とする。According to the present invention, in order to achieve the above object, [1] a mounting board for a power amplifier, in which a recess is formed, and an area in which a field effect transistor can be mounted in the recess. And a heat dissipation structure in the shape of a protrusion corresponding to the thickness of the substrate, and a conductive plate led out to the lower surface of the substrate.
【０００８】〔２〕上記〔１〕記載の電力増幅器の実装
基板において、前記電界効果トランジスタはＧａＡｓ−
ＦＥＴであることを特徴とする。[2] In the mounting substrate of the power amplifier according to [1], the field-effect transistor is a GaAs-type.
It is an FET.
【０００９】〔３〕上記〔１〕記載の電力増幅器の実装
基板において、前記導電板は銅板であり、前記基板はガ
ラスエポキシ基板であることを特徴とする。[3] The mounting board for a power amplifier according to [1], wherein the conductive plate is a copper plate, and the substrate is a glass epoxy substrate.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態につい
て図を参照しながら詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１１】図１は本発明の第１実施例を示すＧａＡｓ
−ＦＥＴの実装断面図である。FIG. 1 shows GaAs according to a first embodiment of the present invention.
FIG. 6 is a mounting cross-sectional view of the FET.
【００１２】この図に示すように、銅板１７にＧａＡｓ
−ＦＥＴ１１が搭載できうる面積で、ガラスエポキシ基
板１４と同じ高さの凸部（肉厚部）１７Ａの形状の放熱
構造を持たせる。銅板１７の凸部１７ＡにＧａＡｓ−Ｆ
ＥＴ１１を半田１５により接続する。接続に従来のよう
にＡｕＳｎ共晶を用いないのは、ＡｕＳｎの融点がガラ
スエポキシ基板１４の耐熱温度よりも高いためである。
その後、ガラスエポキシ基板１４上に形成されるパッド
１８とＧａＡｓ−ＦＥＴ１１をＡｕワイヤ１３により接
続する。As shown in FIG. 1, GaAs is formed on the copper plate 17.
-Provide a heat radiating structure in the shape of a convex portion (thick portion) 17A having an area where the FET 11 can be mounted and having the same height as the glass epoxy substrate 14. GaAs-F is formed on the projection 17A of the copper plate 17.
The ET 11 is connected by the solder 15. The reason why AuSn eutectic is not used for connection as in the prior art is that the melting point of AuSn is higher than the heat resistant temperature of the glass epoxy substrate 14.
After that, the pad 18 formed on the glass epoxy substrate 14 and the GaAs-FET 11 are connected by the Au wire 13.
【００１３】このように、第１実施例によれば、銅板１
７の凸部１７Ａに直接ＧａＡｓ−ＦＥＴ１１を半田１５
により接続することができるため、電力増幅器の組立時
における工数削減とコスト低減の効果が得られる。As described above, according to the first embodiment, the copper plate 1
7 is directly soldered to the GaAs-FET 11 on the projection 17A.
Therefore, it is possible to obtain the effect of reducing the number of steps and the cost at the time of assembling the power amplifier.
【００１４】次に、本発明の第２実施例について説明す
る。Next, a second embodiment of the present invention will be described.
【００１５】図２は本発明の第２実施例を示すＧａＡｓ
−ＦＥＴの実装断面図である。なお、第１実施例と同じ
部分については、同じ符号を付してそれらの説明は省略
する。FIG. 2 shows GaAs according to a second embodiment of the present invention.
FIG. 6 is a mounting cross-sectional view of the FET. Note that the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
【００１６】この図に示すように、銅板２１にプレス機
を用いてＧａＡｓ−ＦＥＴ１１が搭載できうる面積で、
ガラスエポキシ基板１４と同じ高さの凸部（打ち出し
部）２１Ａを有する形状にする。プレス機によってでき
たガラスエポキシ基板１４の凹部には、ＧａＡｓ−ＦＥ
Ｔ１１の放熱をよくするため、熱伝導性の樹脂２３を流
し込み、空洞をなくす。銅板２１の凸部２１ＡにＧａＡ
ｓ−ＦＥＴ１１を半田１５により接続する。As shown in FIG. 1, an area where the GaAs-FET 11 can be mounted on the copper plate 21 by using a press machine is provided.
A shape having a projection (embossed portion) 21A having the same height as the glass epoxy substrate 14 is formed. GaAs-FE is formed in the concave portion of the glass epoxy substrate 14 formed by the press machine.
In order to improve the heat radiation of T11, a thermally conductive resin 23 is poured to eliminate cavities. GaAs is formed on the projection 21A of the copper plate 21.
The s-FET 11 is connected by the solder 15.
【００１７】第１実施例で述べたように、銅板２１とＧ
ａＡｓ−ＦＥＴ１１の接続にＡｕＳｎ共晶を用いないの
は、ＡｕＳｎの融点がガラスエポキシ基板１４の耐熱温
度よりも高いためである。その後、ガラスエポキシ基板
１４上に形成されるパッド１８とＧａＡｓ−ＦＥＴ１１
をＡｕワイヤ１３により接続する。 このように、第２
実施例によれば、銅板２１の凸部２１Ａに直接ＧａＡｓ
−ＦＥＴ１１を半田１５により接続することができるた
め、電力増幅器の組立時における工数削減とコスト低減
の効果が得られる。As described in the first embodiment, the copper plate 21 and G
The reason why the AuSn eutectic is not used for the connection of the aAs-FET 11 is that the melting point of AuSn is higher than the heat resistant temperature of the glass epoxy substrate 14. After that, the pad 18 formed on the glass epoxy substrate 14 and the GaAs-FET 11
Are connected by an Au wire 13. Thus, the second
According to the embodiment, GaAs is directly formed on the protrusion 21A of the copper plate 21.
-Since the FET 11 can be connected by the solder 15, the effects of reducing man-hours and cost during assembly of the power amplifier can be obtained.
【００１８】なお、第２実施例では、銅板の凸部の裏側
に熱伝導性の樹脂を流しこんだが、樹脂に限らず、熱伝
導性がよければ半田などの金属を用いることも可能であ
る。In the second embodiment, a thermally conductive resin is poured on the back side of the convex portion of the copper plate. However, the present invention is not limited to the resin, and a metal such as solder can be used if the thermal conductivity is good. .
【００１９】また、上記実施例に示したＧａＡｓ−ＦＥ
Ｔに代えて、他のトランジスタを用いるようにしてもよ
い。Further, the GaAs-FE shown in the above embodiment is used.
Instead of T, another transistor may be used.
【００２０】更に、上記実施例に示した銅板に代えて他
の導電板を用いるようにしてもよい。Further, another conductive plate may be used in place of the copper plate shown in the above embodiment.
【００２１】また、上記実施例に示したガラスエポキシ
基板に代えて、他の絶縁基板を用いるようにしてもよ
い。Further, instead of the glass epoxy substrate shown in the above embodiment, another insulating substrate may be used.
【００２２】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
【００２３】[0023]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。As described above, according to the present invention, the following effects can be obtained.
【００２４】（Ａ）組立時の工数及びコストの低減化を
図ることができる電力増幅器の実装基板を得る。(A) A power amplifier mounting board capable of reducing the man-hour and cost for assembling is obtained.
【００２５】（Ｂ）特に、銅板の凸部に直接ＧａＡｓ−
ＦＥＴを半田により接続することができるため、電力増
幅器の組立時における工数削減とコスト低減化を図るこ
とができる。(B) In particular, GaAs-
Since the FETs can be connected by solder, it is possible to reduce man-hours and cost during assembly of the power amplifier.
【図１】本発明の第１実施例を示すＧａＡｓ−ＦＥＴの
実装断面図である。FIG. 1 is a mounting sectional view of a GaAs-FET showing a first embodiment of the present invention.
【図２】本発明の第２実施例を示すＧａＡｓ−ＦＥＴの
実装断面図である。FIG. 2 is a mounting sectional view of a GaAs-FET showing a second embodiment of the present invention.
【図３】従来の電力増幅器の実装基板組立模式図であ
る。FIG. 3 is a schematic view of a mounting board assembly of a conventional power amplifier.
【図４】図３のＡ−Ａ線断面図である。FIG. 4 is a sectional view taken along line AA of FIG. 3;
【図５】図４のＢ部の拡大図である。FIG. 5 is an enlarged view of a portion B in FIG. 4;
１１ ＧａＡｓ−ＦＥＴ １３ Ａｕワイヤ １４ ガラスエポキシ基板 １５ 半田 １７，２１ 銅板 １７Ａ 凸部（肉厚部） １８ パッド ２１Ａ 凸部（打ち出し部） DESCRIPTION OF SYMBOLS 11 GaAs-FET 13 Au wire 14 Glass epoxy board 15 Solder 17,21 Copper plate 17A Convex part (thick part) 18 Pad 21A Convex part (embossed part)
フロントページの続き (72)発明者 明神 哲也 東京都港区虎ノ門１丁目７番12号 沖電気 工業株式会社内 Ｆターム(参考） 5F036 AA01 BB08 BC06 BD01 5J091 AA01 AA41 CA87 FA16 HA24 KA65 KA66 QA04 5J092 AA01 AA41 CA87 FA16 HA24 KA65 KA66 QA04 Continuation of the front page (72) Inventor Tetsuya Myojin 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. F term (reference) 5F036 AA01 BB08 BC06 BD01 5J091 AA01 AA41 CA87 FA16 HA24 KA65 KA66 QA04 5J092 AA01 AA41 CA87 FA16 HA24 KA65 KA66 QA04
Claims (3)
凹部が形成される基板と、（ｂ）前記凹部に電界効果ト
ランジスタを搭載可能な面積で、かつ前記基板厚分の凸
部の形状の放熱構造を有し、かつ、前記基板の下面に導
出される導電板を具備することを特徴とする電力増幅器
の実装基板。1. A mounting board for a power amplifier, comprising:
A substrate on which a concave portion is formed, and (b) a heat dissipation structure having an area capable of mounting a field-effect transistor in the concave portion and having a shape of a convex portion corresponding to the thickness of the substrate, and being led out to the lower surface of the substrate. A mounting board for a power amplifier, comprising:
おいて、前記電界効果トランジスタはＧａＡｓ−ＦＥＴ
であることを特徴とする電力増幅器の実装基板。2. The mounting substrate for a power amplifier according to claim 1, wherein said field-effect transistor is a GaAs-FET.
A mounting board for a power amplifier, characterized in that:
おいて、前記導電板は銅板であり、前記基板はガラスエ
ポキシ基板であることを特徴とする電力増幅器の実装基
板。3. The mounting board for a power amplifier according to claim 1, wherein said conductive plate is a copper plate, and said substrate is a glass epoxy substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000061951A JP2001250881A (en) | 2000-03-07 | 2000-03-07 | Mounted substrate of power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000061951A JP2001250881A (en) | 2000-03-07 | 2000-03-07 | Mounted substrate of power amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001250881A true JP2001250881A (en) | 2001-09-14 |
Family
ID=18582022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000061951A Withdrawn JP2001250881A (en) | 2000-03-07 | 2000-03-07 | Mounted substrate of power amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001250881A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009037995A1 (en) | 2007-09-21 | 2009-03-26 | Nec Corporation | High output power amplifier, wireless transmitter, wireless transmitting and receiving device, and high output power amplifier mounting method |
| JP2021019149A (en) * | 2019-07-23 | 2021-02-15 | 三菱電機株式会社 | Semiconductor device |
| US11557554B2 (en) | 2018-07-12 | 2023-01-17 | Mitsubishi Electric Corporation | Semiconductor device |
-
2000
- 2000-03-07 JP JP2000061951A patent/JP2001250881A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009037995A1 (en) | 2007-09-21 | 2009-03-26 | Nec Corporation | High output power amplifier, wireless transmitter, wireless transmitting and receiving device, and high output power amplifier mounting method |
| US11557554B2 (en) | 2018-07-12 | 2023-01-17 | Mitsubishi Electric Corporation | Semiconductor device |
| JP2021019149A (en) * | 2019-07-23 | 2021-02-15 | 三菱電機株式会社 | Semiconductor device |
| JP7262334B2 (en) | 2019-07-23 | 2023-04-21 | 三菱電機株式会社 | semiconductor equipment |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20060728 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20060728 |
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| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20070605 |