JP2001246055A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which can continue a game in such a manner that the game may not become disadvantageous to a game player even when the feeding of a power source to the board is shut off, and can return to the initial state when a game is newly performed so that the game may not become unfair to the game player. SOLUTION: From a power source for backing up of a power source board 42, a power source for backing up is fed to the RAMs 41c, 43c, 44c, 45c and 46c of a main board 41, a sound board 43 which is a subsidiary board, a pattern display board 44, a discharge control board 45, and a decoration board 46. At the same time, when a delete switch 42s is depressed, the memory contents of the RAMs 41c, 43c, 44c, 45c and 46c can be deleted by a software-based means with CPUs 41a, 43a, 44a, 45a and 46a of respective boards. Thus, the game can be continued by the backed up memory contents at the time of an undesirable shutoff of the power source. Also, when a new game is performed, the memory contents can easily be deleted, and the game can be started from the initial state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine, and more particularly, to backing up a volatile memory arranged on a main board or a main board and a sub-board for controlling the gaming machine, and an erase switch. By manipulating the means,
The present invention relates to a gaming machine provided with erasure control means for controlling the contents of a backed-up volatile memory to be erased by software.

[0002]

2. Description of the Related Art Conventionally, in a gaming machine such as a pachinko machine, for example, a main board for controlling the gaming machine is provided, and the main board is used to control a symbol display device of the gaming machine, control a lighting mode of an electric decoration, Control of sound generation and control of payout of game balls were performed. However, in recent years, the control of the gaming machine has become complicated, and if only the main board is used, the burden on the main board is increased. In addition to the main board that controls the gaming machine, a symbol display device is provided to assist in controlling the main board. A sub-board consisting of a symbol display board for controlling the game, a payout control board for controlling the payout of the game balls, an illumination board for controlling the light emission mode of the illumination of the gaming machine, a sound board for controlling the sound generation of the gaming machine, and the like. There was a gaming machine provided independently of the main board. In a gaming machine provided with such a sub-board, a gaming machine capable of performing complicated control without imposing an excessive load on the main board could be obtained.
In such a conventional gaming machine in which such a main board and other sub-boards are separately provided, when power supply to some or all of the boards is undesirably cut off for some reason, the power supply is turned off. If there is already a jackpot before the supply is cut off or a prize ball has been paid out, the jackpot state will be released when the power is turned on again or the prize ball will not be paid out, so it is disadvantageous for the player In some cases, inconveniences such as a state may occur. Therefore, it is conceivable to provide backup means for memories of the main board and the sub-board so that the stored contents of the control means can be preserved even when the supply of the power supply current to the board is cut off.

[0003]

However, if a backup means is provided so that the stored contents of the memory can be retained even when the supply of the power supply current to the substrate is cut off,
For example, when the main power is turned off in the state of a jackpot, when the main power is turned on to perform a new game next, the game is started from a state of a jackpot or the like, which is unfair to the player. There was a problem.

In order to solve the above-mentioned problems, the present invention provides a disadvantage to a player when the supply of power is restored even when the supply of power to a part or all of the substrates is undesirably cut off. It is an object of the present invention to provide a gaming machine that can continue the game so as not to become unreliable, and can easily return to an initial state so as not to be unfair to a player when playing a new game. .

[0005]

According to a first aspect of the present invention, there is provided a gaming machine comprising: a main board for controlling the gaming machine; and a power supply board for supplying power to the main board. A gaming machine provided with backup means for supplying backup power to the volatile memory of the main board to back up the contents of the volatile memory so that the contents of the volatile memory are not erased; and Erase switch means operated to erase the contents of the memory; and erase control for controlling the contents of the volatile memory backed up by the backup means to be erased when the erase switch means is operated. Means are provided.

In the gaming machine having this structure, the backup means supplies backup power to the volatile memory of the main board so that the volatile memory can be backed up so that the contents of the volatile memory are not erased. Even when the supply of power is interrupted, the game can be continued so as not to be disadvantageous for the player when the supply of power is restored. Also provided is an erase switch means and an erase control means,
When the erase switch means is operated, the contents of the volatile memory backed up by the backup means can be erased, so that when playing a new game, it is easy to return to the initial state so as not to be unfair to the player. Can be.

In the gaming machine according to the second aspect of the present invention, a main board for controlling the gaming machine and a control board for controlling the main board are provided.
A gaming machine in which the above-described sub-board and a power supply board for supplying power to the main board and the sub-board are provided independently of each other, wherein at least one of the main board and the sub-board is provided. Backup means for supplying backup power to the volatile memory to back up the volatile memory so that the contents of the volatile memory are not erased, and erasure operated to erase the contents of the volatile memory backed up by the backup means A switch means and an erasure control means for controlling the contents of the volatile memory backed up by the backup means to be erased when the erasure switch means is operated.

In the gaming machine having this structure, the backup means supplies backup power to the volatile memories of the main board and the sub-board so that the contents of the volatile memory can be backed up without being erased. Even when the supply of power supply current to the sub-board is cut off, when the supply of power is restored, the game can be continued so as not to be disadvantageous for the player. In particular, since the backup is performed even on the sub-board, the state before the supply of the power supply current is cut off can be restored more reproducibly. In addition, when the erase switch means is operated, the contents of the volatile memory backed up by the backup means can be erased when the erase switch means is operated. It is possible to easily return to the initial state so as not to go out.

According to a third aspect of the present invention, in addition to the configuration of the second aspect of the present invention, the erase control means further comprises:
When the erase switch is operated, a signal resulting from the operation of the erase switch is obtained by using the CPU of the main board or the sub-board on which the volatile memory backed up by the backup is arranged. Accordingly, control is performed such that the contents of the volatile memory are erased for each substrate.

In the gaming machine having this structure, in addition to the function of the gaming machine according to the second aspect, when the erase switch is operated, the main board or the sub board on which the volatile memory backed up by the backup is arranged. Using the CPU of the substrate, the contents of the volatile memory can be erased for each substrate in response to a signal resulting from the operation of the erase switch means. The contents of the memory can be erased.

According to a fourth aspect of the present invention, in addition to the configuration of the second aspect of the gaming machine, the erasure control means includes:
When the erase switch is operated, the CPU of the main board on which the volatile memory backed up by the backup is arranged is used, and the main switch is operated in accordance with a signal resulting from the operation of the erase switch. While erasing the contents of the volatile memory arranged on the board, the CPU of the main board sends a predetermined signal to the CPU of the sub-board, and the CPU of the sub-board makes the CPU of the sub-board dispose the volatile memory arranged on the sub-board. The control is performed such that the contents of the memory are erased.

In the gaming machine having this configuration, in addition to the function of the gaming machine according to the second aspect, when the erase switch is operated, the CPU of the main board on which the volatile memory backed up by the backup is arranged. And erases the contents of the volatile memory arranged on the main board according to a signal resulting from the operation of the erase switch means, and the CPU on the main board sends a predetermined signal to the CPU on the sub-board, The contents of the volatile memory arranged on the sub-board can be erased by the CPU of the board.

In the gaming machine according to a fifth aspect of the present invention, in addition to the configuration of the gaming machine according to any one of the first to fourth aspects, the erasing control means is configured to operate the erasing switch means while operating the erasing switch means. When the main power of the device is turned on, control is performed such that the contents of the volatile memory are erased.

In the gaming machine having this configuration, in addition to the operation of the gaming machine according to any one of claims 1 to 4, when the main power of the gaming machine is turned on while the erase switch is operated, the volatilization is performed. Since the contents of the volatile memory are erased, the contents of the volatile memory can be easily erased by arbitrarily operating the erase switch means only when the contents of the volatile memory are to be erased.

In the game machine according to a sixth aspect of the present invention, in addition to the structure of the game machine according to any one of the first to fifth aspects, the erasing control means includes a main power supply of the game machine which is turned on. When the operation of the erase switch means is detected until a predetermined time has elapsed since the start of the operation, the content of the volatile memory is controlled to be erased.

In the gaming machine having this configuration, in addition to the operation of the gaming machine according to any one of the first to fifth aspects, it is also possible to provide the gaming machine with a predetermined time after the main power of the gaming machine is turned on. In order to erase the contents of the volatile memory when the operation of the erase switch means is detected, the operation of the erase switch means is detected for a certain period of time to prevent malfunction, and after a predetermined time has elapsed, the erase switch means is operated. However, the contents of the volatile memory are not erased.

According to a seventh aspect of the present invention, in addition to the configuration of the gaming machine according to any one of the first to sixth aspects, the volatile memory includes a substrate on which the volatile memory is disposed. It is characterized by being a main storage unit integrally formed with a CPU, a nonvolatile memory, and the like, and configured as a part of a one-chip microcomputer having a backup power supply terminal for the volatile memory.

In the gaming machine having this configuration, in addition to the function of the gaming machine according to any one of claims 1 to 6, the volatile memory includes a CPU and a non-volatile memory of a substrate on which the volatile memory is disposed. Since it is a main storage device that is integrally formed with the like and is configured as a part of a one-chip microcomputer having a backup power supply terminal for the volatile memory,
The structure of the substrate can be made simpler.

According to an eighth aspect of the present invention, in addition to the configuration of the gaming machine according to any one of the first to seventh aspects, the erase switch means is arranged on the power supply board. And

In the gaming machine having this structure, in addition to the function of the gaming machine according to any one of the first to seventh aspects, the erase switch means is arranged on the power supply board, so that the power is supplied to the erase switch means from the power supply board. Easy.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below by way of examples with reference to the drawings.

(Embodiment 1) A pachinko machine 1 according to Embodiment 1 of the present invention will be described with reference to the drawings. First, the mechanical configuration of the pachinko machine 1 will be described. FIG. 1 is a front view of the pachinko machine 1. As shown in FIG. 1, a substantially square game board 2 is provided in an upper half portion of the front of the pachinko machine 1, and a substantially circular game area 4 surrounded by a guide rail 3 is provided on the game board 2. Is provided. A lower plate of the game board 2 of the pachinko machine 1 is provided with an upper plate 5 for supplying a game ball to a launcher (not shown) and receiving a prize ball. A lower plate 6 for receiving an overflowing prize ball is provided, and a firing handle 7 is provided on the right side of the lower plate 6.

Next, the mechanical structure of the game board 2 is shown in FIG.
This will be described with reference to FIG. FIG. 2 is a front view of the game board 2 of the pachinko machine 1. The game board 2 has a substantially circular game area 4 surrounded by a guide rail 3, and a special symbol display device 8 having a liquid crystal screen is provided at substantially the center of the game area 4. In addition, an illuminated windmill 9 is provided on the upper right of the special symbol display device 8, and an illuminated windmill 10 is also provided on the upper left. Further, a normal symbol start gate 11 is provided on the right side of the special symbol display device 8, and an ordinary symbol start gate 12 is provided on the left side.

A special symbol starting electric accessory 15 is provided directly below the special symbol display device 8, and a special winning opening 16 is provided below the special symbol starting electric accessory 15. A winning opening 30 and a winning opening 31 are provided on the left and right of the special winning opening 16.

A winning opening 19 is provided below the ordinary symbol starting gate 11, and a winning opening 20 is provided below the ordinary symbol starting gate 12. Further, a stage 21 on which game balls can be temporarily mounted is horizontally provided below the special symbol display device 8. A game ball passage opening 22 is provided on the right shoulder of the special symbol display device 8, and a game ball passage opening 23 is also provided on the left shoulder of the special symbol display device 8. The game balls passing through these game ball passage openings 22 and 23 appear on the stage 21 through the inside (warp zone) of the special symbol display device 8. The game ball appearing on the stage 21 falls toward the special symbol starting electric accessory 15 provided immediately below the stage 21.

Above the special symbol display device 8, a normal symbol display device 24 is provided so that a symbol such as a single digit or a single alphabet can be displayed. Further, a special symbol starting reservation unit 25 composed of two LEDs is provided on each of the right and left sides of the ordinary symbol display device 24 to display the number of so-called reserved balls that have won the special symbol starting electric accessory 15. Can be. Also, between the special symbol display device 8 and the ordinary symbol display device 24, 4
There is provided a normal symbol start reservation unit 26 composed of a plurality of LEDs, and this normal symbol start reservation unit 26 can display the so-called reserved ball number of game balls that have passed the normal symbol start gates 11 and 12. In addition, in addition to the above, an out port, various illumination lamps, a windmill, a large number of obstacle nails, and the like are arranged at predetermined positions on the game board 2.

Next, the structure and display screen of the special symbol display device 8 will be described with reference to FIG. FIG. 3 is a front view of the special symbol display device 8. As shown in FIG. 3, on the liquid crystal screen of the special symbol display device 8, three special symbols of a first stop symbol L1, a second stop symbol L2, and a third stop symbol L3 can be displayed side by side in a horizontal direction. ing. In addition, the special symbol display device 8 performs the above-described first stop symbol L1 and second stop symbol L
2. In addition to displaying the third stop symbol L3, a moving image, a message, and the like can be displayed. The special symbols may be displayed not only horizontally but also vertically or diagonally. The special symbol display device 8 uses not only a liquid crystal display device but also a CR
It goes without saying that various display devices such as T, LED, and plasma display can be used. The special symbol display device 8 includes a symbol control board 44 (see FIG. 4) on the back surface.

The first stop symbol L1 and the second stop symbol L
2. Examples of the symbols displayed on the third stop symbol L3 include "10,000", "20,000", "30,000", which imitate a mahjong tile.
"Shiman", "50,000", "60,000", "70,000", "80,000"
"Kuman", "white solid" (hereinafter "white"),
There are twelve kinds of "Hatsu" and "Medium", and the game ball wins the special symbol starting electric accessory 15, and the three symbols of the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3 are displayed. In the case where the same number, character or pattern are arranged (for example, three "Seven thousand" shown in FIG. 3 are arranged), or in the case where a specific number, character or pattern is combined, etc. A jackpot.

Of the twelve symbols, "Sanma", "Five thousand", "Seven thousand", "White", "Hatsu", and "Medium" are probability variation symbols (specific jackpot symbols). If any of the symbols is the same as the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3, the probability change is entered, and the probability of drawing the next big hit is increased. change. The probability of a jackpot is, for example, in the normal state,
317.6 times, and 68.1 in the probability fluctuation state.
It is 1 / min, but is not necessarily limited to this value. In addition, "10,000", "20,000", "40,000", "60,000"
"Yama" and "Kuma" are non-stochastic fluctuation symbols (non-specific jackpot symbols or normal symbols).

Next, an electric circuit configuration of the pachinko machine 1 of the present embodiment will be described with reference to FIG. FIG.
FIG. 2 is a block diagram illustrating an electric circuit configuration of the pachinko machine 1. The control unit of the pachinko machine 1 includes a main board 41, a power board 4
2, sound board 43, symbol display board 44, payout control board 4
5, an illumination board 46, and a launch board 47. The main board 41 includes a power board 42, a sound board 43, and a symbol display board 4.
4. The payout control board 45, the illuminated board 46, and the firing board 47 are connected to each other.

FIG. 5 shows the main board 4 of the pachinko machine 1.
1. supply of a power supply current between the power supply board 42, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46;
FIG. 4 is a diagram illustrating a signal flow. As shown in FIG. 5, the main board 41 includes a CPU 41a, a ROM 41b, and a RAM 41.
c, an I / O interface 41d, a reset circuit 17, and the like are connected to each other by a bus line 41e and provided.
On the power supply board 42, an erase switch 42s is provided.
CPU 43a, ROM 43b, RAM 4
3c, I / O interface 43d, etc.
and are connected to each other by e. Similarly, the CPU 44a, the ROM 44b, the RAM 4
4c, the I / O interface 44d, etc.
e, connected to each other, and provided to the payout control board 45.
CPU 45a, ROM 45b, RAM 45c, I /
The O interface 45d and the like are connected to each other by a bus line 45e and provided.
a, a ROM 46b, a RAM 46c, an I / O interface 46d, etc., are connected to each other by a bus line 46e. In addition, a connection line connected to the power supply board 42 has an AC24 supplied from a power supply source (not shown).
A power switch 80 capable of supplying or interrupting V power current is provided.

From the power supply board 42, a power supply line 82a is connected to the main board 41, a power supply line 82b is connected to the sound board 43, and a power supply line 82 is connected to the symbol display board 44.
is connected, the power supply line 82d is connected to the payout control board 45, the power supply line 82e is connected to the illuminated board 46, and the power supply current is connected to each board. The power supply line 8
For 2a to 82e, as shown in FIG. 4, power supply lines for supplying power of a voltage corresponding to each application such as DC + 12V and DC + 5V including a backup power supply to each substrate are separately provided. Is omitted for simplicity of description.

Erase switch 4 provided on power supply board 42
2s is connected to the I / O interface 41d of the main board 41 by a signal line 79a, connected to the I / O interface 43d of the sound board 43 by a signal line 79b, and I / O of the symbol display board 44 by a signal line 79c. O interface 44d, and the payout control board 4 is connected by a signal line 79d.
5 is connected to the I / O interface 45d of
9e, the I / O interface 46d of the illuminated board 46
It is connected to the.

The erase switch 42s is a push button switch, for example, and is configured to close the circuit only when the switch is pressed. When the erase switch 42s is pressed, a signal of a predetermined voltage is transmitted to the main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46 by the power supply current supplied from the power supply board 42. Be composed. The main board 41, the sound board 43, and the design display board 4
4. The circuit may be configured such that the supply current is supplied from all or a part of the payout control board 45 and the illuminated board 46, and the circuit is opened and closed by the erase switch 42s. Note that the wiring may be wired in a star shape or a loop shape.

When the erase switch 42s is opened and closed in this manner, for example, a signal sent from the erase switch 42s via the signal line 79a connected to the main board 41 is transmitted from the I / O interface 41d to the CPU via the bus line 41e.
41a, and the CPU 41a of the main board 41
It acknowledges that the erase switch 42s is ON. Similarly, a signal transmitted by the erase switch 42s via the signal line 79b connected to the sound board 43 is transmitted from the I / O interface 43d to the CP via the bus line 43e.
CPU 43a of the sound board 43 received by the U43a
Acknowledges that the erase switch 42s is ON, and the signal transmitted by the erase switch 42s through the signal line 79c connected to the symbol display board 44 is transmitted from the I / O interface 44d through the bus line 44e. CPU
CPU 44 of the symbol display board 44
a recognizes that the erase switch 42s is ON, and sends a signal transmitted by the erase switch 42s via the signal line 79d connected to the payout control board 45 from the I / O interface 45d to the bus line 45e. Via CP
The CPU 4 of the payout control board 45 received by the U45a
5a recognizes that the erase switch 42s is ON, and the signal transmitted by the erase switch 42s through the signal line 79e connected to the electric decoration board 46 transmits the signal from the I / O interface 46d to the bus line 46e. Via CPU
CPU 46a of the illumination board 46
Acknowledges that the erase switch 42s is ON.

Returning to FIG. 4, the main board 41 has a winning opening switch 32 provided at each of the winning openings 19, 20, 30, 31 (see FIG. 2), and a special symbol start-up. A starting port switch 33 for detecting a winning of a game ball to the electric accessory 15 and a gate switch 3 for detecting passing of the game ball to the normal symbol starting gates 11 and 12 (see FIG. 2).
4, a count switch 35 for detecting the number of winning balls of the game balls to the special winning opening 16, and a V provided in the special winning opening 16.
A V-switch 36 for detecting a prize of a game ball to a zone (not shown), and a special symbol starting electric accessory solenoid 3 for opening and closing an opening / closing member of the special symbol starting electric accessory 15 (see FIG. 2).
7, a special winning opening solenoid 38 for opening and closing the special winning opening 16 (see FIG. 2), a guiding device solenoid 39, an external connection terminal 2 board 40 for outputting jackpot information of the gaming machine to an external device, and a 7 segment It is connected to a normal design board 60 which is composed of LEDs and displays a normal design.

The external connection terminal 2 board 40 is provided with a jackpot 1 information terminal, a jackpot 2 information terminal, and a symbol confirmation information terminal. It is possible to output the information of the symbol to be performed. A special symbol display device 8 is connected to the symbol display substrate 44, and a speaker 61 is connected to the sound substrate 43.
Is connected, and the illuminated board 46 is
2 is connected, and the game board 2
Each illumination lamp provided on the surface of is connected.

Further, on the main board 41, a lower plate full detection switch 6 for detecting that the lower plate 6 is full of game balls is provided.
3, a prize ball passage ball cut-out detection switch 64 for detecting a ball cut in a prize ball passage (not shown), and a prize ball payout confirmation switch 65 for checking the number of prize ball payouts from a prize ball device (not shown). Have been. The award ball payout confirmation switch 65 is also connected to the payout control board 45.

The payout control board 45 also has a ball lending passage ball out detection switch 66 for detecting a ball lending passage running out.
And a ball lending and payout confirmation switch 67 for checking the number of balls to be paid and paid out from a ball lending device (not shown), a prize ball payout solenoid 68 for driving a prize ball device (not shown), and a ball lending device (not shown). A ball lending and dispensing solenoid 69 to be driven and a prize ball device provided from a prize ball tank for storing a prize ball provided at the upper rear portion of the pachinko machine 1 are provided on a tank rail (not shown) for guiding game balls to the ball lending device. A tank rail vibration motor 70 for applying vibration to the tank rail to prevent clogging of game balls on the tank rail; a prepaid card unit 71 for reading lending data from the prepaid card;
The external connection terminal 1 and the substrate 72 are connected. The external connection terminal 1 board 72 is provided with a prize ball payout number information terminal and a ball rental payout number information terminal, and can output the prize ball payout number information and the ball rental payout number information to an external device.

Further, on the launch board 47, a launch ball jump strength adjustment volume 73 built in the launch handle 7 is provided.
, Launch device stop switch 74, touch sensor 75
And the launch motor 76 are connected.

Next, the power supply board 42 will be described. 24 V AC is input to the power supply board 42 via a power switch 80, and a DC 5 V, DC 12 V, DC 24 V, DC 3 V
2V can be output. The power supply board 42 can also output a reset signal, a backup power supply, a power failure detection signal, and 24 V AC. Further, in the power supply board 42, the DC 12V output is DC + 1
Three circuits of 2VA, DC + 12VB and DC + 12VC are prepared. DC + 12VA is connected to the main board 41, and DC + 12VB is connected to the main board 41 and the payout control board 45.
The DC + 12VC is connected to the special symbol display device 8, the sound board 43, and the illumination board 46. In addition, from the power supply board 42, 24V AC is input to the payout control board 45, and the backup power supply is a main board 41, a sound board 43, a symbol display board 44, a payout control board 45, an electric decoration board. 46.

The output of DC 24V is DC + 24V
A and DC + 24VB 2 circuits are prepared, DC + 24V
A is connected to the main board 41, and DC + 24VB is connected to the payout control board 45. Further, an output of DC 32 V is provided in one circuit of DC + 32 V, and is connected to the launch board 47. An output of DC 5V is provided in one circuit of DC + 5V, and is connected to the main board 41, the special symbol display device 8, the sound board 43, the payout control board 45, the illuminated board 46, and the emission board 47. Note that a firing device stop signal is input from the payout control board 45 to the firing board 47 via a signal line 77.

An erase switch 42 s is arranged on the power supply board 42, which is the erase switch 42 s in the first embodiment.
Since the power for transmitting the signal is supplied from the power supply board 42, the power supply is provided on the power supply board 42, and the erase switch 42s is not necessarily provided on the power supply board 42.
You do not need to place them. For example, a push button may be provided at a position separated from the power supply board 42 or operated by a key operation. In short, the position and form are not limited as long as a signal can be transmitted.

Next, referring to FIG. 5, the main board 41, the power supply board 42, the sound board 43, and the symbol display board 4 of the first embodiment.
4. The payout control board 45, the illuminated board 46, and the supply of the power supply current and the flow of signals between them will be described in detail. First,
The main board 41 includes a CPU 41a, a ROM 41b, a RAM
41c and a reset circuit 17 are provided.
The M41b stores a main control program executed by the CPU 41a for controlling the entire pachinko machine 1, data of initial values, and the like. Further, a program for erasing the stored contents of the backed-up RAM 41c in the present embodiment is also stored here. Therefore, C
The PU 41a constitutes the erasure control means of the present invention. The RAM 41c is a volatile memory for storing various data and the like. Even when the power supply from the power supply is cut off, the stored contents are retained for a long time.

The sound board 43 includes a CPU 43a, a ROM 4
3b, a RAM 43c, and the like are provided mutually connected to a bus line 43e. The ROM 43b stores audio data and the like, and stores various programs executed by the CPU 43a, data of initial values, and the like. Also,
Backed-up RAM 43c in the present embodiment
The program for erasing the stored contents of the above is also stored here. The RAM 43c is a volatile memory that stores various data and the like. Even when a normal power supply from the power supply board 42 to the sound board 43 is cut off by the backup power supply of the power supply board 42, the storage contents thereof are stored. Is held.

A CPU 44a, R
The OM 44b, the RAM 44c, and the like are provided so as to be mutually connected to the bus line 44e, and the ROM 44b stores various display data and CPUs displayed on the special symbol display device 8.
Various programs executed by 44a, data of initial values, and the like are stored. Further, a program for erasing the stored contents of the backed-up RAM 44c in the present embodiment is also stored here. Also, R
The AM 44c is a volatile memory for storing various data and the like. Even when the normal power supply from the power supply board 42 to the symbol display board 44 is cut off by the backup power supply of the power supply board 42, the stored contents are stored. It is to be retained. Note that the symbol display substrate 44 can be configured to include a plurality of CPUs in accordance with the recent increase in definition and speed of images.

CPU 45a, R
An OM 45b, a RAM 45c, and the like are provided so as to be mutually connected to a bus line 45e.
Various programs executed by the U45a, data of initial values, and the like are stored. Further, a program for erasing the stored contents of the RAM 45c backed up in the present embodiment is also stored here. Also,
The RAM 45c is a volatile memory that stores various data, for example, the number of winning prize balls, the number of prize balls to be paid out, and the like. The power supply board 42 to the payout control board 45 Even if the normal power supply is cut off, the stored contents are retained.

A CPU 46a, a ROM,
46b, a RAM 46c, and the like are provided mutually connected to a bus line 46e.
A program such as various illumination patterns executed by 6a and data of initial values are stored. Further, a program for erasing the stored contents of the RAM 46c backed up in the present embodiment is also stored here. The RAM 46 c is a volatile memory that temporarily stores various data, for example, an illumination pattern to be controlled at the time of a big hit, and is supplied from the power supply substrate 42 to the illumination decoration substrate 46 by a backup power supply of the power supply substrate 42. Even if the normal power supply is cut off, the stored contents are retained.

The backup power supply of the power supply board 42 is N
It is composed of a secondary battery such as an iCd battery, an electrolytic capacitor, or the like, and is a NiC which is a backup power supply when a current of 24 V AC which is a normal power supply current is input.
A secondary battery such as a d-battery, an electrolytic capacitor, and the like are configured to be charged. When the supply of power to the power supply board 42 is stopped, the current charged in a secondary battery such as a NiCd battery or an electrolytic capacitor is transferred to the RAM 41c of the main board 41, the RAM 43c of the sound board 43, and the symbol display board 44. RAM 44c, RAM 4 of the payout control board 45
5c, it can be supplied to the RAM 46c of the illuminated substrate 46 as a power source for storing and storing. Further, a power switch 80 is provided on the input side of the AC 24 V of the power supply board 42, and the supply of the AC 24 V to the power supply board 42 and the stop of the supply are enabled.

Further, in the main substrate 41 of this embodiment, C
PU41a, ROM41b, RAM41c are one chip
Formed as a modular 64-pin microcomputer
This microcomputer has a power supply terminal for backup.
The child V_BBIt has terminals. This V_BBTerminal is DC +
A current from a 5V backup power supply is input. this
In the microcomputer, V_BBIf there is no input to the terminal,
It is configured so that the main power of the So
Therefore, if the RAM 41c is soft as in the present embodiment,
If there is no means for erasing the contents stored in the RAM 41c
If you try to erase_BBThe cord connected to the terminal
Pull out the cable or provide a separate switch for disconnection
V from the backup power supply of the power supply board 42
_BBThe connection to the terminal must be physically disconnected.
However, in this case, the power supply of the main board 41 itself is turned off.
Inconvenience. Also, the sound board 4
3, symbol display board 44, payout control board 45, illumination board 4
6 also has the same configuration as the main substrate 41,
In the storage of these RAMs 43c, 44c, 45c, 46c
In order to erase the contents,
V from power supply for up _BBPhysically disconnects the connection to the terminal
Must. In the pachinko machine 1 of the first embodiment,
Without such complicated work, the main board 41, the sound board 43,
Of the symbol display board 44, the payout control board 45, and the illuminated board 46
Storage of RAMs 41c, 43c, 44c, 45c, 46c
The contents can be easily erased.

Next, the operation of the pachinko machine 1 according to the first embodiment will be described with reference to flowcharts shown in FIGS. 7 and 8, taking a main routine (main control) of control on the main board 41 as an example. FIG. 7 is a flowchart showing a main routine (main control) of the pachinko machine 1. FIG.
5 is a flowchart showing in detail a procedure of a power-on process (S1) of the flowchart shown in FIG.

In the main routine of the flowchart shown in FIG. 7, the reset circuit 17 shown in FIG. 5 is executed at fixed intervals (for example, 2 milliseconds, hereinafter referred to as "2 ms").
CPU of the main board 41 according to the reset signal
41a performs processing in order from the start, and performs the processing from the start to the end within 2 ms.
Therefore, every time the reset signal is input at intervals of 2 ms, the process is repeated from the start. The program for performing the processing of the flowchart shown in FIG.
1b. 7 to 11 and the following description, “step” in the flowchart is abbreviated as “S”.

First, the main routine of the pachinko machine 1 will be described with reference to FIG. First, when the power is turned on, a power-on process (S1) is executed.

Here, the procedure of the power-on process (S1) in the flowchart shown in FIG. 7 will be described in detail with reference to FIG. When the power is turned on from the power supply board 42 to the main board 41 (power ON), that is, when the power switch 80 of the power supply board 42 is turned on or the power failure state is recovered,
The CPU 41a of the main board 41 starts up, and the ROM 41a
The following procedure is performed in accordance with the control program read from. When the CPU 41a starts up, the erase switch 42s disposed on the power supply board 42 is turned on via the I / O interface 41d and the signal line 79a as shown in FIG.
It is determined whether or not the operation has been performed (S20). For example, if the signal from the erase switch 42s is equal to or higher than a predetermined HI level voltage, it is determined to be ON (S20: YES), and if it is lower than the predetermined level voltage, it is OFF. Judge (S20: N
O).

In the pachinko machine 1, when the power switch 80 is closed, the RAM 41c
When the power switch 80 is turned off, the main board 41 is supplied from the battery of the backup power supply via the power supply line 82a even when the power switch 80 is turned off. since the power supply current from the _{V BB} pin RAM41c one-chip microcomputer provided is input, the contents stored in the RAM41c is held as it is.

Here, in S20, the erase switch 42
s is not ON (S20: N
O), that is, when the erase switch 42s is not pressed, the power restoration process (S28) is performed. Power restoration processing (S2
8) a case where the CPU 41a reads out the contents stored in the backed-up RAM 41c, and based on the contents stored in the RAM 41c, the power supply is cut off by the administrator's will or against the will. Then, the state of the pachinko machine 1 is restored to the state before the power was turned off. Therefore, for example, even if a power failure due to an accident occurs during the game of the player, if the player is in a jackpot state before the power failure, RA is restored after the power is restored.
Since the big hit flag stored in M41c is on, the game can be continued in the big hit state again.

If the pachinko machine 1 has already performed the normal processing, the power restoration processing (S28)
The recovery process is not performed, and the process based on the contents stored in the RAM 41c is continued. When the power restoration process (S28) ends, the power-on process (S1) of FIG. 7 ends (FIG. 8: END), and the process proceeds to the next stack pointer setting process (FIG. 7: S2).

On the other hand, if it is assumed that the erase switch 42s is depressed when the power is turned on, the fact that the erase switch 42s is ON indicates that the I / O interface 41 and the signal line 79 are on.
a (YES in S20), and the CPU 41a
As a result, a backup RAM clear procedure for clearing the backed up contents of the RAM 41c by software is executed (S22). In this case, the contents of the RAM 41c are completely cleared. And backup RAM
When the clear (S22) process is completed, the power-on process (FIG. 7: S1) of FIG. 7 ends (FIG. 8: END),
The process proceeds to the next stack pointer setting process (FIG. 7: S2).

In the flowchart shown in FIG. 8, when the power-on process (S1) is completed, a stack pointer setting process for setting a designated address of the stack pointer is performed (S2). Next, a RAM check for checking the stored contents of the RAM 41c is performed (S3). The RAM check (S3) is for determining whether or not the power-on initial setting process (S4) is being performed. At this time, it is determined whether or not a predetermined numerical value written in the power-on initial setting process (S4) is written in the initial setting storage area of the RAM 41c.

The backup RAM clear of FIG. 8 (S2
When the process of 2) is being performed, since a predetermined numerical value is not written in the initial setting storage area of the RAM 41c (S3: NO), the power-on initial setting process is performed (S4). In addition, even when the power is not turned on, for some reason R
When the storage of the AM 41c is not normal, the RAM check (S3) also determines that the storage is not normal. In this process, the storage value of each storage area of the RAM 41c is set to a predetermined default value. For example, the value of each loop counter stored in a loop counter storage area (not shown) is set to an initial value (for example, “0”), and a predetermined numerical value is stored in the initial setting storage area.
Then, the processing of FIG. 7 is temporarily ended (end).

Processing is performed from the start by the reset signal. First, in the power-on process (S1), if the erase switch 42s is not pressed (FIG. 8: S20: N)
O), a power recovery process (S28) is performed,
1c, the processing is performed based on the storage, and as described above, nothing is performed here and the stack pointer setting processing (S
Go to 2). And in the RAM check (S3),
Since a predetermined numerical value is written in the initial setting storage area, the RAM 41c is determined to be normal (S3: YES),
The process proceeds to the next liquid crystal screen command output process (S5). In the liquid crystal screen command output processing (S5), the main board 41
Sends a signal for controlling the display of the liquid crystal screen to the symbol display board 44, and the symbol display board 44
At the same time, the information is stored in the AM 44c, and the predetermined symbol information is read out from the table stored in the ROM 44b by the designation or the lottery designated based on the control signal, and the image information is transmitted from the drive circuit (not shown) to the special symbol display device 8. . Next, the process proceeds to a sound command output process (S6). In this sound command output processing (S6), the main board 4
A signal designating a pattern to be uttered by the speaker 61 is sent from 1 to the sound board 43, and the sound board 43 reads out voice information according to the pattern from the ROM 43b and makes the speaker 61 utter the voice information via the drive circuit. Next, a lamp command output process (S7) is performed. In the lamp command output process (S7), a signal designating a blinking pattern of various lamps provided in the pachinko machine 1 is output from the main board 41 to the illumination board 46. The illuminated board 46 reads the illuminated control information of this pattern from the ROM 46b and sends out drive signals to various lamps. Then
Port output processing is performed (S8). In the port output process (S8), the jackpot information, the symbol determination information, and the like of the pachinko machine 1 are output to a game center management computer (not shown) via the external connection terminal 2 board 40 and the like.

Next, a switch reading process (S9) is performed. This switch reading process (S9) is performed by the normal symbol starting gates 11 and 12 and the special symbol starting electric accessory 1 shown in FIG.
5, detecting a winning of a game ball to the special winning opening 16, the winning opening 19, 20, 30, 31 or the like.

When the switch reading process (S9) is completed,
Next, a loop counter updating process (S10) is performed. In the loop counter updating process (S10), the RAM 41
The values of the normal symbol selection loop counter, the jackpot determination loop counter, the special symbol creation counter, the reach determination counter, and the reach pattern determination counter stored in the loop counter storage area (not shown) of FIG. Increment). When the value exceeds the maximum value set in each loop counter, the value of each loop counter is cleared to 0 and programmed to return to "0".

Next, it is determined whether an error has occurred in the pachinko machine 1 (S11). If an error has occurred in the pachinko machine 1 (S11: YES), the condition device process (S12) The special symbol processing (S13) and the normal symbol processing (S14) are skipped to perform the processing, and the special symbol display device 8
To display an error or the like. If no error has occurred (S11: NO), the process proceeds to the condition device process (S12).

In the condition device processing (S12), the special winning opening 1
6 (see FIG. 2), a jackpot demonstration display process on the liquid crystal screen (see FIG. 3) of the special symbol display device 8, and the like are performed. In the first round of processing, a special symbol processing (S
Since the jackpot determination process in 13) has not been performed yet, in the condition device process (S12), nothing is performed and the process proceeds to the next process. Next, a special symbol process (S13) is performed. In the special symbol processing (S13), a big hit determination processing is performed.

When the special symbol processing (S13) is completed, next, a normal symbol processing (S14) is performed. In the ordinary symbol processing (S14), the count value of the ordinary symbol selection loop counter (not shown) is changed to the ordinary symbol random number by the passing of the game ball to the ordinary symbol starting gates 11, 12, and the RAM is used as the ordinary symbol random number.
41c is stored in a non-illustrated ordinary symbol random number storage area,
The symbols are fixedly displayed on the ordinary symbol display device 24 based on the ordinary symbol random numbers.

When the normal symbol processing (S14) is completed, next, a payout control (S15) for paying out prize balls is performed.
When paying out prize balls, the signal line 78 is
A payout request command is transmitted to the payout control board 45 via the. The payout control board 45 temporarily stores a payout request command in the RAM 45c, and pays out prize balls sequentially based on the payout request command. Then, the frame lamp control (S16)
After that, the processing of the main routine ends. The processing of this main routine includes the processing of the subroutine and
It ends within ms. Therefore, the main routine does not always execute all the procedures up to the end, leaves the result of the processing in a flag or the like, and is executed so as to always end within 2 ms. The CPU 41a receives a reset signal from the reset circuit 17 every 2 ms.
Repeats the processing of the main routine shown in FIG. 7 from the start.

If it is determined in the special symbol processing (S13) of the processing of the main routine of the first cycle that the state is a big hit state, R
"1" is stored in a jackpot flag storage area (not shown) of the AM 41c, the jackpot flag is turned on, and the opening and closing operations of the jackpot 16 are performed a predetermined number of times in the next condition device processing (S12) in the second round. (For example, 15 times or 16 times
Times).

The pachinko machine 1 of the first embodiment has been described in detail with the main board 41 as an example. However, the sound board 43, the symbol display board 44, the payout control board 45, which are sub-boards other than the main board 41, Also in the illumination board 46, the main board 41
Similarly to the above, the signal of the erase switch 42s of the power supply board 42 is
From the signal lines 79b, 79c, 79d, 79e, I / O interfaces 43d, 44d, 45 of the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46, respectively.
d, 46d, the respective CPUs 43a, 44a,
The detection is performed by 45a and 46a, and the same control as that of the main board 41 is performed. That is, when the power is turned on, the same processing as the processing in the procedure of the flowchart shown in FIG. 8 is performed, and if the erase switch 42s is not pressed (S20: N
O), a power restoration process (S28) is performed. In addition, in the flowchart of FIG. 7, the processing of S1 to S4 is processing that is commonly performed in each substrate, and the processing of S5 to S16 is
The processing differs according to each substrate and is performed based on a unique flow. For example, in the case of the symbol display board 44, if a command from the main board 41 is stored in the RAM 44c, processing for displaying a symbol on the special symbol display device 8 is performed according to the command. Therefore, for example, if "10,000", "10,000", "10,000" is displayed on the special symbol display device 8, even after the power is turned on again, the special symbol display device is again displayed based on the storage in the RAM 44c. 8, "10,000",
"10,000" and "10,000" symbols are displayed. On the other hand, when the power is turned on again while the erase switch 42s is being pressed (S20: YES), the process of clearing the backup RAM (S22) is performed, and the initial screen is displayed on the special symbol display device 8. You.

In the case of the payout control board 45, if the erase switch 42s is not pressed (S20: N
O), power restoration processing (S28) is performed, and if the number of payout balls to be paid out is stored in the RAM 45c, the payout of payout balls is performed based on the storage. On the other hand, the erase switch 42
If the power is turned on again while s is pressed (S
20: YES), backup RAM clear (S22)
Is performed, and even if there is a prize ball to be paid out before the power is turned off, it is not paid out. The same applies to the sound board 43 and the illumination board 46.

Power recovery processing (S28) or backup RA
When the procedure of M clear (S22) is completed, the sound board 43,
Returning to the respective routines of the symbol display board 44, the payout control board 45, and the illuminated board 46, normal processing (not shown in detail) is continued. In the case of the normal processing, when the procedure of clearing the backup RAM (S22) is being executed, the RAM check in FIG.
For c, the same initial settings as in the power-on initial setting process (S4) in FIG. 7 are performed.

In the pachinko machine 1 according to the first embodiment, the case where the power is turned on while pressing the erase switch 42s when the power is turned on has been described. However, even if the erase switch 42s is pressed after the power is turned on (S20: YES). ), So that the process of clearing the backup RAM (S22) is performed. Therefore, if power is supplied to the pachinko machine 1, the RAM 41c and the like can be cleared at any time.

The ON condition of the power switch 80 and the ON condition of the erase switch 42s are AND conditions, and the power switch 8
RAM 41c, 43c, 44c, 45c, 46c only when the erase switch 42s is turned on when 0 is turned on.
Unless the power is once turned off and the power is turned on again, RA is depressed even if the erase switch 42s is pressed.
M41c, 43c, 44c, 45c, 46c may be configured not to be erased.

Further, the erase switch 4 is provided only for a predetermined time.
It may be configured such that input of 2s is permitted. Here, FIG. 9 is a flowchart showing another processing method of the power-on processing (FIG. 7: S1). As shown in FIG. 9, for example, in the case of the main board 41, the RAM 41c of the main board 41
The elapsed time obtained by counting the time since the power was turned on again is stored. If a predetermined time, for example, 30 seconds before the power was turned on (S120: NO), the erase switch 42s is turned on (S122: YES). ), Backup RAM
The process of clearing (S124) is performed, but after a predetermined time of 30 seconds has elapsed (S120: YES), the power restoration process (S126).
May be performed so that the process of clearing the backup RAM (S124) is not executed.

If the pachinko machine 1 is configured and controlled as in this modified example, the erasing switch 4 is not turned on until the predetermined time elapses after the main power of the pachinko machine 1 is turned on again.
Only when the press of 2s is detected, the RAMs 41c and 43
The contents of c, 44c, 45c, and 46c are deleted. That is, the CPU 41a, 43a,
44a, 45a and 46a repeatedly detect the detection of the erase switch 42s to prevent a detection error,
On the other hand, after 30 seconds, even if the erase switch 42s is operated, it is possible to prevent the contents of the RAMs 41c, 43c, 44c, 45c and 46c from being erased. In this case, the RAMs 41c, 43c, 44c, 45c, 46
If the content of c is to be erased after 30 seconds, the backup power supply must be cut off by hardware because the software cannot be erased. In this case, however, it was formed in a one-chip microcomputer as described above. Input terminal Vc of main power supply
c (not shown), the main power of the pachinko machine 1 is turned off, and the RAM is
It is also possible to prevent the contents of 41c, 43c, 44c, 45c, 46c from being erased. Of course, the predetermined time may be set to one second after the power is turned on again, or may be set to five minutes depending on the purpose.

As described above, the pachinko machine 1 according to the first embodiment of the present embodiment has the following configuration and operation, and has the following effects. That is, the main board 41 and the sound board 4 which is a sub-board
3, symbol display board 44, payout control board 45, illumination board 4
RAMs 41c, 43c and 44 which are volatile memories of No. 6
c, 45c, and 46c by supplying a backup power supply,
Since the contents of the RAMs 41c, 43c, 44c, 45c, and 46c can be backed up so as not to be erased, power supply to the main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46 is undesirably performed. When the power supply is restored even when the power supply is cut off, the game can be continued so as not to be disadvantageous to the player. In particular, the sound board 43, the symbol display board 44, the payout control board 45, and the illuminated board 46, which are the sub-boards, are also backed up, so that the state before the power supply is cut off can be restored more reproducibly.

The erase switch 42 s as erase switch means, the main board 41 and the sound board 4 as erase control means are provided.
3, symbol display board 44, payout control board 45, illumination board 4
6 are provided with the CPUs 41a, 43a, 44a, 45a, 46a and ROMs 41b, 43b, 444b, 45b, 46b. When the erase switch 42s is pressed, the backed up RAMs 41c, 43c, 44c, 45c, 4c are provided.
Since the contents of 6c can be deleted, when a new game is played, the player can easily return to the initial state so as not to be unfair.

In particular, when the erase switch 42s is pressed, the backed-up RAMs 41c, 43c, 44
main board 41 on which c, 45c, 46c are arranged, sound board 4
3, symbol display board 44, payout control board 45, illumination board 4
6 using the CPUs 41a, 43a, 44a, 45a, and 46a to erase the contents of the volatile memory for each substrate in response to a signal by pressing the erase switch 42s.
The main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the R
There is an effect that all the contents of the AMs 41c, 43c, 44c, 45c, and 46c can be easily erased.

Further, when the erase switch 42s is depressed,
In order to erase the contents of the AMs 41c, 43c, 44c, 45c and 46c, the erasure switch 42s is consciously operated only when the user wants to erase the contents.
An accident of erasing the content of c can be effectively prevented.

Also, for example, the RA provided on the main substrate 41
M41c, CPU41a, ROM41b are integrally formed as a one-chip microcomputer, due to the provision of a backup power supply terminal _{V BB} of RAM 41c, there is an effect that it the configuration of the main substrate 41 in a simpler structure. Also, the sound board 43, the symbol display board 44, the payout control board 4
5. The same applies to the illuminated substrate 46. Since the erase switch 42s is disposed on the power supply board 42, there is also an effect that the power supply from the power supply board 42 can be easily supplied to the erase switch 42s.

(Embodiment 2) Next, a pachinko machine 2 of Embodiment 2 which is another embodiment of the present invention will be described with reference to the drawings. Since the pachinko machine 2 has the same basic configuration as the pachinko machine 1, only the configuration different from the pachinko machine 1 will be described, and the same or equivalent components will be denoted by the same reference numerals and description thereof will be omitted. .

FIG. 6 shows the main board 4 in the pachinko machine 2.
1. supply of a power supply current between the power supply board 42, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46;
FIG. 4 is a diagram illustrating a signal flow. In the pachinko machine 1, as shown in FIG. 5, the erase switch 42s provided on the power supply board 42 is
The main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the I / O interfaces 41d, 43d, 44d, 45d, 46d of the illuminated board 46 are connected by d and 79e, respectively.

On the other hand, in the pachinko machine 2, the erase switch 42s provided on the power supply board 42 as shown in FIG. 6 is connected to the I / O interface 41d of the main board 41 by a signal line 83a. . Then, the I / O interface 41d of the main board 41 is connected to the I / O interface 43d of the sound board 43 by a signal line 83b,
The signal line 83c connects to the I / O interface 44d of the symbol display board 44, the signal line 83d connects to the I / O interface 45d of the payout control board 45, and the signal line 83e connects to the I / O interface of the illuminated board 46. The difference lies in being connected to the interface 46d. Other configurations are the same as those in FIG.

The main board 41 of the pachinko machine 2 configured as shown in FIG. 6 is controlled as follows. The main board 41 of the pachinko machine 1 shown in FIG.
Is executed. The main routine of the main board 41 of the pachinko machine 2 will now be described with reference to FIG. 7, which is the main routine of the main board of the pachinko machine 1. First, when the power is turned on, the power is turned on (S1).
Is executed. The pachinko machine 2 performs this power-on processing (S
The control of 1) is different from the control of the pachinko machine 1.

Here, FIG. 10 is a flowchart showing in detail the procedure of the power-on process (S1) of the flowchart shown in FIG. 7 for the main board 41 in the pachinko machine 2. Hereinafter, with reference to FIG. 10, the power-on processing of the pachinko machine 2 (S
The procedure 1) will be described in detail. Power supply board 4 on main board 41
2 when the power is turned on (power ON), that is, the power switch 80 of the power board 42 is turned on, or
When the power failure recovers, the CPU 41a of the main board 41 starts up and performs the following procedure according to the control program read from the ROM 41b.

As shown in FIG. 6, the signal from the erase switch 42s is transmitted to the I / O interface 41d of the main board 41 via the signal line 83a. Then, the main substrate 41
Of the erase switch 42s
Receive via the / O interface 41d. The CPU 41a that has started up there is the I / O interface 41.
d, It is determined whether the erase switch 42s provided on the power supply board 42 via the signal line 83a is turned on (S3).
0) For example, if the signal from the erase switch 42s is equal to or higher than a predetermined HI level voltage, it is determined to be ON (S30:
If it is less than the voltage of the predetermined level, it is determined to be OFF (S30: NO).

In the pachinko machine 2, when the power switch 80 is closed, the RAM 41c
The stored contents are retained by receiving the power supply current of C + 5V. Even when the power switch 80 is turned off, the power supply board 4
Through the power supply line 82a from the battery backup power source provided in the 2, since the power supply current from the V _BB pin RAM41c one-chip microcomputer provided in the main substrate 41 is entered, stored in RAM41c The content is kept as it is.

Here, in S30, the erase switch 42
s is not ON (S30: N
O), that is, when the erase switch 42s is not pressed, the power restoration process (S38) is performed as in the case of the pachinko machine 1. In the power restoration process (S38), the CPU 41a reads out the contents stored in the backed-up RAM 41c, and based on the contents stored in the RAM 41c, the power is turned on or off by the administrator. When the power is turned off, the state of the pachinko machine 2 is restored to the state before the power was turned off. Therefore, for example, even in the case where a power failure due to an accident occurs during a game of the player, if the player is in a jackpot state before the power failure, the jackpot flag stored in the RAM 41c is turned on after the power is restored. Therefore, the game can be continued in the jackpot state again.

When the pachinko machine 2 has already performed the normal processing, the power recovery processing (S38)
The recovery process is not performed, and the process based on the contents stored in the RAM 41c is continued. When the power restoration process (S38) ends, the power-on process (S1) in FIG. 7 ends (FIG. 10: END), and the process proceeds to the next stack pointer setting process (FIG. 7: S2).

On the other hand, if it is assumed that the erase switch 42s is depressed when the power is turned on, the fact that the erase switch 42s is ON indicates that the I / O interface 41d and the signal line 8
Detected via 3a (S30: YES).

Here, the RAM clear command is sent (S3
The procedure 2) is executed by the CPU 41a of the main board 41. In pachinko machine 2, unlike pachinko machine 1,
No signal is sent directly from the power supply board 42 to the erase switch 42s to the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46, which are the sub boards. Therefore, the fact that the erase switch 42s is ON is transmitted to the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46, which are sub-boards.
From the / O interface 41d, the signal lines 83b, 83
c, 83d, 83e, the I / O interface 43d of the sound board 43, the I / O interface 44d of the symbol display board 44, and the I / O interface 4 of the payout control board 45.
5d, a RAM clear command is sent to each of the CPUs 43a, 44a, 45a, 46a via the I / O interface 46d of the illuminated board 46. The RAM clear command is transmitted to the RAMs 43c, 44c,
This is a command for instructing to delete the contents of 45c and 46c.

The CPU 41a of the main board 41 which has completed the procedure of sending the RAM clear command (S32) executes a backup RAM clear procedure for clearing the backed up contents of the RAM 41c by software (S3).
4). In this case, the contents of the RAM 41c are completely erased (cleared). Then, the backup RAM is cleared (S
When the process of 22) is completed, the power-on process (S
After the processing of 1) is completed (FIG. 10: END), the process proceeds to the next stack pointer setting processing (FIG. 7: S2).
The main routine in the main board 41 of the pachinko machine 2 is the same as the control of the pachinko machine 1 after S2 in FIG. , The description of the control of the main board 41 of the pachinko machine 2 is omitted.

On the other hand, the sound board 43, the symbol display board 44, the payout control board 45, and the illuminated board 46, which are the sub boards of the pachinko machine 2, perform the processing according to the flowchart shown in FIG. Here, FIG. 11 is a flowchart showing a procedure of processing in the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46 of the pachinko machine 2. That is, when the power is turned on again, the CPUs 43a, 43
If the RAMs 4a, 45a, and 46a determine that the RAM clear command has not been received within a predetermined time (S40: NO), the power restoration process (S48) is performed.
The power restoration process (S48) is performed by the CPUs 43a, 44a, and 45.
a, 46a, the RAM 43 backed up
c, 44c, 45c, and 46c, and reads out the contents stored in the RAMs 43c, 44c, 45c, and 46c.
When the power is cut off by the administrator or against the will based on the contents stored in the pachinko machine, the state of the pachinko machine 2 is restored to the state before the power was cut off. For example, in the case of the symbol display substrate 44, the main substrate 4
If the command from 1 is stored in the RAM 44c,
According to the command, the special symbol display device 8 displays the symbol. Therefore, if, for example, "10,000", "10,000", "10,000" are displayed on the special symbol display device 8,
After the power is turned on again, the symbols "10,000", "10,000", and "10,000" are displayed again on the special symbol display device 8. Also,
In the case of the payout control board 45, if the number of payout balls to be paid out is stored in the RAM 45c, the payout of payout balls is performed based on the storage.

On the other hand, if the RAM clear command is received within a predetermined time (S40: YES), the backup R
The process of AM clear (S42) is performed, and an initial screen is displayed on the special symbol display device 8. Dispensing control board 4
If it is 5, even if there is a prize ball to be paid out before the power is turned off, it will not be paid out. Note that the sound board 43 and the illumination board 46 are similarly controlled.

Power recovery processing (S48) or backup RA
When the procedure of M clear (S42) is completed, the sound board 43,
Returning to the respective routines of the symbol display board 44, the payout control board 45, and the illuminated board 46, the normal processing (S50) not shown in detail is continued. Note that normal processing (S5
In 0), the backup RAM is cleared (S42).
Is the RAM check in FIG. 7 normal? Similar to the determination of (S3), the same determination as the determination that the RAM check is not normal (S3: NO) is made. The same initial settings are made.

As described above, the pachinko machine 2 according to the second embodiment of the present embodiment has the above-described configuration and operation, and has the following effects. That is, when the erase switch 42s is pressed, the RAM 41c is a volatile memory that is backed up by a backup power supply provided on the power supply board 42 that is a backup means.
Using the CPU 41a of the main board 41 on which is disposed, the contents of the RAM 41c disposed on the main board 41 are softly erased in accordance with a signal resulting from the operation of the erase switch 42s as the erase switch means, and the main board 41 is erased. 41 CP
U41a is a CPU 43 of a sound board 43, a symbol display board 44, a payout control board 45, and an illumination board 46, which are sub-boards.
a, 44a, 45a, and 46a are RAMs that are predetermined signals.
CPU 43a, 44a, 45 sends a clear command.
a, 46a, a RAM 43 disposed on the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46.
There is an effect that the contents of c, 44c, 45c, and 46c can be erased by software.

Although the embodiments of the present invention have been described with reference to the first and second embodiments, it is needless to say that the present invention is not limited to the above embodiments. For example, one that backs up only a part of the sub-boards, or one that backs up only the main board without backing up the sub-boards, or that backs up only this main board that is composed only of the main board without the sub-boards It can be applied to a game machine.

FIG. 12 is a diagram showing a configuration in which only the main board 41 and the payout control board 45 are backed up by the backup power supply provided in the power board 42 in the pachinko machine 1 of the first embodiment. As shown in FIG. 12, the main board 41
The power supply line 84a is connected to the RAM 4 of the main board 41.
1c is supplied with backup power. A power supply line 84d is connected from the backup power supply of the power supply board 42 to the payout control board 45, and the RAM of the payout control board 45
A backup power is supplied to 45c. Here, in FIGS. 5 and 6, the power supply lines 82a to 82e connect DC + 1 including a backup power supply as shown in FIG.
A power supply of a voltage corresponding to each application such as 2 V and DC + 5 V is supplied to each substrate.
Power supply lines 84a and 84d in FIG. 12 only show connection to a backup power supply for the sake of explanation. Therefore, the sound board 43, the symbol display board 44, and the illuminated board 46
Other DC + 12V, DC + 5 except power supply for backup
A power supply line (not shown) for supplying V power is connected to the power supply board 42.

On the other hand, the erase switch 42s of the power supply board 42
The signal line 85a is connected to the CPU 41a via the I / O interface 41d of the main board 41. Similarly, the erase switch 42s of the power supply board 42 is connected to the signal line 85a.
Through the I / O interface 41d of the main board 41,
Connected to PU 41a. Accordingly, the CPUs 43a, 44a, and 4 of the sound board 43, the symbol display board 44, and the illumination board 46.
6a is not connected to the erase switch 42s.

In the configuration shown in FIG.
Only the M41c and the RAM 45c of the payout control board 45 are backed up, and the CPU 41a of the main board 41 and the CP of the payout control board 45 are pressed by pressing the erase switch 42s.
By U45a, the stored contents of the RAM 41c of the main board 41 and the RAM 45c of the payout control board 45 are erased in a software manner. On the other hand, the sound board 43, the symbol display board 44, and the illuminated board 46 have the RAMs 43c, 44c, 46 while the main power of DC + 12V and DC + 5V are supplied.
c is retained, but the DC + 12
When the power supply of V and DC + 5V is not supplied, the RAM 4
The stored contents of 3c, 44c and 46c are deleted.

Therefore, if the gaming machine has a configuration as shown in FIG. 12, a flag (not shown) indicating a special gaming state.
The storage of the RAM 41c of the main board 41 and the RAM 45c of the payout control board 45, which store the storage contents that greatly affect the player's profit such as the payout of award balls, can be backed up and held, and can be erased. The configuration of the gaming machine can be simplified by not backing up the sound board 43, the symbol display board 44, and the illuminated board 46 that have little effect on the profit of the player.

Next, FIG. 13 shows the pachinko machine 2 of the second embodiment.
5 is a diagram showing a configuration in which only a main board 41 and a payout control board 45 are backed up by a backup power supply provided in a power supply board 42 in FIG. As shown in FIG.
A power supply line 86a is connected from the backup power supply of the power supply board 42 to the main board 41, and the RAM 41c of the main board 41 is connected.
Is supplied with backup power. The power supply board 4
A power supply line 86d is connected from the backup power supply to the payout control board 45, and the RAM 45 of the payout control board 45 is connected to the power supply line 86d.
The power for backup is supplied to c. In addition, similarly to FIG. 12, in FIG. 5 and FIG.
2e is a D including a backup power source as shown in FIG.
A power supply of a voltage according to each application such as C + 12 V, DC + 5 V, etc. is supplied to each substrate. The power supply lines 86a and 86d are
For the sake of explanation, only the connection with the backup power supply is shown. Accordingly, the sound board 43, the symbol display board 44, and the illuminated board 46 have a DC + 12V other than the backup power supply.
The power supply circuit 42 is connected to a power supply board 42 via a power supply line (not shown) for supplying power of DC + 5V.

On the other hand, the erase switch 42s of the power supply board 42
The signal line 87a is connected to the CPU 41a via the I / O interface 41d of the main board 41. Unlike FIG. 12, the signal line 87d is connected from the CPU 41a of the main board 41 via the I / O interface 41d, and the signal line 87d is connected to the CPU 45a via the I / O interface 45d of the payout control board 45. You. Accordingly, the CPU 4 of the sound board 43, the symbol display board 44, and the illumination board 46
3a, 44a and 46a are not connected to either the erase switch 42s or the CPU 41a of the main board 41.

In the configuration shown in FIG.
Only the M41c and the RAM 45c of the payout control board 45 are backed up, and when the erase switch 42s is pressed, the CPU 41a of the main board 41
While the stored contents of M41c are erased, the main board 41
CPU 41a includes an I / O interface 41d, a signal line 87d, and an I / O interface 4 of the payout control board 45.
A RAM clear command (see FIG. 10) is transmitted to the CPU 45a of the payout control board 45 via 5d, and the CPU 45a of the payout control board 45 erases the contents of the RAM 45c by software. On the other hand, a sound board 43, a symbol display board 44,
The illumination board 46 is a DC + 12V, DC
While the power of +5 V is supplied, the RAMs 43c and 44
c and 46c are retained, but the main power supply D
If power supply of C + 12V and DC + 5V is not supplied,
The contents stored in the RAMs 43c, 44c and 46c are deleted.

Therefore, in the gaming machine having such a configuration, the main board 41 which stores a flag (not shown) indicating a special gaming state and storage contents which greatly affect the player's profit such as payout of award balls. RAM 41c and payout control board 45
Of the RAM 45c can be backed up and held,
The sound board 43, the symbol display board 44, and the illuminated board 46, which can be erased and have relatively little effect on the profit of the player, are not backed up, so that the configuration of the gaming machine can be simplified.

Next, FIG. 14 shows that in the pachinko machine 1 of the first embodiment, only the main board 41 and the payout control board 45 are backed up by the backup power supply provided on the power board 42, and the erase switch 41s is set to the main board 41. FIG. As shown in FIG.
Power supply line 88 from the backup power supply to the main board 41
a is connected, and backup power is supplied to the RAM 41 c of the main board 41. A power supply line 88d is connected from the backup power supply of the power supply board 42 to the payout control board 45, and the backup power is supplied to the RAM 45c of the payout control board 45. Here, in FIGS. 5 and 6, DC + 12V and DC + 5V including a backup power supply as shown in FIG.
And the like. A power supply having a voltage corresponding to each use such as is supplied to each substrate.
Although illustrated as 2a to 82e, the power supply lines 88a and 88d in FIG. 12 only show connection to a backup power supply for the sake of explanation. Therefore, the sound board 43,
The symbol display board 44 and the illuminated board 46 are connected to the power supply board 42 by a power supply line (not shown) that supplies power of DC +12 V and DC +5 V other than the backup power supply.

On the other hand, the erase switch 41 s is
When the erase switch 41s is operated by receiving power from a power supply line (not shown) of the main board 41, a predetermined signal is transmitted. The erase switch 41s is connected to the CPU via the I / O interface 41d of the main board 41
41a. The erase switch 41s is connected to the CPU 45a via the I / O interface 45d of the payout control board 45 via the signal line 89d. Therefore, the sound substrate 43, the symbol display substrate 44, and the C
The PUs 43a, 44a and 46a are not connected to the erase switch 41s arranged on the main board 41.

In the configuration shown in FIG.
Only the M41c and the RAM 45c of the payout control board 45 are backed up, and the CPU 41a of the main board 41 and the CP of the payout control board 45 are
By U45a, the stored contents of the RAM 41c of the main board 41 and the RAM 45c of the payout control board 45 are erased in a software manner. On the other hand, the sound board 43, the symbol display board 44, and the illuminated board 46 have the RAMs 43c, 44c, 46 while the main power of DC + 12V and DC + 5V are supplied.
c is retained, but the DC + 12
When the power supply of V and DC + 5V is not supplied, the RAM 4
The stored contents of 3c, 44c and 46c are deleted.

Therefore, if the gaming machine has a configuration as shown in FIG. 14, a flag (not shown) indicating a special gaming state.
The storage of the RAM 41c of the main board 41 and the RAM 45c of the payout control board 45, which store the storage contents that greatly affect the player's profit such as the payout of award balls, can be backed up and held, and can be erased. The configuration of the gaming machine can be simplified by not backing up the sound board 43, the symbol display board 44, and the illuminated board 46 that have little effect on the profit of the player. Further, by disposing the switch 41 s on the main board 41, the switch 41 s
The signal line for connecting to one I / O interface can be shortened, and the signal attenuation can be reduced.

Although not shown, a backup means which does not include a sub-board, supplies backup power to the RAM 41c of the main board 41 from a backup power supply provided on the power supply board 42, and backs up only the RAM 41c, A pachinko machine having an erase switch 42s operated to erase the contents of the RAM 41c, wherein the RAM 41c is backed up and the erase switch 42s is pressed to erase only the stored contents of the RAM 41c. Can also. Then, the power supply board 42 and the main board 41 may be integrally formed.

The gaming machine has been described as an example of a type 1 pachinko machine, but not only a type 1 pachinko machine but also a pachinko machine of each type, such as a slot machine, a pachinko machine, a pachislot machine, and not limited thereto It goes without saying that the present invention can be applied to various types of gaming machines controlled by the main board.

Further, it is easily presumed that those skilled in the art can implement the present invention with various modifications and improvements without departing from the scope of the claims.

[0113]

As described above, in the gaming machine according to the first aspect of the present invention, backup power can be supplied to the volatile memory of the main board by the backup means so that the contents of the volatile memory are not erased. Therefore, even when the supply of the power supply current to the main board is undesirably cut off,
When the supply of power is restored, the game can be continued so as not to be disadvantageous for the player. In addition, when the erase switch means is operated, the contents of the volatile memory backed up by the backup means can be erased when the erase switch means is operated, so that when playing a new game, it is unfair to the player. There is an effect that it is possible to easily return to the initial state so as not to be out of order.

In the gaming machine according to the second aspect of the present invention, backup power can be supplied to the volatile memories of the main board and the sub-board by the backup means so that the contents of the volatile memories are not erased. Even when the supply of the power supply current to the main board and the sub-board is cut off, the game can be continued so as not to be disadvantageous for the player when the supply of the power supply is restored. In particular, since the backup is performed even on the sub-board, the state before the supply of the power supply current is cut off can be restored more reproducibly. In addition, when the erase switch means is operated, the contents of the volatile memory backed up by the backup means can be erased when the erase switch means is operated, so that when playing a new game, it is unfair to the player. There is an effect that it is possible to easily return to the initial state so as not to be out of order.

The gaming machine according to the third aspect of the present invention provides the gaming machine according to the second aspect.
In addition to the effects of the gaming machine described in the above, when the erase switch means is operated, the C of the main board or the sub-board on which the volatile memory backed up by the backup means is arranged
Using the PU, there is an effect that the contents of the volatile memory can be erased for each substrate according to the signal resulting from the operation of the erase switch means. Therefore, there is an effect that the contents of the volatile memories on the main substrate and the sub substrate can be erased by one erase switch.

The gaming machine according to the fourth aspect of the present invention provides the gaming machine according to the second aspect.
In addition to the effects of the gaming machine described in the above, when the erase switch means is operated, using the CPU of the main board on which the volatile memory backed up by the backup means is arranged,
In response to a signal resulting from the operation of the erase switch means, the contents of the volatile memory arranged on the main board are erased, and the CPU of the main board sends a predetermined signal to the CPU of the sub-board, Accordingly, there is an effect that the contents of the volatile memory arranged on the sub-board can be erased.

The gaming machine according to the fifth aspect of the present invention provides the gaming machine according to the first aspect.
In addition to the effects of the gaming machine according to any one of claims 4 to 4,
When the main power of the gaming machine is turned on while the erase switch means is operated, to erase the contents of the volatile memory,
There is an effect that the contents of the volatile memory can be easily erased by arbitrarily operating the erase switch means only when the contents of the volatile memory are to be erased.

The gaming machine according to the sixth aspect of the present invention provides the gaming machine according to the first aspect.
In addition to the effects of the gaming machine according to any one of claims 5 to 5,
When the operation of the erase switch is detected during a predetermined time period after the main power of the gaming machine is turned on, the operation of the erase switch is detected for a certain period of time to erase the contents of the volatile memory when the operation of the erase switch is detected. In addition to preventing erroneous operation, the contents of the volatile memory are not erased even if the erase switch is operated after a predetermined time has elapsed.

[0119] The gaming machine of the invention according to claim 7 is characterized by claim 1.
In addition to the effects of the gaming machine according to any one of claims 6 to 6,
The volatile memory is integrally formed with the CPU and the non-volatile memory of the substrate on which the volatile memory is arranged,
Since the main memory is configured as a part of the one-chip microcomputer having the backup power supply terminal of the volatile memory, the structure of the substrate can be simplified.

[0120] The gaming machine according to the eighth aspect of the present invention provides the gaming machine according to the first aspect.
In addition to the effects of the gaming machine according to any one of claims 7 to 7,
Since the erase switch means is arranged on the power supply substrate, there is an effect that the erase switch means can be easily supplied with power from the power supply substrate.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko machine 1. FIG.

FIG. 2 is a front view of the game board 2 of the pachinko machine 1.

FIG. 3 is a front view of the special symbol display device 8;

FIG. 4 is a block diagram showing an electric circuit configuration of the pachinko machine 1;

FIG. 5 shows a main board 41 and a power supply board 4 in the pachinko machine 1;
2, sound board 43, symbol display board 44, payout control board 4
FIG. 5 is a diagram for explaining the supply of a power supply current between the illuminated substrates 46 and the flow of signals.

FIG. 6 shows a main board 41 and a power supply board 4 in the pachinko machine 2;
2, sound board 43, symbol display board 44, payout control board 4
FIG. 5 is a diagram for explaining the supply of a power supply current between the illuminated substrates 46 and the flow of signals.

FIG. 7 is a flowchart showing a main routine of the pachinko machine 1.

FIG. 8 is a flowchart showing a power-on process (S
It is a flowchart which shows the procedure of 1) in detail.

9 is a flowchart showing another processing method of the power-on processing (FIG. 7: S1).

10 is a flowchart showing in detail a procedure of a power-on process (S1) of the flowchart shown in FIG. 7 for the main board 41 in the pachinko machine 2. FIG.

FIG. 11 shows the sound board 43 and the symbol display board 4 of the pachinko machine 2
4 is a flowchart showing a procedure of processing in a payout control board 45 and an illuminated board 46.

FIG. 12 shows a power supply board 4 in the pachinko machine 1 according to the first embodiment.
The main board 41 is provided by the backup power supply provided in
FIG. 9 is a diagram showing a configuration for backing up only the payout control board 45.

FIG. 13 shows a power supply board 4 in the pachinko machine 2 of the second embodiment.
The main board 41 is provided by the backup power supply provided in
FIG. 9 is a diagram showing a configuration for backing up only the payout control board 45.

FIG. 14 is a diagram illustrating a main board 4 of the pachinko machine 1 according to the first embodiment, which is provided by a backup power supply provided on a power board 42;
FIG. 11 is a diagram showing a configuration in which only 1 and the payout control board 45 are backed up and an erase switch 41s is provided on the main board 41.

[Explanation of symbols]

1 pachinko machine 2 game board 4 game area 8 special symbol display device 41 main board 42 power supply board 43 sound board 44 symbol display board 45 payout control board 46 electric decoration boards 41a, 43a, 44a, 45a, 46a CPU 41b, 43b, 44b , 45b, 46b ROM 41c, 43c, 44c, 45c, 46c RAM 41d, 43d, 44d, 45d, 46d I / O interface 42s Erase switch 77, 78, 79a, 79b, 79c, 79d, 79
e, 83a, 83b, 83c, 83d, 83e Signal line 80 Power switch 82a, 82b, 82c, 82d, 82e Power supply line

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 3, 2000 (2007.3)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention] Gaming machine

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine, and more particularly, to backing up a volatile memory arranged on a main board or a main board and a sub-board for controlling the gaming machine, and an erase switch. By manipulating the means,
The present invention relates to a gaming machine provided with erasure control means for controlling the contents of a backed-up volatile memory to be erased by software.

[0002]

2. Description of the Related Art Conventionally, in a gaming machine such as a pachinko machine, for example, a main board for controlling the gaming machine is provided, and the main board is used to control a symbol display device of the gaming machine, control a lighting mode of an electric decoration, Control of sound generation and control of payout of game balls were performed. However, in recent years, the control of the gaming machine has become complicated, and if only the main board is used, the burden on the main board is increased. In addition to the main board that controls the gaming machine, a symbol display device is provided to assist in controlling the main board. A sub-board consisting of a symbol display board for controlling the game, a payout control board for controlling the payout of the game balls, an illumination board for controlling the light emission mode of the illumination of the gaming machine, a sound board for controlling the sound generation of the gaming machine, and the like. There was a gaming machine provided independently of the main board. In a gaming machine provided with such a sub-board, a gaming machine capable of performing complicated control without imposing an excessive load on the main board could be obtained.
In such a conventional gaming machine in which such a main board and other sub-boards are separately provided, when power supply to some or all of the boards is undesirably cut off for some reason, the power supply is turned off. If there is already a jackpot before the supply is cut off or a prize ball has been paid out, the jackpot state will be released when the power is turned on again or the prize ball will not be paid out, so it is disadvantageous for the player In some cases, inconveniences such as a state may occur. Therefore, it is conceivable to provide backup means for memories of the main board and the sub-board so that the stored contents of the control means can be preserved even when the supply of the power supply current to the board is cut off.

[0003]

However, if a backup means is provided so that the stored contents of the memory can be retained even when the supply of the power supply current to the substrate is cut off,
For example, when the main power is turned off in the state of a jackpot, when the main power is turned on to perform a new game next, the game is started from a state of a jackpot or the like, which is unfair to the player. There was a problem.

In order to solve the above-mentioned problems, the present invention provides a disadvantage to a player when the supply of power is restored even when the supply of power to a part or all of the substrates is undesirably cut off. It is an object of the present invention to provide a gaming machine that can continue the game so as not to become unreliable, and can easily return to an initial state so as not to be unfair to a player when playing a new game. .

[0005]

According to a first aspect of the present invention, there is provided a gaming machine comprising: a main board for controlling the gaming machine; and a power supply board for supplying power to the main board. A gaming machine provided with backup means for supplying backup power to the volatile memory of the main board to back up the contents of the volatile memory so that the contents of the volatile memory are not erased; and Erase switch means operated to erase the contents of the memory; and erase control for controlling the contents of the volatile memory backed up by the backup means to be erased when the erase switch means is operated. Means are provided.

In the gaming machine having this structure, the backup means supplies backup power to the volatile memory of the main board so that the volatile memory can be backed up so that the contents of the volatile memory are not erased. Even when the supply of power is interrupted, the game can be continued so as not to be disadvantageous for the player when the supply of power is restored. Also provided is an erase switch means and an erase control means,
When the erase switch means is operated, the contents of the volatile memory backed up by the backup means can be erased, so that when playing a new game, it is easy to return to the initial state so as not to be unfair to the player. Can be.

In the gaming machine according to the second aspect of the present invention, a main board for controlling the gaming machine and a control board for controlling the main board are provided.
A gaming machine in which the above-described sub-board and a power supply board for supplying power to the main board and the sub-board are provided independently of each other, wherein at least one of the main board and the sub-board is provided. Backup means for supplying backup power to the volatile memory to back up the volatile memory so that the contents of the volatile memory are not erased, and erasure operated to erase the contents of the volatile memory backed up by the backup means A switch means and an erasure control means for controlling the contents of the volatile memory backed up by the backup means to be erased when the erasure switch means is operated.

In the gaming machine having this structure, the backup means supplies backup power to the volatile memories of the main board and the sub-board so that the contents of the volatile memory can be backed up without being erased. Even when the supply of power supply current to the sub-board is cut off, when the supply of power is restored, the game can be continued so as not to be disadvantageous for the player. In particular, since the backup is performed even on the sub-board, the state before the supply of the power supply current is cut off can be restored more reproducibly. In addition, when the erase switch means is operated, the contents of the volatile memory backed up by the backup means can be erased when the erase switch means is operated. It is possible to easily return to the initial state so as not to go out.

According to a third aspect of the present invention, in addition to the configuration of the second aspect of the present invention, the erase control means further comprises:
When the erase switch is operated, a signal resulting from the operation of the erase switch is obtained by using the CPU of the main board or the sub-board on which the volatile memory backed up by the backup is arranged. Accordingly, control is performed such that the contents of the volatile memory are erased for each substrate.

In the gaming machine having this structure, in addition to the function of the gaming machine according to the second aspect, when the erase switch is operated, the main board or the sub board on which the volatile memory backed up by the backup is arranged. Using the CPU of the substrate, the contents of the volatile memory can be erased for each substrate in response to a signal resulting from the operation of the erase switch means. The contents of the memory can be erased.

According to a fourth aspect of the present invention, in addition to the configuration of the second aspect of the gaming machine, the erasure control means includes:
When the erase switch is operated, the CPU of the main board on which the volatile memory backed up by the backup is arranged is used, and the main switch is operated in accordance with a signal resulting from the operation of the erase switch. While erasing the contents of the volatile memory arranged on the board, the CPU of the main board sends a predetermined signal to the CPU of the sub-board, and the CPU of the sub-board makes the CPU of the sub-board dispose the volatile memory arranged on the sub-board. The control is performed such that the contents of the memory are erased.

In the gaming machine having this configuration, in addition to the function of the gaming machine according to the second aspect, when the erase switch is operated, the CPU of the main board on which the volatile memory backed up by the backup is arranged. And erases the contents of the volatile memory arranged on the main board according to a signal resulting from the operation of the erase switch means, and the CPU on the main board sends a predetermined signal to the CPU on the sub-board, The contents of the volatile memory arranged on the sub-board can be erased by the CPU of the board.

In the gaming machine according to a fifth aspect of the present invention, in addition to the configuration of the gaming machine according to any one of the first to fourth aspects, the erasing control means is configured to operate the erasing switch means while operating the erasing switch means. When the main power of the device is turned on, control is performed such that the contents of the volatile memory are erased.

In the gaming machine having this configuration, in addition to the operation of the gaming machine according to any one of claims 1 to 4, when the main power of the gaming machine is turned on while the erase switch is operated, the volatilization is performed. Since the contents of the volatile memory are erased, the contents of the volatile memory can be easily erased by arbitrarily operating the erase switch means only when the contents of the volatile memory are to be erased.

In the game machine according to a sixth aspect of the present invention, in addition to the structure of the game machine according to any one of the first to fifth aspects, the erasing control means includes a main power supply of the game machine which is turned on. When the operation of the erase switch means is detected until a predetermined time has elapsed since the start of the operation, the content of the volatile memory is controlled to be erased.

In the gaming machine having this configuration, in addition to the operation of the gaming machine according to any one of the first to fifth aspects, it is also possible to provide the gaming machine with a predetermined time after the main power of the gaming machine is turned on. In order to erase the contents of the volatile memory when the operation of the erase switch means is detected, the operation of the erase switch means is detected for a certain period of time to prevent malfunction, and after a predetermined time has elapsed, the erase switch means is operated. However, the contents of the volatile memory are not erased.

According to a seventh aspect of the present invention, in addition to the configuration of the gaming machine according to any one of the first to sixth aspects, the volatile memory includes a substrate on which the volatile memory is disposed. It is characterized by being a main storage unit integrally formed with a CPU, a nonvolatile memory, and the like, and configured as a part of a one-chip microcomputer having a backup power supply terminal for the volatile memory.

In the gaming machine having this configuration, in addition to the function of the gaming machine according to any one of claims 1 to 6, the volatile memory includes a CPU and a non-volatile memory of a substrate on which the volatile memory is disposed. Since it is a main storage device that is integrally formed with the like and is configured as a part of a one-chip microcomputer having a backup power supply terminal for the volatile memory,
The structure of the substrate can be made simpler.

According to an eighth aspect of the present invention, in addition to the configuration of the gaming machine according to any one of the first to seventh aspects, the erase switch means is arranged on the power supply board. And

In the gaming machine having this structure, in addition to the function of the gaming machine according to any one of the first to seventh aspects, the erase switch means is arranged on the power supply board, so that the power is supplied to the erase switch means from the power supply board. Easy.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below by way of examples with reference to the drawings.

(Embodiment 1) A pachinko machine 1 according to Embodiment 1 of the present invention will be described with reference to the drawings. First, the mechanical configuration of the pachinko machine 1 will be described. FIG. 1 is a front view of the pachinko machine 1. As shown in FIG. 1, a substantially square game board 2 is provided in an upper half portion of the front of the pachinko machine 1, and a substantially circular game area 4 surrounded by a guide rail 3 is provided on the game board 2. Is provided. A lower plate of the game board 2 of the pachinko machine 1 is provided with an upper plate 5 for supplying a game ball to a launcher (not shown) and receiving a prize ball. A lower plate 6 for receiving an overflowing prize ball is provided, and a firing handle 7 is provided on the right side of the lower plate 6.

Next, the mechanical structure of the game board 2 is shown in FIG.
This will be described with reference to FIG. FIG. 2 is a front view of the game board 2 of the pachinko machine 1. The game board 2 has a substantially circular game area 4 surrounded by a guide rail 3, and a special symbol display device 8 having a liquid crystal screen is provided at substantially the center of the game area 4. In addition, an illuminated windmill 9 is provided on the upper right of the special symbol display device 8, and an illuminated windmill 10 is also provided on the upper left. Further, a normal symbol start gate 11 is provided on the right side of the special symbol display device 8, and an ordinary symbol start gate 12 is provided on the left side.

A special symbol starting electric accessory 15 is provided directly below the special symbol display device 8, and a special winning opening 16 is provided below the special symbol starting electric accessory 15. A winning opening 30 and a winning opening 31 are provided on the left and right of the special winning opening 16.

A winning opening 19 is provided below the ordinary symbol starting gate 11, and a winning opening 20 is provided below the ordinary symbol starting gate 12. Further, a stage 21 on which game balls can be temporarily mounted is horizontally provided below the special symbol display device 8. A game ball passage opening 22 is provided on the right shoulder of the special symbol display device 8, and a game ball passage opening 23 is also provided on the left shoulder of the special symbol display device 8. The game balls passing through these game ball passage openings 22 and 23 appear on the stage 21 through the inside (warp zone) of the special symbol display device 8. The game ball appearing on the stage 21 falls toward the special symbol starting electric accessory 15 provided immediately below the stage 21.

Above the special symbol display device 8, a normal symbol display device 24 is provided so that a symbol such as a single digit or a single alphabet can be displayed. Further, a special symbol starting reservation unit 25 composed of two LEDs is provided on each of the right and left sides of the ordinary symbol display device 24 to display the number of so-called reserved balls that have won the special symbol starting electric accessory 15. Can be. Also, between the special symbol display device 8 and the ordinary symbol display device 24, 4
There is provided a normal symbol start reservation unit 26 composed of a plurality of LEDs, and this normal symbol start reservation unit 26 can display the so-called reserved ball number of game balls that have passed the normal symbol start gates 11 and 12. In addition, in addition to the above, an out port, various illumination lamps, a windmill, a large number of obstacle nails, and the like are arranged at predetermined positions on the game board 2.

Next, the structure and display screen of the special symbol display device 8 will be described with reference to FIG. FIG. 3 is a front view of the special symbol display device 8. As shown in FIG. 3, on the liquid crystal screen of the special symbol display device 8, three special symbols of a first stop symbol L1, a second stop symbol L2, and a third stop symbol L3 can be displayed side by side in a horizontal direction. ing. In addition, the special symbol display device 8 performs the above-described first stop symbol L1 and second stop symbol L
2. In addition to displaying the third stop symbol L3, a moving image, a message, and the like can be displayed. The special symbols may be displayed not only horizontally but also vertically or diagonally. The special symbol display device 8 uses not only a liquid crystal display device but also a CR
It goes without saying that various display devices such as T, LED, and plasma display can be used. The special symbol display device 8 includes a symbol control board 44 (see FIG. 4) on the back surface.

The first stop symbol L1 and the second stop symbol L
2. Examples of the symbols displayed on the third stop symbol L3 include "10,000", "20,000", "30,000", which imitate a mahjong tile.
"Shiman", "50,000", "60,000", "70,000", "80,000"
"Kuman", "white solid" (hereinafter "white"),
There are twelve kinds of "Hatsu" and "Medium", and the game ball wins the special symbol starting electric accessory 15, and the three symbols of the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3 are displayed. In the case where the same number, character or pattern are arranged (for example, three "Seven thousand" shown in FIG. 3 are arranged), or in the case where a specific number, character or pattern is combined, etc. A jackpot.

Of the twelve symbols, "Sanma", "Five thousand", "Seven thousand", "White", "Hatsu", and "Medium" are probability variation symbols (specific jackpot symbols). If any of the symbols is the same as the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3, the probability change is entered, and the probability of drawing the next big hit is increased. change. The probability of a jackpot is, for example, in the normal state,
317.6 times, and 68.1 in the probability fluctuation state.
It is 1 / min, but is not necessarily limited to this value. In addition, "10,000", "20,000", "40,000", "60,000"
"Yama" and "Kuma" are non-stochastic fluctuation symbols (non-specific jackpot symbols or normal symbols).

Next, an electric circuit configuration of the pachinko machine 1 of the present embodiment will be described with reference to FIG. FIG.
FIG. 2 is a block diagram illustrating an electric circuit configuration of the pachinko machine 1. The control unit of the pachinko machine 1 includes a main board 41, a power board 4
2, sound board 43, symbol display board 44, payout control board 4
5, an illumination board 46, and a launch board 47. The main board 41 includes a power board 42, a sound board 43, and a symbol display board 4.
4. The payout control board 45, the illuminated board 46, and the firing board 47 are connected to each other.

FIG. 5 shows the main board 4 of the pachinko machine 1.
1. supply of a power supply current between the power supply board 42, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46;
FIG. 4 is a diagram illustrating a signal flow. As shown in FIG. 5, the main board 41 includes a CPU 41a, a ROM 41b, and a RAM 41.
c, an I / O interface 41d, a reset circuit 17, and the like are connected to each other by a bus line 41e and provided.
On the power supply board 42, an erase switch 42s is provided.
CPU 43a, ROM 43b, RAM 4
3c, I / O interface 43d, etc.
and are connected to each other by e. Similarly, the CPU 44a, the ROM 44b, the RAM 4
4c, the I / O interface 44d, etc.
e, connected to each other, and provided to the payout control board 45.
CPU 45a, ROM 45b, RAM 45c, I /
The O interface 45d and the like are connected to each other by a bus line 45e and provided.
a, a ROM 46b, a RAM 46c, an I / O interface 46d, etc., are connected to each other by a bus line 46e. In addition, a connection line connected to the power supply board 42 has an AC24 supplied from a power supply source (not shown).
A power switch 80 capable of supplying or interrupting V power current is provided.

From the power supply board 42, a power supply line 82a is connected to the main board 41, a power supply line 82b is connected to the sound board 43, and a power supply line 82 is connected to the symbol display board 44.
is connected, the power supply line 82d is connected to the payout control board 45, the power supply line 82e is connected to the illuminated board 46, and the power supply current is connected to each board. The power supply line 8
For 2a to 82e, as shown in FIG. 4, power supply lines for supplying power of a voltage corresponding to each application such as DC + 12V and DC + 5V including a backup power supply to each substrate are separately provided. Is omitted for simplicity of description.

Erase switch 4 provided on power supply board 42
2s is connected to the I / O interface 41d of the main board 41 by a signal line 79a, connected to the I / O interface 43d of the sound board 43 by a signal line 79b, and I / O of the symbol display board 44 by a signal line 79c. O interface 44d, and the payout control board 4 is connected by a signal line 79d.
5 is connected to the I / O interface 45d of
9e, the I / O interface 46d of the illuminated board 46
It is connected to the.

The erase switch 42s is a push button switch, for example, and is configured to close the circuit only when the switch is pressed. When the erase switch 42s is pressed, a signal of a predetermined voltage is transmitted to the main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46 by the power supply current supplied from the power supply board 42. Be composed. The main board 41, the sound board 43, and the design display board 4
4. The circuit may be configured such that the supply current is supplied from all or a part of the payout control board 45 and the illuminated board 46, and the circuit is opened and closed by the erase switch 42s. Note that the wiring may be wired in a star shape or a loop shape.

When the erase switch 42s is opened and closed in this manner, for example, a signal sent from the erase switch 42s via the signal line 79a connected to the main board 41 is transmitted from the I / O interface 41d to the CPU via the bus line 41e.
41a, and the CPU 41a of the main board 41
It acknowledges that the erase switch 42s is ON. Similarly, a signal transmitted by the erase switch 42s via the signal line 79b connected to the sound board 43 is transmitted from the I / O interface 43d to the CP via the bus line 43e.
CPU 43a of the sound board 43 received by the U43a
Acknowledges that the erase switch 42s is ON, and the signal transmitted by the erase switch 42s through the signal line 79c connected to the symbol display board 44 is transmitted from the I / O interface 44d through the bus line 44e. CPU
CPU 44 of the symbol display board 44
a recognizes that the erase switch 42s is ON, and sends a signal transmitted by the erase switch 42s via the signal line 79d connected to the payout control board 45 from the I / O interface 45d to the bus line 45e. Via CP
The CPU 4 of the payout control board 45 received by the U45a
5a recognizes that the erase switch 42s is ON, and the signal transmitted by the erase switch 42s through the signal line 79e connected to the electric decoration board 46 transmits the signal from the I / O interface 46d to the bus line 46e. Via CPU
CPU 46a of the illumination board 46
Acknowledges that the erase switch 42s is ON.

Returning to FIG. 4, the main board 41 has a winning opening switch 32 provided at each of the winning openings 19, 20, 30, 31 (see FIG. 2), and a special symbol start-up. A starting port switch 33 for detecting a winning of a game ball to the electric accessory 15 and a gate switch 3 for detecting passing of the game ball to the normal symbol starting gates 11 and 12 (see FIG. 2).
4, a count switch 35 for detecting the number of winning balls of the game balls to the special winning opening 16, and a V provided in the special winning opening 16.
A V-switch 36 for detecting a prize of a game ball to a zone (not shown), and a special symbol starting electric accessory solenoid 3 for opening and closing an opening / closing member of the special symbol starting electric accessory 15 (see FIG. 2).
7, a special winning opening solenoid 38 for opening and closing the special winning opening 16 (see FIG. 2), a guiding device solenoid 39, an external connection terminal 2 board 40 for outputting jackpot information of the gaming machine to an external device, and a 7 segment It is connected to a normal design board 60 which is composed of LEDs and displays a normal design.

The external connection terminal 2 board 40 is provided with a jackpot 1 information terminal, a jackpot 2 information terminal, and a symbol confirmation information terminal. It is possible to output the information of the symbol to be performed. A special symbol display device 8 is connected to the symbol display substrate 44, and a speaker 61 is connected to the sound substrate 43.
Is connected, and the illuminated board 46 is
2 is connected, and the game board 2
Each illumination lamp provided on the surface of is connected.

Further, on the main board 41, a lower plate full detection switch 6 for detecting that the lower plate 6 is full of game balls is provided.
3, a prize ball passage ball cut-out detection switch 64 for detecting a ball cut in a prize ball passage (not shown), and a prize ball payout confirmation switch 65 for checking the number of prize ball payouts from a prize ball device (not shown). Have been. The award ball payout confirmation switch 65 is also connected to the payout control board 45.

The payout control board 45 also has a ball lending passage ball out detection switch 66 for detecting a ball lending passage running out.
And a ball lending and payout confirmation switch 67 for checking the number of balls to be paid and paid out from a ball lending device (not shown), a prize ball payout solenoid 68 for driving a prize ball device (not shown), and a ball lending device (not shown). A ball lending and dispensing solenoid 69 to be driven and a prize ball device provided from a prize ball tank for storing a prize ball provided at the upper rear portion of the pachinko machine 1 are provided on a tank rail (not shown) for guiding game balls to the ball lending device. A tank rail vibration motor 70 for applying vibration to the tank rail to prevent clogging of game balls on the tank rail; a prepaid card unit 71 for reading lending data from the prepaid card;
The external connection terminal 1 and the substrate 72 are connected. The external connection terminal 1 board 72 is provided with a prize ball payout number information terminal and a ball rental payout number information terminal, and can output the prize ball payout number information and the ball rental payout number information to an external device.

Further, on the launch board 47, a launch ball jump strength adjustment volume 73 built in the launch handle 7 is provided.
, Launch device stop switch 74, touch sensor 75
And the launch motor 76 are connected.

Next, the power supply board 42 will be described. 24 V AC is input to the power supply board 42 via a power switch 80, and a DC 5 V, DC 12 V, DC 24 V, DC 3 V
2V can be output. The power supply board 42 can also output a reset signal, a backup power supply, a power failure detection signal, and 24 V AC. Further, in the power supply board 42, the DC 12V output is DC + 1
Three circuits of 2VA, DC + 12VB and DC + 12VC are prepared. DC + 12VA is connected to the main board 41, and DC + 12VB is connected to the main board 41 and the payout control board 45.
The DC + 12VC is connected to the special symbol display device 8, the sound board 43, and the illumination board 46. In addition, from the power supply board 42, 24V AC is input to the payout control board 45, and the backup power supply is a main board 41, a sound board 43, a symbol display board 44, a payout control board 45, an electric decoration board. 46.

The output of DC 24V is DC + 24V
A and DC + 24VB 2 circuits are prepared, DC + 24V
A is connected to the main board 41, and DC + 24VB is connected to the payout control board 45. Further, an output of DC 32 V is provided in one circuit of DC + 32 V, and is connected to the launch board 47. An output of DC 5V is provided in one circuit of DC + 5V, and is connected to the main board 41, the special symbol display device 8, the sound board 43, the payout control board 45, the illuminated board 46, and the emission board 47. Note that a firing device stop signal is input from the payout control board 45 to the firing board 47 via a signal line 77.

An erase switch 42 s is arranged on the power supply board 42, which is the erase switch 42 s in the first embodiment.
Since the power for transmitting the signal is supplied from the power supply board 42, the power supply is provided on the power supply board 42, and the erase switch 42s is not necessarily provided on the power supply board 42.
You do not need to place them. For example, a push button may be provided at a position separated from the power supply board 42 or operated by a key operation. In short, the position and form are not limited as long as a signal can be transmitted.

Next, referring to FIG. 5, the main board 41, the power supply board 42, the sound board 43, and the symbol display board 4 of the first embodiment.
4. The payout control board 45, the illuminated board 46, and the supply of the power supply current and the flow of signals between them will be described in detail. First,
The main board 41 includes a CPU 41a, a ROM 41b, a RAM
41c and a reset circuit 17 are provided.
The M41b stores a main control program executed by the CPU 41a for controlling the entire pachinko machine 1, data of initial values, and the like. Further, a program for erasing the stored contents of the backed-up RAM 41c in the present embodiment is also stored here. Therefore, C
The PU 41a constitutes the erasure control means of the present invention. The RAM 41c is a volatile memory for storing various data and the like. Even when the power supply from the power supply is cut off, the stored contents are retained for a long time.

The sound board 43 includes a CPU 43a, a ROM 4
3b, a RAM 43c, and the like are provided mutually connected to a bus line 43e. The ROM 43b stores audio data and the like, and stores various programs executed by the CPU 43a, data of initial values, and the like. Also,
Backed-up RAM 43c in the present embodiment
The program for erasing the stored contents of the above is also stored here. The RAM 43c is a volatile memory that stores various data and the like. Even when a normal power supply from the power supply board 42 to the sound board 43 is cut off by the backup power supply of the power supply board 42, the storage contents thereof are stored. Is held.

A CPU 44a, R
The OM 44b, the RAM 44c, and the like are provided so as to be mutually connected to the bus line 44e, and the ROM 44b stores various display data and CPUs displayed on the special symbol display device 8.
Various programs executed by 44a, data of initial values, and the like are stored. Further, a program for erasing the stored contents of the backed-up RAM 44c in the present embodiment is also stored here. Also, R
The AM 44c is a volatile memory for storing various data and the like. Even when the normal power supply from the power supply board 42 to the symbol display board 44 is cut off by the backup power supply of the power supply board 42, the stored contents are stored. It is to be retained. Note that the symbol display substrate 44 can be configured to include a plurality of CPUs in accordance with the recent increase in definition and speed of images.

CPU 45a, R
An OM 45b, a RAM 45c, and the like are provided so as to be mutually connected to a bus line 45e.
Various programs executed by the U45a, data of initial values, and the like are stored. Further, a program for erasing the stored contents of the RAM 45c backed up in the present embodiment is also stored here. Also,
The RAM 45c is a volatile memory that stores various data, for example, the number of winning prize balls, the number of prize balls to be paid out, and the like. The power supply board 42 to the payout control board 45 Even if the normal power supply is cut off, the stored contents are retained.

A CPU 46a, a ROM,
46b, a RAM 46c, and the like are provided mutually connected to a bus line 46e.
A program such as various illumination patterns executed by 6a and data of initial values are stored. Further, a program for erasing the stored contents of the RAM 46c backed up in the present embodiment is also stored here. The RAM 46 c is a volatile memory that temporarily stores various data, for example, an illumination pattern to be controlled at the time of a big hit, and is supplied from the power supply substrate 42 to the illumination decoration substrate 46 by a backup power supply of the power supply substrate 42. Even if the normal power supply is cut off, the stored contents are retained.

The backup power supply of the power supply board 42 is N
It is composed of a secondary battery such as an iCd battery, an electrolytic capacitor, or the like, and is a NiC which is a backup power supply when a current of 24 V AC which is a normal power supply current is input.
A secondary battery such as a d-battery, an electrolytic capacitor, and the like are configured to be charged. When the supply of power to the power supply board 42 is stopped, the current charged in a secondary battery such as a NiCd battery or an electrolytic capacitor is transferred to the RAM 41c of the main board 41, the RAM 43c of the sound board 43, and the symbol display board 44. RAM 44c, RAM 4 of the payout control board 45
5c, it can be supplied to the RAM 46c of the illuminated substrate 46 as a power source for storing and storing. Further, a power switch 80 is provided on the input side of the AC 24 V of the power supply board 42, and the supply of the AC 24 V to the power supply board 42 and the stop of the supply are enabled.

Further, in the main substrate 41 of this embodiment, C
PU41a, ROM41b, RAM41c are one chip
Formed as a modular 64-pin microcomputer
This microcomputer has a power supply terminal for backup.
The child V_BBIt has terminals. This V_BBTerminal is DC +
A current from a 5V backup power supply is input. this
In the microcomputer, V_BBIf there is no input to the terminal,
It is configured so that the main power of the So
Therefore, if the RAM 41c is soft as in the present embodiment,
If there is no means for erasing the contents stored in the RAM 41c
If you try to erase_BBThe cord connected to the terminal
Pull out the cable or provide a separate switch for disconnection
V from the backup power supply of the power supply board 42
_BBThe connection to the terminal must be physically disconnected.
However, in this case, the power supply of the main board 41 itself is turned off.
Inconvenience. Also, the sound board 4
3, symbol display board 44, payout control board 45, illumination board 4
6 also has the same configuration as the main substrate 41,
In the storage of these RAMs 43c, 44c, 45c, 46c
In order to erase the contents,
V from power supply for up _BBPhysically disconnects the connection to the terminal
Must. In the pachinko machine 1 of the first embodiment,
Without such complicated work, the main board 41, the sound board 43,
Of the symbol display board 44, the payout control board 45, and the illuminated board 46
Storage of RAMs 41c, 43c, 44c, 45c, 46c
The contents can be easily erased.

Next, the operation of the pachinko machine 1 according to the first embodiment will be described with reference to flowcharts shown in FIGS. 7 and 8, taking a main routine (main control) of control on the main board 41 as an example. FIG. 7 is a flowchart showing a main routine (main control) of the pachinko machine 1. FIG.
5 is a flowchart showing in detail a procedure of a power-on process (S1) of the flowchart shown in FIG.

In the main routine of the flowchart shown in FIG. 7, the reset circuit 17 shown in FIG. 5 is executed at fixed intervals (for example, 2 milliseconds, hereinafter referred to as "2 ms").
CPU of the main board 41 according to the reset signal
41a performs processing in order from the start, and performs the processing from the start to the end within 2 ms.
Therefore, every time the reset signal is input at intervals of 2 ms, the process is repeated from the start. The program for performing the processing of the flowchart shown in FIG.
1b. 7 to 11 and the following description, “step” in the flowchart is abbreviated as “S”.

First, the main routine of the pachinko machine 1 will be described with reference to FIG. First, when the power is turned on, a power-on process (S1) is executed.

Here, the procedure of the power-on process (S1) in the flowchart shown in FIG. 7 will be described in detail with reference to FIG. When the power is turned on from the power supply board 42 to the main board 41 (power ON), that is, when the power switch 80 of the power supply board 42 is turned on or the power failure state is recovered,
The CPU 41a of the main board 41 starts up, and the ROM 41a
The following procedure is performed in accordance with the control program read from. When the CPU 41a starts up, the erase switch 42s disposed on the power supply board 42 is turned on via the I / O interface 41d and the signal line 79a as shown in FIG.
It is determined whether or not the operation has been performed (S20). For example, if the signal from the erase switch 42s is equal to or higher than a predetermined HI level voltage, it is determined to be ON (S20: YES), and if it is lower than the predetermined level voltage, it is OFF. Judge (S20: N
O).

In the pachinko machine 1, when the power switch 80 is closed, the RAM 41c
When the power switch 80 is turned off, the main board 41 is supplied from the battery of the backup power supply via the power supply line 82a even when the power switch 80 is turned off. since the power supply current from the _{V BB} pin RAM41c one-chip microcomputer provided is input, the contents stored in the RAM41c is held as it is.

Here, in S20, the erase switch 42
s is not ON (S20: N
O), that is, when the erase switch 42s is not pressed, the power restoration process (S28) is performed. Power restoration processing (S2
8) a case where the CPU 41a reads out the contents stored in the backed-up RAM 41c, and based on the contents stored in the RAM 41c, the power supply is cut off by the administrator's will or against the will. Then, the state of the pachinko machine 1 is restored to the state before the power was turned off. Therefore, for example, even if a power failure due to an accident occurs during the game of the player, if the player is in a jackpot state before the power failure, RA is restored after the power is restored.
Since the big hit flag stored in M41c is on, the game can be continued in the big hit state again.

If the pachinko machine 1 has already performed the normal processing, the power restoration processing (S28)
The recovery process is not performed, and the process based on the contents stored in the RAM 41c is continued. When the power restoration process (S28) ends, the power-on process (S1) of FIG. 7 ends (FIG. 8: END), and the process proceeds to the next stack pointer setting process (FIG. 7: S2).

On the other hand, if it is assumed that the erase switch 42s is depressed when the power is turned on, the fact that the erase switch 42s is ON indicates that the I / O interface 41 and the signal line 79 are on.
a (YES in S20), and the CPU 41a
As a result, a backup RAM clear procedure for clearing the backed up contents of the RAM 41c by software is executed (S22). In this case, the contents of the RAM 41c are completely cleared. And backup RAM
When the clear (S22) process is completed, the power-on process (FIG. 7: S1) of FIG. 7 ends (FIG. 8: END),
The process proceeds to the next stack pointer setting process (FIG. 7: S2).

In the flowchart shown in FIG. 8, when the power-on process (S1) is completed, a stack pointer setting process for setting a designated address of the stack pointer is performed (S2). Next, a RAM check for checking the stored contents of the RAM 41c is performed (S3). The RAM check (S3) is for determining whether or not the power-on initial setting process (S4) is being performed. At this time, it is determined whether or not a predetermined numerical value written in the power-on initial setting process (S4) is written in the initial setting storage area of the RAM 41c.

The backup RAM clear of FIG. 8 (S2
When the process of 2) is being performed, since a predetermined numerical value is not written in the initial setting storage area of the RAM 41c (S3: NO), the power-on initial setting process is performed (S4). In addition, even when the power is not turned on, for some reason R
When the storage of the AM 41c is not normal, the RAM check (S3) also determines that the storage is not normal. In this process, the storage value of each storage area of the RAM 41c is set to a predetermined default value. For example, the value of each loop counter stored in a loop counter storage area (not shown) is set to an initial value (for example, “0”), and a predetermined numerical value is stored in the initial setting storage area.
Then, the processing of FIG. 7 is temporarily ended (end).

Processing is performed from the start by the reset signal. First, in the power-on process (S1), if the erase switch 42s is not pressed (FIG. 8: S20: N)
O), a power recovery process (S28) is performed,
1c, the processing is performed based on the storage, and as described above, nothing is performed here and the stack pointer setting processing (S
Go to 2). And in the RAM check (S3),
Since a predetermined numerical value is written in the initial setting storage area, the RAM 41c is determined to be normal (S3: YES),
The process proceeds to the next liquid crystal screen command output process (S5). In the liquid crystal screen command output processing (S5), the main board 41
Sends a signal for controlling the display of the liquid crystal screen to the symbol display board 44, and the symbol display board 44
At the same time, the information is stored in the AM 44c, and the predetermined symbol information is read out from the table stored in the ROM 44b by the designation or the lottery designated based on the control signal, and the image information is transmitted from the drive circuit (not shown) to the special symbol display device 8. . Next, the process proceeds to a sound command output process (S6). In this sound command output processing (S6), the main board 4
A signal designating a pattern to be uttered by the speaker 61 is sent from 1 to the sound board 43, and the sound board 43 reads out voice information according to the pattern from the ROM 43b and makes the speaker 61 utter the voice information via the drive circuit. Next, a lamp command output process (S7) is performed. In the lamp command output process (S7), a signal designating a blinking pattern of various lamps provided in the pachinko machine 1 is output from the main board 41 to the illumination board 46. The illuminated board 46 reads the illuminated control information of this pattern from the ROM 46b and sends out drive signals to various lamps. Then
Port output processing is performed (S8). In the port output process (S8), the jackpot information, the symbol determination information, and the like of the pachinko machine 1 are output to a game center management computer (not shown) via the external connection terminal 2 board 40 and the like.

Next, a switch reading process (S9) is performed. This switch reading process (S9) is performed by the normal symbol starting gates 11 and 12 and the special symbol starting electric accessory 1 shown in FIG.
5, detecting a winning of a game ball to the special winning opening 16, the winning opening 19, 20, 30, 31 or the like.

When the switch reading process (S9) is completed,
Next, a loop counter updating process (S10) is performed. In the loop counter updating process (S10), the RAM 41
The values of the normal symbol selection loop counter, the jackpot determination loop counter, the special symbol creation counter, the reach determination counter, and the reach pattern determination counter stored in the loop counter storage area (not shown) of FIG. Increment). When the value exceeds the maximum value set in each loop counter, the value of each loop counter is cleared to 0 and programmed to return to "0".

Next, it is determined whether an error has occurred in the pachinko machine 1 (S11). If an error has occurred in the pachinko machine 1 (S11: YES), the condition device process (S12) The special symbol processing (S13) and the normal symbol processing (S14) are skipped to perform the processing, and the special symbol display device 8
To display an error or the like. If no error has occurred (S11: NO), the process proceeds to the condition device process (S12).

In the condition device processing (S12), the special winning opening 1
6 (see FIG. 2), a jackpot demonstration display process on the liquid crystal screen (see FIG. 3) of the special symbol display device 8, and the like are performed. In the first round of processing, a special symbol processing (S
Since the jackpot determination process in 13) has not been performed yet, in the condition device process (S12), nothing is performed and the process proceeds to the next process. Next, a special symbol process (S13) is performed. In the special symbol processing (S13), a big hit determination processing is performed.

When the special symbol processing (S13) is completed, next, a normal symbol processing (S14) is performed. In the ordinary symbol processing (S14), the count value of the ordinary symbol selection loop counter (not shown) is changed to the ordinary symbol random number by the passing of the game ball to the ordinary symbol starting gates 11, 12, and the RAM is used as the ordinary symbol random number.
41c is stored in a non-illustrated ordinary symbol random number storage area,
The symbols are fixedly displayed on the ordinary symbol display device 24 based on the ordinary symbol random numbers.

When the normal symbol processing (S14) is completed, next, a payout control (S15) for paying out prize balls is performed.
When paying out prize balls, the signal line 78 is
A payout request command is transmitted to the payout control board 45 via the. The payout control board 45 temporarily stores a payout request command in the RAM 45c, and pays out prize balls sequentially based on the payout request command. Then, the frame lamp control (S16)
After that, the processing of the main routine ends. The processing of this main routine includes the processing of the subroutine and
It ends within ms. Therefore, the main routine does not always execute all the procedures up to the end, leaves the result of the processing in a flag or the like, and is executed so as to always end within 2 ms. The CPU 41a receives a reset signal from the reset circuit 17 every 2 ms.
Repeats the processing of the main routine shown in FIG. 7 from the start.

If it is determined in the special symbol processing (S13) of the processing of the main routine of the first cycle that the state is a big hit state, R
"1" is stored in a jackpot flag storage area (not shown) of the AM 41c, the jackpot flag is turned on, and the opening and closing operations of the jackpot 16 are performed a predetermined number of times in the next condition device processing (S12) in the second round. (For example, 15 times or 16 times
Times).

The pachinko machine 1 of the first embodiment has been described in detail with the main board 41 as an example. However, the sound board 43, the symbol display board 44, the payout control board 45, which are sub-boards other than the main board 41, Also in the illumination board 46, the main board 41
Similarly to the above, the signal of the erase switch 42s of the power supply board 42 is
From the signal lines 79b, 79c, 79d, 79e, I / O interfaces 43d, 44d, 45 of the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46, respectively.
d, 46d, the respective CPUs 43a, 44a,
The detection is performed by 45a and 46a, and the same control as that of the main board 41 is performed. That is, when the power is turned on, the same processing as the processing in the procedure of the flowchart shown in FIG. 8 is performed, and if the erase switch 42s is not pressed (S20: N
O), a power restoration process (S28) is performed. In addition, in the flowchart of FIG. 7, the processing of S1 to S4 is processing that is commonly performed in each substrate, and the processing of S5 to S16 is
The processing differs according to each substrate and is performed based on a unique flow. For example, in the case of the symbol display board 44, if a command from the main board 41 is stored in the RAM 44c, processing for displaying a symbol on the special symbol display device 8 is performed according to the command. Therefore, for example, if "10,000", "10,000", "10,000" is displayed on the special symbol display device 8, even after the power is turned on again, the special symbol display device is again displayed based on the storage in the RAM 44c. 8, "10,000",
"10,000" and "10,000" symbols are displayed. On the other hand, when the power is turned on again while the erase switch 42s is being pressed (S20: YES), the process of clearing the backup RAM (S22) is performed, and the initial screen is displayed on the special symbol display device 8. You.

In the case of the payout control board 45, if the erase switch 42s is not pressed (S20: N
O), power restoration processing (S28) is performed, and if the number of payout balls to be paid out is stored in the RAM 45c, the payout of payout balls is performed based on the storage. On the other hand, the erase switch 42
If the power is turned on again while s is pressed (S
20: YES), backup RAM clear (S22)
Is performed, and even if there is a prize ball to be paid out before the power is turned off, it is not paid out. The same applies to the sound board 43 and the illumination board 46.

Power recovery processing (S28) or backup RA
When the procedure of M clear (S22) is completed, the sound board 43,
Returning to the respective routines of the symbol display board 44, the payout control board 45, and the illuminated board 46, normal processing (not shown in detail) is continued. In the case of the normal processing, when the procedure of clearing the backup RAM (S22) is being executed, the RAM check in FIG.
For c, the same initial settings as in the power-on initial setting process (S4) in FIG. 7 are performed.

In the pachinko machine 1 according to the first embodiment, the case where the power is turned on while pressing the erase switch 42s when the power is turned on has been described. However, even if the erase switch 42s is pressed after the power is turned on (S20: YES). ), So that the process of clearing the backup RAM (S22) is performed. Therefore, if power is supplied to the pachinko machine 1, the RAM 41c and the like can be cleared at any time.

The ON condition of the power switch 80 and the ON condition of the erase switch 42s are AND conditions, and the power switch 8
RAM 41c, 43c, 44c, 45c, 46c only when the erase switch 42s is turned on when 0 is turned on.
Unless the power is once turned off and the power is turned on again, RA is depressed even if the erase switch 42s is pressed.
M41c, 43c, 44c, 45c, 46c may be configured not to be erased.

Further, the erase switch 4 is provided only for a predetermined time.
It may be configured such that input of 2s is permitted. Here, FIG. 9 is a flowchart showing another processing method of the power-on processing (FIG. 7: S1). As shown in FIG. 9, for example, in the case of the main board 41, the RAM 41c of the main board 41
The elapsed time obtained by counting the time since the power was turned on again is stored. If a predetermined time, for example, 30 seconds before the power was turned on (S120: NO), the erase switch 42s is turned on (S122: YES). ), Backup RAM
The process of clearing (S124) is performed, but after a predetermined time of 30 seconds has elapsed (S120: YES), the power restoration process (S126).
May be performed so that the process of clearing the backup RAM (S124) is not executed.

If the pachinko machine 1 is configured and controlled as in this modified example, the erasing switch 4 is not turned on until the predetermined time elapses after the main power of the pachinko machine 1 is turned on again.
Only when the press of 2s is detected, the RAMs 41c and 43
The contents of c, 44c, 45c, and 46c are deleted. That is, the CPU 41a, 43a,
44a, 45a and 46a repeatedly detect the detection of the erase switch 42s to prevent a detection error,
On the other hand, after 30 seconds, even if the erase switch 42s is operated, it is possible to prevent the contents of the RAMs 41c, 43c, 44c, 45c and 46c from being erased. In this case, the RAMs 41c, 43c, 44c, 45c, 46
If the content of c is to be erased after 30 seconds, the backup power supply must be cut off by hardware because the software cannot be erased. In this case, however, it was formed in a one-chip microcomputer as described above. Input terminal Vc of main power supply
c (not shown), the main power of the pachinko machine 1 is turned off, and the RAM is
It is also possible to prevent the contents of 41c, 43c, 44c, 45c, 46c from being erased. Of course, the predetermined time may be set to one second after the power is turned on again, or may be set to five minutes depending on the purpose.

As described above, the pachinko machine 1 according to the first embodiment of the present embodiment has the following configuration and operation, and has the following effects. That is, the main board 41 and the sound board 4 which is a sub-board
3, symbol display board 44, payout control board 45, illumination board 4
RAMs 41c, 43c and 44 which are volatile memories of No. 6
c, 45c, and 46c by supplying a backup power supply,
Since the contents of the RAMs 41c, 43c, 44c, 45c, and 46c can be backed up so as not to be erased, power supply to the main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46 is undesirably performed. When the power supply is restored even when the power supply is cut off, the game can be continued so as not to be disadvantageous to the player. In particular, the sound board 43, the symbol display board 44, the payout control board 45, and the illuminated board 46, which are the sub-boards, are also backed up, so that the state before the power supply is cut off can be restored more reproducibly.

The erase switch 42 s as erase switch means, the main board 41 and the sound board 4 as erase control means are provided.
3, symbol display board 44, payout control board 45, illumination board 4
6 are provided with the CPUs 41a, 43a, 44a, 45a, 46a and ROMs 41b, 43b, 444b, 45b, 46b. When the erase switch 42s is pressed, the backed up RAMs 41c, 43c, 44c, 45c, 4c are provided.
Since the contents of 6c can be deleted, when a new game is played, the player can easily return to the initial state so as not to be unfair.

In particular, when the erase switch 42s is pressed, the backed-up RAMs 41c, 43c, 44
main board 41 on which c, 45c, 46c are arranged, sound board 4
3, symbol display board 44, payout control board 45, illumination board 4
6 using the CPUs 41a, 43a, 44a, 45a, and 46a to erase the contents of the volatile memory for each substrate in response to a signal by pressing the erase switch 42s.
The main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the R
There is an effect that all the contents of the AMs 41c, 43c, 44c, 45c, and 46c can be easily erased.

Further, when the erase switch 42s is depressed,
In order to erase the contents of the AMs 41c, 43c, 44c, 45c and 46c, the erasure switch 42s is consciously operated only when the user wants to erase the contents.
An accident of erasing the content of c can be effectively prevented.

Also, for example, the RA provided on the main substrate 41
M41c, CPU41a, ROM41b are integrally formed as a one-chip microcomputer, due to the provision of a backup power supply terminal _{V BB} of RAM 41c, there is an effect that it the configuration of the main substrate 41 in a simpler structure. Also, the sound board 43, the symbol display board 44, the payout control board 4
5. The same applies to the illuminated substrate 46. Since the erase switch 42s is disposed on the power supply board 42, there is also an effect that the power supply from the power supply board 42 can be easily supplied to the erase switch 42s.

(Embodiment 2) Next, a pachinko machine according to Embodiment 2 which is another embodiment of the present invention will be described with reference to the drawings. Since the pachinko machine shown in the second embodiment has the same basic configuration as the pachinko machine 1, only the configuration that is different from the pachinko machine 1 will be described. Description is omitted.

FIG. 6 shows a power supply between the main board 41, the power supply board 42, the sound board 43, the symbol display board 44, the payout control board 45, and the illuminated board 46 in the pachinko machine according to the second embodiment . FIG. 3 is a diagram for explaining current supply and signal flow. In the pachinko machine 1, as shown in FIG. 5, the erase switch 42s provided on the power supply board 42 is connected to signal lines 79a, 79b, 79.
c, 79d, and 79e, the main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the I
/ O interfaces 41d, 43d, 44d, 45d,
46d.

On the other hand, in the pachinko machine shown in the second embodiment, the erase switch 42s provided on the power supply board 42 as shown in FIG.
Is connected to the I / O interface 41d. And
From the I / O interface 41d of the main board 41, the I / O interface 43d of the sound board 43 is connected by a signal line 83b.
To the symbol display substrate 44 via the signal line 83c.
Connected to the I / O interface 44d, connected to the I / O interface 45d of the payout control board 45 by a signal line 83d, and connected to the I / O interface 46d of the illuminated board 46 by a signal line 83e. Are different. Other configurations are the same as those in FIG.

FIG. 6 shows a second embodiment of the present invention.
The main board 41 of the dick machine is controlled as follows. Real
On the main board 41 of the pachinko machine shown in the second embodiment , the same main routine as that of the main board 41 of the pachinko machine 1 shown in FIG. 7 is executed. The main routine of the main board 41 of the pachinko machine according to the second embodiment will be described with reference to FIG. 7, which is the main routine of the main board of the pachinko machine 1. First, when the power is turned on, a power-on process (S1) is executed. Real
The pachinko machine according to the second embodiment performs the power-on process (S1).
Is different from the control of the pachinko machine 1.

[0085] Here, snapping Figure 10, shown in Example 2
Is a procedure flowchart showing in detail the power-on processing of the flowchart shown in FIG. 7 of the main substrate 41 (S1) in co machine. Referring to FIG. 10 below, Pachi shown in Example 2
The procedure of the power-on process (S1) of the stamp machine will be described in detail. When the power is supplied from the power supply board 42 to the main board 41 (power ON), that is, when the power switch 80 of the power supply board 42 is turned ON or when the power failure is recovered, the CPU 41a of the main board 41 starts up, The following procedure is performed according to the control program read from the ROM 41b.

As shown in FIG. 6, the signal from the erase switch 42s is transmitted to the I / O interface 41d of the main board 41 via the signal line 83a. Then, the main substrate 41
Of the erase switch 42s
Receive via the / O interface 41d. The CPU 41a that has started up there is the I / O interface 41.
d, It is determined whether the erase switch 42s provided on the power supply board 42 via the signal line 83a is turned on (S3).
0) For example, if the signal from the erase switch 42s is equal to or higher than a predetermined HI level voltage, it is determined to be ON (S30:
If it is less than the voltage of the predetermined level, it is determined to be OFF (S30: NO).

In the pachinko machine according to the second embodiment , when the power switch 80 is closed, the RAM 41c receives the power supply current of +5 V DC from the power supply board 42 and retains the stored contents. even when cut, through the power supply line 82a from the battery backup power source provided in the power supply board 42, RAM 41c from V _BB pin of the one-chip microcomputer provided in the main substrate 41
, The contents stored in the RAM 41c are held as they are.

Here, in S30, the erase switch 42
s is not ON (S30: N
O), that is, when the erase switch 42s is not pressed, the power restoration process (S38) is performed as in the case of the pachinko machine 1. In the power restoration process (S38), the CPU 41a reads out the contents stored in the backed-up RAM 41c, and based on the contents stored in the RAM 41c, the power is turned on or off by the administrator. When the power is cut off, the state of the pachinko machine shown in the second embodiment is restored to the state before the power was turned off. Therefore, for example, even in the case where a power failure due to an accident occurs during a game of the player, if the player is in a jackpot state before the power failure, the jackpot flag stored in the RAM 41c is turned on after the power is restored. Therefore, the game can be continued in the jackpot state again.

The pachinko machine already shown in Example 2
If normal processing is being performed, power restoration processing (S38)
, The recovery process is not performed and the RAM 41
The process based on the stored content of c is continued. When the power restoration process (S38) ends, the power-on process (S1) in FIG.
Is completed (FIG. 10: END), and the process proceeds to the next stack pointer setting process (FIG. 7: S2).

On the other hand, if it is assumed that the erase switch 42s is depressed when the power is turned on, the fact that the erase switch 42s is ON indicates that the I / O interface 41d and the signal line 8
Detected via 3a (S30: YES).

Here, the RAM clear command is sent (S3
The procedure 2) is executed by the CPU 41a of the main board 41. In the pachinko machine shown in the second embodiment , unlike the pachinko machine 1, from the power supply board 42, the sound board 43 as a sub-board, the symbol display board 44, the payout control board 45, and the illuminating board 46 to the erase switch 42s. No signal is sent directly. Therefore, the fact that the erase switch 42s is turned on indicates that the sound board 43, the symbol display board 44,
In order to transmit the signals to the payout control board 45 and the illuminated board 46, a signal line 83 is transmitted from the I / O interface 41 d of the main board 41.
b, 83c, 83d, 83e, I / O of the sound board 43
Interface 43d, I / O interface 44d of symbol display board 44, I / O interface 45d of payout control board 45, and I / O interface 4 of illumination board 46
A RAM clear command is sent to each of the CPUs 43a, 44a, 45a, 46a via 6d. RA
The M clear command is transmitted to the CPUs 43a, 44a, 45a,
RAM 43c backed up for 46a,
This is a command for instructing to delete the contents of 44c, 45c, and 46c.

The CPU 41a of the main board 41 which has completed the procedure of sending the RAM clear command (S32) executes a backup RAM clear procedure for clearing the backed up contents of the RAM 41c by software (S3).
4). In this case, the contents of the RAM 41c are completely erased (cleared). Then, the backup RAM is cleared (S
When the process of 22) is completed, the power-on process (S
After the processing of 1) is completed (FIG. 10: END), the process proceeds to the next stack pointer setting processing (FIG. 7: S2).
The main routine in the main board 41 of the pachinko machine shown in the second embodiment is the same as that of the control of the pachinko machine 1 after S2 in FIG.
Instead of the description in the description of the main board 41 of the pachinko machine shown in Example 2, the description thereof is omitted in the control of the main board 41 of the pachinko machine shown in Example 2.

On the other hand, in the sound board 43, the symbol display board 44, the payout control board 45, and the illuminated board 46, which are the sub boards of the pachinko machine shown in the second embodiment, the processing according to the flowchart shown in FIG. 11 is performed. . Here, FIG. 11, the real
Sound board 43 and symbol display board 4 of the pachinko machine shown in Embodiment 2.
4 is a flowchart showing a procedure of processing in a payout control board 45 and an illuminated board 46. That is, when the power is turned on again, if the CPU 43a, 44a, 45a, 46a determines that the RAM clear command has not been received within a predetermined time (S40: NO), the power recovery processing ( S48) is performed. The power restoration process (S48)
The contents stored in the backed-up RAMs 43c, 44c, 45c, and 46c are read out by the U43a, 44a, 45a, and 46a.
Based on the contents stored in 44c, 45c, and 46c, when the power supply is cut off by the administrator's will or against the intention, the state of the pachinko machine shown in the second embodiment before the power supply is cut off. It restores the state. For example, in the case of the symbol display board 44, if a command from the main board 41 is stored in the RAM 44c, a symbol is displayed on the special symbol display device 8 according to the command. Therefore, for example, "10,000", "11,000",
If it is displayed as "10,000", "10,000", "10,000", "10,000",
The design of "Ichiman" is displayed. Also, the payout control board 45
In this case, if the number of payout balls to be paid out is stored in the RAM 45c, the payout of payout balls is performed based on the storage.

On the other hand, if the RAM clear command is received within a predetermined time (S40: YES), the backup R
The process of AM clear (S42) is performed, and an initial screen is displayed on the special symbol display device 8. Dispensing control board 4
If it is 5, even if there is a prize ball to be paid out before the power is turned off, it will not be paid out. Note that the sound board 43 and the illumination board 46 are similarly controlled.

Power recovery processing (S48) or backup RA
When the procedure of M clear (S42) is completed, the sound board 43,
Returning to the respective routines of the symbol display board 44, the payout control board 45, and the illuminated board 46, the normal processing (S50) not shown in detail is continued. Note that normal processing (S5
In 0), the backup RAM is cleared (S42).
Is the RAM check in FIG. 7 normal? Similar to the determination of (S3), the same determination as the determination that the RAM check is not normal (S3: NO) is made. The same initial settings are made.

As described above, the implementation of the present embodiment
The pachinko machine shown in Example 2 has the following effects because it has the above configuration and operation. That is, when the erase switch 42s is pressed, the RAM 41, which is a volatile memory, is backed up by a backup power supply provided on the power supply board 42 as a backup means.
c using the CPU 41a of the main board 41 on which the RAM 41c is disposed on the main board 41 in response to a signal resulting from the operation of the erase switch 42s as the erase switch means.
Is erased by software, and the C
The PU 41a includes a sub-substrate sound board 43, a symbol display board 44, a payout control board 45, and a CPU 43 of an electric decoration board 46.
a, 44a, 45a, and 46a are RAMs that are predetermined signals.
CPU 43a, 44a, 45 sends a clear command.
a, 46a, a RAM 43 disposed on the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46.
There is an effect that the contents of c, 44c, 45c, and 46c can be erased by software.

Although the embodiments of the present invention have been described with reference to the first and second embodiments, it is needless to say that the present invention is not limited to the above embodiments. For example, one that backs up only a part of the sub-boards, or one that backs up only the main board without backing up the sub-boards, or that backs up only this main board that is composed only of the main board without the sub-boards It can be applied to a game machine.

FIG. 12 is a diagram showing a configuration in which only the main board 41 and the payout control board 45 are backed up by the backup power supply provided in the power board 42 in the pachinko machine 1 of the first embodiment. As shown in FIG. 12, the main board 41
The power supply line 84a is connected to the RAM 4 of the main board 41.
1c is supplied with backup power. A power supply line 84d is connected from the backup power supply of the power supply board 42 to the payout control board 45, and the RAM of the payout control board 45
A backup power is supplied to 45c. Here, in FIGS. 5 and 6, the power supply lines 82a to 82e connect DC + 1 including a backup power supply as shown in FIG.
A power supply of a voltage corresponding to each application such as 2 V and DC + 5 V is supplied to each substrate.
Power supply lines 84a and 84d in FIG. 12 only show connection to a backup power supply for the sake of explanation. Therefore, the sound board 43, the symbol display board 44, and the illuminated board 46
Other DC + 12V, DC + 5 except power supply for backup
A power supply line (not shown) for supplying V power is connected to the power supply board 42.

On the other hand, the erase switch 42s of the power supply board 42
The signal line 85a is connected to the CPU 41a via the I / O interface 41d of the main board 41. Similarly, the erase switch 42s of the power supply board 42 is connected to the signal line 85a.
Through the I / O interface 41d of the main board 41,
Connected to PU 41a. Accordingly, the CPUs 43a, 44a, and 4 of the sound board 43, the symbol display board 44, and the illumination board 46.
6a is not connected to the erase switch 42s.

In the configuration shown in FIG.
Only the M41c and the RAM 45c of the payout control board 45 are backed up, and the CPU 41a of the main board 41 and the CP of the payout control board 45 are pressed by pressing the erase switch 42s.
By U45a, the stored contents of the RAM 41c of the main board 41 and the RAM 45c of the payout control board 45 are erased in a software manner. On the other hand, the sound board 43, the symbol display board 44, and the illuminated board 46 have the RAMs 43c, 44c, 46 while the main power of DC + 12V and DC + 5V are supplied.
c is retained, but the DC + 12
When the power supply of V and DC + 5V is not supplied, the RAM 4
The stored contents of 3c, 44c and 46c are deleted.

Therefore, if the gaming machine has a configuration as shown in FIG. 12, a flag (not shown) indicating a special gaming state.
The storage of the RAM 41c of the main board 41 and the RAM 45c of the payout control board 45, which store the storage contents that greatly affect the player's profit such as the payout of award balls, can be backed up and held, and can be erased. The configuration of the gaming machine can be simplified by not backing up the sound board 43, the symbol display board 44, and the illuminated board 46 that have little effect on the profit of the player.

Next, FIG. 13 shows the pachinko machine according to the second embodiment .
FIG. 7 is a diagram showing a configuration in which only a main board 41 and a payout control board 45 are backed up by a backup power supply provided in a power supply board 42 in the machine . As shown in FIG. 13, the main board 41
The power supply line 86a is connected to the RAM 4 of the main board 41.
1c is supplied with backup power. A power supply line 86d is connected from the backup power supply of the power supply board 42 to the payout control board 45, and the RAM of the payout control board 45 is connected to the power supply line 86d.
A backup power is supplied to 45c. FIG.
5 and 6, the power supply line 82a
As shown in FIG. 4, power supplies of a voltage according to each application such as DC + 12 V and DC + 5 V including a backup power supply are supplied to each substrate as shown in FIG. 4. Although shown as supply lines 82a to 82e, power supply lines 86a and 86d in FIG.
Shows only the connection with the backup power supply for explanation. Therefore, the sound board 43, the symbol display board 44, and the illuminated board 46 are connected to other DC + 12 except for the backup power supply.
The power supply is connected to a power supply board 42 by a power supply line (not shown) for supplying power of V, DC + 5V.

On the other hand, the erase switch 42s of the power supply board 42
The signal line 87a is connected to the CPU 41a via the I / O interface 41d of the main board 41. Unlike FIG. 12, the signal line 87d is connected from the CPU 41a of the main board 41 via the I / O interface 41d, and the signal line 87d is connected to the CPU 45a via the I / O interface 45d of the payout control board 45. You. Accordingly, the CPU 4 of the sound board 43, the symbol display board 44, and the illumination board 46
3a, 44a and 46a are not connected to either the erase switch 42s or the CPU 41a of the main board 41.

In the configuration shown in FIG.
Only the M41c and the RAM 45c of the payout control board 45 are backed up, and when the erase switch 42s is pressed, the CPU 41a of the main board 41
While the stored contents of M41c are erased, the main board 41
CPU 41a includes an I / O interface 41d, a signal line 87d, and an I / O interface 4 of the payout control board 45.
A RAM clear command (see FIG. 10) is transmitted to the CPU 45a of the payout control board 45 via 5d, and the CPU 45a of the payout control board 45 erases the contents of the RAM 45c by software. On the other hand, a sound board 43, a symbol display board 44,
The illumination board 46 is a DC + 12V, DC
While the power of +5 V is supplied, the RAMs 43c and 44
c and 46c are retained, but the main power supply D
If power supply of C + 12V and DC + 5V is not supplied,
The contents stored in the RAMs 43c, 44c and 46c are deleted.

Therefore, in the gaming machine having such a configuration, the main board 41 which stores a flag (not shown) indicating a special gaming state and storage contents which greatly affect the player's profit such as payout of award balls. RAM 41c and payout control board 45
Of the RAM 45c can be backed up and held,
The sound board 43, the symbol display board 44, and the illuminated board 46, which can be erased and have relatively little effect on the profit of the player, are not backed up, so that the configuration of the gaming machine can be simplified.

Next, FIG. 14 shows that in the pachinko machine 1 of the first embodiment, only the main board 41 and the payout control board 45 are backed up by the backup power supply provided on the power board 42, and the erase switch 41s is set to the main board 41. FIG. As shown in FIG.
Power supply line 88 from the backup power supply to the main board 41
a is connected, and backup power is supplied to the RAM 41 c of the main board 41. A power supply line 88d is connected from the backup power supply of the power supply board 42 to the payout control board 45, and the backup power is supplied to the RAM 45c of the payout control board 45. Here, in FIGS. 5 and 6, DC + 12V and DC + 5V including a backup power supply as shown in FIG.
And the like. A power supply having a voltage corresponding to each use such as is supplied to each substrate.
Although illustrated as 2a to 82e, the power supply lines 88a and 88d in FIG. 12 only show connection to a backup power supply for the sake of explanation. Therefore, the sound board 43,
The symbol display board 44 and the illuminated board 46 are connected to the power supply board 42 by a power supply line (not shown) that supplies power of DC +12 V and DC +5 V other than the backup power supply.

On the other hand, the erase switch 41 s is
When the erase switch 41s is operated by receiving power from a power supply line (not shown) of the main board 41, a predetermined signal is transmitted. The erase switch 41s is connected to the CPU via the I / O interface 41d of the main board 41
41a. The erase switch 41s is connected to the CPU 45a via the I / O interface 45d of the payout control board 45 via the signal line 89d. Therefore, the sound substrate 43, the symbol display substrate 44, and the C
The PUs 43a, 44a and 46a are not connected to the erase switch 41s arranged on the main board 41.

In the configuration shown in FIG.
Only the M41c and the RAM 45c of the payout control board 45 are backed up, and the CPU 41a of the main board 41 and the CP of the payout control board 45 are
By U45a, the stored contents of the RAM 41c of the main board 41 and the RAM 45c of the payout control board 45 are erased in a software manner. On the other hand, the sound board 43, the symbol display board 44, and the illuminated board 46 have the RAMs 43c, 44c, 46 while the main power of DC + 12V and DC + 5V are supplied.
c is retained, but the DC + 12
When the power supply of V and DC + 5V is not supplied, the RAM 4
The stored contents of 3c, 44c and 46c are deleted.

Therefore, if the gaming machine has a configuration as shown in FIG. 14, a flag (not shown) indicating a special gaming state.
The storage of the RAM 41c of the main board 41 and the RAM 45c of the payout control board 45, which store the storage contents that greatly affect the player's profit such as the payout of award balls, can be backed up and held, and can be erased. The configuration of the gaming machine can be simplified by not backing up the sound board 43, the symbol display board 44, and the illuminated board 46 that have little effect on the profit of the player. Further, by disposing the switch 41 s on the main board 41, the switch 41 s
The signal line for connecting to one I / O interface can be shortened, and the signal attenuation can be reduced.

Although not shown, a backup means which does not include a sub-board, supplies backup power to the RAM 41c of the main board 41 from a backup power supply provided on the power supply board 42, and backs up only the RAM 41c, A pachinko machine having an erase switch 42s operated to erase the contents of the RAM 41c, wherein the RAM 41c is backed up and the erase switch 42s is pressed to erase only the stored contents of the RAM 41c. Can also. Then, the power supply board 42 and the main board 41 may be integrally formed.

The gaming machine has been described as an example of a type 1 pachinko machine, but not only a type 1 pachinko machine but also a pachinko machine of each type, such as a slot machine, a pachinko machine, a pachislot machine, and not limited thereto It goes without saying that the present invention can be applied to various types of gaming machines controlled by the main board.

Further, it is easily presumed that those skilled in the art can implement the present invention with various modifications and improvements without departing from the scope of the claims.

[0113]

As described above, in the gaming machine according to the first aspect of the present invention, backup power can be supplied to the volatile memory of the main board by the backup means so that the contents of the volatile memory are not erased. Therefore, even when the supply of the power supply current to the main board is undesirably cut off,
When the supply of power is restored, the game can be continued so as not to be disadvantageous for the player. In addition, when the erase switch means is operated, the contents of the volatile memory backed up by the backup means can be erased when the erase switch means is operated, so that when playing a new game, it is unfair to the player. There is an effect that it is possible to easily return to the initial state so as not to be out of order.

In the gaming machine according to the second aspect of the present invention, backup power can be supplied to the volatile memories of the main board and the sub-board by the backup means so that the contents of the volatile memories are not erased. Even when the supply of the power supply current to the main board and the sub-board is cut off, the game can be continued so as not to be disadvantageous for the player when the supply of the power supply is restored. In particular, since the backup is performed even on the sub-board, the state before the supply of the power supply current is cut off can be restored more reproducibly. In addition, when the erase switch means is operated, the contents of the volatile memory backed up by the backup means can be erased when the erase switch means is operated, so that when playing a new game, it is unfair to the player. There is an effect that it is possible to easily return to the initial state so as not to be out of order.

The gaming machine according to the third aspect of the present invention provides the gaming machine according to the second aspect.
In addition to the effects of the gaming machine described in the above, when the erase switch means is operated, the C of the main board or the sub-board on which the volatile memory backed up by the backup means is arranged
Using the PU, there is an effect that the contents of the volatile memory can be erased for each substrate according to the signal resulting from the operation of the erase switch means. Therefore, there is an effect that the contents of the volatile memories on the main substrate and the sub substrate can be erased by one erase switch.

The gaming machine according to the fourth aspect of the present invention provides the gaming machine according to the second aspect.
In addition to the effects of the gaming machine described in the above, when the erase switch means is operated, using the CPU of the main board on which the volatile memory backed up by the backup means is arranged,
In response to a signal resulting from the operation of the erase switch means, the contents of the volatile memory arranged on the main board are erased, and the CPU of the main board sends a predetermined signal to the CPU of the sub-board, Accordingly, there is an effect that the contents of the volatile memory arranged on the sub-board can be erased.

The gaming machine according to the fifth aspect of the present invention provides the gaming machine according to the first aspect.
In addition to the effects of the gaming machine according to any one of claims 4 to 4,
When the main power of the gaming machine is turned on while the erase switch means is operated, to erase the contents of the volatile memory,
There is an effect that the contents of the volatile memory can be easily erased by arbitrarily operating the erase switch means only when the contents of the volatile memory are to be erased.

The gaming machine according to the sixth aspect of the present invention provides the gaming machine according to the first aspect.
In addition to the effects of the gaming machine according to any one of claims 5 to 5,
When the operation of the erase switch is detected during a predetermined time period after the main power of the gaming machine is turned on, the operation of the erase switch is detected for a certain period of time to erase the contents of the volatile memory when the operation of the erase switch is detected. In addition to preventing erroneous operation, the contents of the volatile memory are not erased even if the erase switch is operated after a predetermined time has elapsed.

[0119] The gaming machine of the invention according to claim 7 is characterized by claim 1.
In addition to the effects of the gaming machine according to any one of claims 6 to 6,
The volatile memory is integrally formed with the CPU and the non-volatile memory of the substrate on which the volatile memory is arranged,
Since the main memory is configured as a part of the one-chip microcomputer having the backup power supply terminal of the volatile memory, the structure of the substrate can be simplified.

[0120] The gaming machine according to the eighth aspect of the present invention provides the gaming machine according to the first aspect.
In addition to the effects of the gaming machine according to any one of claims 7 to 7,
Since the erase switch means is arranged on the power supply substrate, there is an effect that the erase switch means can be easily supplied with power from the power supply substrate.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko machine 1. FIG.

FIG. 2 is a front view of the game board 2 of the pachinko machine 1.

FIG. 3 is a front view of the special symbol display device 8;

FIG. 4 is a block diagram showing an electric circuit configuration of the pachinko machine 1;

FIG. 5 shows a main board 41 and a power supply board 4 in the pachinko machine 1;
2, sound board 43, symbol display board 44, payout control board 4
FIG. 5 is a diagram for explaining the supply of a power supply current between the illuminated substrates 46 and the flow of signals.

FIG. 6 shows a main board 4 in the pachinko machine according to the second embodiment .
1. supply of a power supply current between the power supply board 42, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46;
FIG. 4 is a diagram illustrating a signal flow.

FIG. 7 is a flowchart showing a main routine of the pachinko machine 1.

FIG. 8 is a flowchart showing a power-on process (S
It is a flowchart which shows the procedure of 1) in detail.

9 is a flowchart showing another processing method of the power-on processing (FIG. 7: S1).

FIG. 10 shows a main board 4 in the pachinko machine according to the second embodiment .
1 is a power-on process (S1) in the flowchart shown in FIG.
5 is a flowchart showing the details of the procedure.

FIG. 11 is a flowchart illustrating a procedure of processing in the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46 of the pachinko machine according to the second embodiment .

FIG. 12 shows a power supply board 4 in the pachinko machine 1 according to the first embodiment.
The main board 41 is provided by the backup power supply provided in
FIG. 9 is a diagram showing a configuration for backing up only the payout control board 45.

FIG. 13 shows a main board 4 provided by a backup power supply provided on a power supply board 42 in the pachinko machine shown in the second embodiment .
6 is a diagram showing a configuration for backing up only the payout control board 1 and the payout control board 45. FIG.

FIG. 14 is a diagram illustrating a main board 4 of the pachinko machine 1 according to the first embodiment, which is provided by a backup power supply provided on a power board 42;
FIG. 11 is a diagram showing a configuration in which only 1 and the payout control board 45 are backed up and an erase switch 41s is provided on the main board 41.

[Description of Signs] 1 Pachinko machine 2 Gaming board 4 Gaming area 8 Special symbol display device 41 Main board 42 Power board 43 Sound board 44 Symbol display board 45 Dispensing control board 46 Illumination board 41a, 43a, 44a, 45a, 46a CPU 41b, 43b, 44b, 45b, 46b ROM 41c, 43c, 44c, 45c, 46c RAM 41d, 43d, 44d, 45d, 46d I / O interface 42s Erase switch 77, 78, 79a, 79b, 79c, 79d, 79
e, 83a, 83b, 83c, 83d, 83e Signal line 80 Power switch 82a, 82b, 82c, 82d, 82e Power supply line

Claims (8)

[Claims] 1. A game machine comprising: a main board for controlling a game machine; and a power supply board for supplying power to the main board, wherein a backup power is supplied to a volatile memory of the main board. Backup means for backing up the contents of the volatile memory so as not to be erased, erase switch means operated to erase the contents of the volatile memory backed up by the backup means, and erase switch means operated A gaming machine provided with an erasure control means for performing control so that the contents of the volatile memory backed up by the backup means are erased when the backup is performed. 2. A main board for controlling a gaming machine, one or more sub-boards for assisting control of the main board, and a power supply board for supplying power to the main board and the sub-board, respectively. Backup means for supplying a backup power supply to a volatile memory of at least one of the main board and the sub-board so as not to erase the contents of the volatile memory. And erase switch means operated to erase the contents of the volatile memory backed up by the backup means; and when the erase switch means is operated, the volatile memory backed up by the backup means A game machine comprising an erasure control means for controlling the contents of the game to be erased. 3. The erasure control means, when the erasure switch means is operated, using a CPU of the main board or the sub-board on which the volatile memory backed up by the backup means is arranged. 3. The gaming machine according to claim 2, wherein control is performed such that the content of said volatile memory is erased for each substrate in accordance with a signal resulting from operation of said erase switch means. 4. The erasure control means, when the erasure switch means is operated, uses the CPU of the main substrate on which the volatile memory backed up by the backup means is arranged, and In response to a signal resulting from the operation, the contents of the volatile memory disposed on the main board are erased, and the CPU of the main board sends a predetermined signal to the CPU of the sub-board, 3. The gaming machine according to claim 2, wherein the CPU controls to erase the contents of the volatile memory arranged on the sub-board. 5. The erasure control means controls to erase the contents of the volatile memory when the main power of the gaming machine is turned on while the erasure switch means is operated. The gaming machine according to claim 1. 6. The erasure control means, when the operation of the erasure switch means is detected during a predetermined time from when the main power of the gaming machine is turned on, and deletes the contents of the volatile memory. The gaming machine according to any one of claims 1 to 5, wherein the gaming machine is controlled to delete the game. 7. A part of a one-chip microcomputer which is integrally formed with a CPU and a non-volatile memory of a substrate on which the volatile memory is arranged, and has a backup power supply terminal of the volatile memory. The gaming machine according to any one of claims 1 to 6, wherein the main storage device is configured as: 8. The gaming machine according to claim 1, wherein said erase switch means is arranged on said power supply board.