JP2001244405A - Semiconductor device and its junction structure - Google Patents
Semiconductor device and its junction structureInfo
- Publication number
- JP2001244405A JP2001244405A JP2000054537A JP2000054537A JP2001244405A JP 2001244405 A JP2001244405 A JP 2001244405A JP 2000054537 A JP2000054537 A JP 2000054537A JP 2000054537 A JP2000054537 A JP 2000054537A JP 2001244405 A JP2001244405 A JP 2001244405A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- circuit board
- semiconductor chip
- semiconductor
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置および
半導体装置とプリント基板との接合構造に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a joining structure between the semiconductor device and a printed circuit board.
【0002】[0002]
【従来の技術】従来、半導体装置回路基板に電気的に接
合することにより構成される半導体装置であるパッケー
ジとしては、QFP(Quad Flat Package)、TCP(Tape
Carrier Package)、BGA(Ball Grid Array)、CSP
(Chip Scale or Size Package)、CCB(Controlled Co
llapsed Bonding)が知られている。2. Description of the Related Art Conventionally, semiconductor devices such as QFP (Quad Flat Package), TCP (Tape
Carrier Package), BGA (Ball Grid Array), CSP
(Chip Scale or Size Package), CCB (Controlled Co
llapsed bonding) is known.
【0003】BGAによる実装方法は、例えばUSP5,23
9,198、USP5,285,352、USP5,381,307、USP5,397,921に
記載されている。[0003] The mounting method using the BGA is described, for example, in US Pat.
9,198, USP 5,285,352, USP 5,381,307, USP 5,397,921.
【0004】BGAの構成は、回路基板上に半導体チッ
プをボンディングした後に封止し、回路基板の半導体チ
ップ搭載面と反対側の面上の配線電極部にはんだボール
を搭載し、溶融させた構造のものである。BGAをプリ
ント基板に実装するには、BGAのはんだボールとプリ
ント基板の配線電極部を該はんだボールを介してはんだ
接合を行なう。The BGA has a structure in which a semiconductor chip is bonded onto a circuit board and then sealed, and solder balls are mounted on a wiring electrode portion on a surface opposite to the semiconductor chip mounting surface of the circuit board, and are melted. belongs to. In order to mount the BGA on the printed circuit board, the solder ball of the BGA and the wiring electrode portion of the printed circuit board are soldered via the solder ball.
【0005】従来のBGAによる半導体装置の構成を図
3(a)、(b)を用いて説明する。図3(a)は半導
体装置の断面図、(b)は半導体装置をプリント基板に
接合させた接合構造の断面図である。[0005] The structure of a semiconductor device using a conventional BGA will be described with reference to FIGS. FIG. 3A is a cross-sectional view of a semiconductor device, and FIG. 3B is a cross-sectional view of a bonding structure in which the semiconductor device is bonded to a printed circuit board.
【0006】図3(a)において、101は両面に回路
パターンと電極部を有する回路基板である。回路基板1
01の片側の面には、半導体素子102がダイボンディ
ングされている。ダイボンディングされた半導体素子1
02は樹脂103でトランスファーモールドされ、封止
されている。In FIG. 3A, reference numeral 101 denotes a circuit board having circuit patterns and electrode portions on both surfaces. Circuit board 1
The semiconductor element 102 is die-bonded to one surface of the semiconductor device 102. Die-bonded semiconductor device 1
02 is transfer-molded with resin 103 and sealed.
【0007】半導体素子102をボンディングした面と
は反対側の面の電極部104には、はんだペーストが印
刷され、はんだペースト上にはんだボールを搭載した後
リフロー工程を経てはんだペーストとはんだボールを溶
融させ球状端子105が形成されている。はんだペース
トのフラックスは洗浄により除去され、半導体装置10
6が形成される。[0007] Solder paste is printed on the electrode portion 104 on the surface opposite to the surface to which the semiconductor element 102 is bonded. After the solder balls are mounted on the solder paste, the solder paste and the solder balls are melted through a reflow process. A spherical terminal 105 is formed. The solder paste flux is removed by washing, and the semiconductor device 10 is removed.
6 are formed.
【0008】次いで図3(b)により半導体装置とプリ
ント基板の接合構造を説明する。両面に回路パターンと
電極部108を有するプリント基板107の電極部10
8上にはんだペーストを塗布し、半導体装置106の電
極部104とプリント基板107の電極部108を位置
決めし、プリント基板107の電極部108のはんだペ
ースト上に半導体装置106の球状端子105を搭載す
る。その後リフロー工程を経て球状端子105とはんだ
ペーストを溶融させてはんだ付けを行なう。これで半導
体装置106の電極部104とプリント基板107の電
極部108が電気機械的に接合されたことになる。Next, a joint structure between the semiconductor device and the printed circuit board will be described with reference to FIG. Electrode part 10 of printed circuit board 107 having circuit pattern and electrode part 108 on both sides
8, a solder paste is applied, the electrode portion 104 of the semiconductor device 106 and the electrode portion 108 of the printed board 107 are positioned, and the spherical terminal 105 of the semiconductor device 106 is mounted on the solder paste of the electrode portion 108 of the printed board 107. . Thereafter, the soldering is performed by melting the spherical terminal 105 and the solder paste through a reflow process. Thus, the electrode portion 104 of the semiconductor device 106 and the electrode portion 108 of the printed board 107 are electromechanically joined.
【0009】CSPによる方法は、例えば、USP5,346,8
61、USP5,592,025に記載されている。[0009] The method using the CSP is described, for example, in USP 5,346,8.
61, USP 5,592,025.
【0010】CSPは、半導体チップをボンディングし
樹脂封止したフレキシブル基板の半導体チップ搭載面と
は反対側の面の電極部にクリームはんだを印刷し、その
上にはんだボールを載せリフローはんだ工程に流し、前
記はんだボールを前記フレキシブル基板の電極部と一体
的に構成したものである。プリント基板の配線電極部に
クリームはんだを塗布し、前記はんだボールを位置決め
搭載し、リフローはんだ工程を経てCSPのフレキシブ
ル基板の電極部とプリント基板の電極部とを電気的機械
的に接合を図る。[0010] The CSP prints cream solder on the electrode portion on the opposite side of the semiconductor chip mounting surface of the flexible substrate on which the semiconductor chip has been bonded and resin-sealed, and places a solder ball on the solder paste to flow into a reflow soldering process. And the solder ball is integrally formed with the electrode portion of the flexible substrate. A cream solder is applied to the wiring electrodes of the printed circuit board, the solder balls are positioned and mounted, and the electrodes of the flexible board of the CSP and the electrodes of the printed circuit board are electrically and mechanically joined through a reflow soldering process.
【0011】CCBによる方法は、例えば、USP3,292,2
40、USP3,303,393に記載されている。The method using CCB is described, for example, in US Pat. No. 3,292,2.
40, USP 3,303,393.
【0012】USP3,303,393には、電気回路
素子を電気接続するための回路パターンを形成した回路
基板と、半導体を載せたチップエレメント基板とを電気
機械的に接続するため、ボール状のターミナルエレメン
トをソルダーコーティングを介して前記チップエレメン
ト上に載せ、前記回路基板の回路パターンのターミナル
部と前記ターミナルエレメントとを位置合わせしてはん
だリフロー工程に流してはんだ接合する構成の開示があ
る。US Pat. No. 3,303,393 discloses a ball-shaped terminal for electromechanically connecting a circuit board on which a circuit pattern for electrically connecting an electric circuit element is formed and a chip element board on which a semiconductor is mounted. There is a disclosure of a configuration in which an element is mounted on the chip element via solder coating, a terminal portion of a circuit pattern of the circuit board is aligned with the terminal element, and a solder reflow process is performed to join the solder.
【0013】[0013]
【発明が解決しようとする課題】BGA方式、CSP方
式による従来の半導体素子の接合構造による場合、半導
体素子が1チップのために高密度な実装構造が取れない
という問題が生じている。In the case of the conventional semiconductor device bonding structure of the BGA system and the CSP system, there is a problem that a high-density mounting structure cannot be obtained because the semiconductor device is one chip.
【0014】また、BGA、CSPと他の電気回路素子
とを高速で電気伝送を図る場合、遅延、ノイズの発生等
電気に関わる問題が生じている。[0014] Further, when electric transmission between the BGA, CSP and other electric circuit elements is performed at high speed, problems related to electricity such as generation of delay and noise occur.
【0015】BGA方式、CSP方式による接合構造の
半導体装置は多くの電気機器、通信機器、事務機などの
製品に組み込まれて使用されており、実装の高密度化が
要求され、伝送速度アップに対する要求がますます増え
てきている。Semiconductor devices having a junction structure of the BGA system and the CSP system are used by being incorporated in many products such as electric equipment, communication equipment, and office machines. The demand is increasing.
【0016】BGA、CSPの高密度実装を図る場合、
他の電気回路素子との間隔を狭めたり、他の電気回路素
子を回路基板の裏面に搭載させて高密度化を図っていた
りしているが限界が生じてきている。In order to achieve high-density mounting of BGA and CSP,
Although the distance from other electric circuit elements has been reduced, or other electric circuit elements have been mounted on the back surface of the circuit board to increase the density, there has been a limit.
【0017】また、BGA、CSPと他の電気回路素子
とを高速で電気伝送を図る場合、他の電気回路素子との
間隔を狭めたり、他の電気回路素子の裏面に搭載させて
信号を伝送させる回路基板のパターンをできる限り短く
したり、伝送回路シミュレーションで回路パターンのは
いまわし方を決めてノイズのでにくい回路基板にしてい
るが昨今の電気信号の高速化によりこれも限界が生じて
きている。In the case where high-speed electric transmission is performed between the BGA, CSP and another electric circuit element, a signal is transmitted by narrowing the interval between the electric circuit element and the other electric circuit element or mounting the electric circuit element on the back surface of the other electric circuit element. The pattern of the circuit board to be made is made as short as possible, and the circuit pattern is determined by the transmission circuit simulation, and the circuit board is made difficult to generate noise.However, the speeding up of electric signals in recent years has also caused limitations. .
【0018】本発明が解決しようとする課題は、高密度
実装が可能であり、かつ他の電気回路素子との高速な電
気伝送が可能な半導体装置およびその接合構造を提供す
ることにある。An object of the present invention is to provide a semiconductor device capable of high-density mounting and capable of high-speed electric transmission with another electric circuit element, and a bonding structure thereof.
【0019】[0019]
【課題を解決するための手段】本発明者らが鋭意研究を
重ねた結果、半導体装置を2チップ1パッケージ化する
ことにより上記課題が解決されることを見出し、本発明
を完成するに至った。As a result of intensive studies conducted by the present inventors, they have found that the above-mentioned problems can be solved by packaging a semiconductor device into two chips and one package, and have completed the present invention. .
【0020】すなわち、請求項1に記載した本発明は、
両面に複数の電極部を有する回路基板の上面および下面
にそれぞれ半導体チップが電極部と接合されており、下
面の半導体チップが接合された領域の近傍に外部端子で
ある金属球を設けた半導体装置であって、下面に接合す
る半導体チップのアクティブエリアを回路基板側に設け
たことを特徴とする半導体装置に関するものである。That is, the present invention described in claim 1 provides:
A semiconductor device in which a semiconductor chip is bonded to an electrode portion on each of an upper surface and a lower surface of a circuit board having a plurality of electrode portions on both surfaces, and a metal sphere serving as an external terminal is provided near a region on the lower surface where the semiconductor chip is bonded. The present invention relates to a semiconductor device, wherein an active area of a semiconductor chip bonded to a lower surface is provided on a circuit board side.
【0021】また、請求項2に記載した本発明は、上記
半導体装置において、上面に接合する半導体チップのア
クティブエリアを回路基板側に設けたことを特徴とする
ものである。According to a second aspect of the present invention, in the semiconductor device, an active area of a semiconductor chip to be bonded to an upper surface is provided on a circuit board side.
【0022】また、請求項3に記載した本発明は、上記
半導体装置の外部端子である金属球とプリント基板の電
極部がはんだ接合されたことを特徴とする半導体装置の
接合構造に関するものである。According to a third aspect of the present invention, there is provided a bonding structure of a semiconductor device, wherein a metal ball as an external terminal of the semiconductor device and an electrode portion of a printed circuit board are soldered. .
【0023】[0023]
【発明の実施の形態】第1実施形態 第1実施形態を、図1(a)、(b)に示す。図1
(a)は半導体装置1を、図1(b)は半導体装置1が
プリント基板13にはんだ接合された接合構造を示す図
であり、ともに断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIGS. 1A and 1B show a first embodiment. FIG.
FIG. 1A is a diagram illustrating a semiconductor device 1, and FIG. 1B is a diagram illustrating a bonding structure in which the semiconductor device 1 is solder-bonded to a printed circuit board 13, both of which are cross-sectional views.
【0024】まず図1(a)により本発明の半導体装置
1を説明する。First, a semiconductor device 1 of the present invention will be described with reference to FIG.
【0025】本発明の半導体装置1は、上面および下面
に複数の電極部2、10とパターン(不図示)を備えた
回路基板4の上面に半導体チップ5が電極部2に接合さ
れ、回路基板4の下面には半導体チップ6が電極部10
に接合されている。回路基板2の下面には外部端子の電
極部3が設けられ、該電極部3にはんだボールを備える
ことにより、半導体チップ5、6が外部との電気的接続
を図ることができるように構成されている。In a semiconductor device 1 of the present invention, a semiconductor chip 5 is joined to an electrode portion 2 on an upper surface of a circuit board 4 having a plurality of electrode portions 2, 10 and a pattern (not shown) on the upper and lower surfaces. The semiconductor chip 6 has an electrode portion 10
Is joined to. An electrode portion 3 of an external terminal is provided on the lower surface of the circuit board 2, and the electrode portion 3 is provided with a solder ball, so that the semiconductor chips 5, 6 can be electrically connected to the outside. ing.
【0026】外部端子の電極部3の位置は、回路基板4
の下面であり半導体チップ6が搭載された領域の近傍で
ある。なお、半導体チップ6は、そのアクティブエリア
が回路基板4側に接するように搭載されている。本発明
におけるアクティブエリアとは、半導体チップ上に回路
素子が形成されるエリアのことを言う。The position of the electrode portion 3 of the external terminal is
And the vicinity of the region where the semiconductor chip 6 is mounted. The semiconductor chip 6 is mounted so that its active area is in contact with the circuit board 4 side. The active area in the present invention refers to an area where a circuit element is formed on a semiconductor chip.
【0027】半導体チップ6はそのアクティブエリアが
回路基板4側に接するように搭載されているため、回路
基板4の電極部10が半導体チップ6の外形寸法に設置
できることから、はんだボール7の個数が増すことがで
きるので、半導体装置1の多ピン化が可能となる。Since the semiconductor chip 6 is mounted so that its active area is in contact with the circuit board 4 side, since the electrode portions 10 of the circuit board 4 can be set to the outer dimensions of the semiconductor chip 6, the number of solder balls 7 is reduced. Since the number of pins can be increased, the number of pins of the semiconductor device 1 can be increased.
【0028】半導体チップ5と半導体チップ6は、それ
ぞれ樹脂8,11で封止されている。半導体チップ5
は、回路基板4の上面にワイヤボンディングにより電極
2と接合されており、半導体チップ6は、半導体チップ
6に設けたはんだバンプ9と回路基板4の電極部10と
をはんだ接合している。The semiconductor chip 5 and the semiconductor chip 6 are sealed with resins 8 and 11, respectively. Semiconductor chip 5
Is bonded to the electrode 2 on the upper surface of the circuit board 4 by wire bonding, and the semiconductor chip 6 has a solder bump 9 provided on the semiconductor chip 6 and an electrode portion 10 of the circuit board 4 soldered.
【0029】本発明の半導体装置1の製法の一実施形態
を以下に述べる。One embodiment of the method for manufacturing the semiconductor device 1 of the present invention will be described below.
【0030】上面と下面に複数の電極2、10とパター
ンを備え、かつ下面に外部端子の電極部3を設けた回路
基板4の上面に半導体チップ5をワイヤボンディング
し、樹脂8でトランスファー成形する。その後回路基板
4の下面の電極部10にはんだペーストを塗布し、はん
だバンプ9を有する半導体チップ6を位置決め搭載し、
はんだボール7も同時に外部端子の電極部3に搭載し、
リフロー工程ではんだペースト、はんだバンプ9とはん
だボール7を加熱溶融させて接合する。次にはんだペー
ストのフラックスを洗浄により除去し、樹脂11で半導
体チップ6を封止し、半導体装置1を得る。A semiconductor chip 5 is wire-bonded to an upper surface of a circuit board 4 provided with a plurality of electrodes 2 and 10 and a pattern on the upper and lower surfaces and an electrode portion 3 of an external terminal on the lower surface, and is transfer-molded with a resin 8. . Thereafter, a solder paste is applied to the electrode portion 10 on the lower surface of the circuit board 4, and the semiconductor chip 6 having the solder bump 9 is positioned and mounted.
The solder ball 7 is also mounted on the electrode portion 3 of the external terminal at the same time,
In the reflow process, the solder paste, the solder bumps 9 and the solder balls 7 are heated and melted and joined. Next, the flux of the solder paste is removed by washing, and the semiconductor chip 6 is sealed with the resin 11 to obtain the semiconductor device 1.
【0031】次に図1(b)により、半導体装置1とプ
リント基板13との接合構造を説明する。Next, referring to FIG. 1B, a description will be given of a joint structure between the semiconductor device 1 and the printed circuit board 13. FIG.
【0032】まずプリント基板13の電極部12にはん
だペーストを印刷またはディスペンサー方法で塗布した
後に、半導体装置1の電極部3とプリント基板13を位
置決めし、半導体装置1のはんだボール7をプリント基
板13のはんだペースト上に搭載する。その後リフロー
加熱プロセスではんだペーストとはんだボール7を加熱
溶融させ電気機械的接続を図り接合構造を得る。このリ
フロー加熱プロセスで半導体チップ6のはんだバンプ9
も溶融したが、問題はなかった。First, after the solder paste is applied to the electrode portion 12 of the printed board 13 by printing or dispensing, the electrode portion 3 of the semiconductor device 1 and the printed board 13 are positioned, and the solder balls 7 of the semiconductor device 1 are attached to the printed board 13. Mounted on the solder paste. Thereafter, the solder paste and the solder balls 7 are heated and melted by a reflow heating process to achieve electromechanical connection to obtain a joint structure. In this reflow heating process, the solder bumps 9 of the semiconductor chip 6 are formed.
Melted, but there was no problem.
【0033】その後電気特性を測定して、良好な電気特
性が得られた。従来の2チップ2パッケージ構成より、
電磁波ノイズも軽減した。 第2実施形態 第2実施形態を、図2(a)、(b)に示す。図2
(a)は半導体装置26を、図2(b)は半導体装置2
6がプリント基板27にはんだ接合された接合構造を示
す図であり、ともに断面図である。Thereafter, the electric characteristics were measured, and good electric characteristics were obtained. From the conventional two-chip two-package configuration,
Electromagnetic noise has also been reduced. Second Embodiment FIGS. 2A and 2B show a second embodiment. FIG.
2A shows the semiconductor device 26, and FIG.
6 is a view showing a joint structure in which the printed circuit board 27 is joined by soldering, and both are sectional views.
【0034】本発明の半導体装置26は、上面と下面に
複数の電極部29、31とパターン(不図示)を備えさ
らに下面に外部端子の電極部32を設けた回路基板22
の上面に半導体チップ21と下面に半導体チップ23を
搭載している。外部端子の電極部32にはんだボール2
4を設け、外部との接続を図る構成となっている。外部
端子の電極部32の位置は、回路基板22の下面であり
半導体チップ23が搭載された領域の近傍である。The semiconductor device 26 of the present invention comprises a circuit board 22 having a plurality of electrode portions 29, 31 and a pattern (not shown) on the upper and lower surfaces and further having an electrode portion 32 for external terminals on the lower surface.
The semiconductor chip 21 is mounted on the upper surface and the semiconductor chip 23 is mounted on the lower surface. Solder ball 2 is applied to electrode part 32 of the external terminal.
4 for connection to the outside. The position of the electrode portion 32 of the external terminal is on the lower surface of the circuit board 22 and near the region where the semiconductor chip 23 is mounted.
【0035】半導体チップ21と23は、共にそのアク
ティブエリアが回路基板22に接するように搭載されて
いる。The semiconductor chips 21 and 23 are mounted so that their active areas are in contact with the circuit board 22.
【0036】半導体チップ21と半導体チップ23は、
それぞれ樹脂25で封止されている。半導体チップ21
は、半導体チップ21に設けたはんだバンプ28と回路
基板22の電極部29とをはんだ接合している。半導体
チップ23は、実施例1と同様に半導体チップ23に設
けたはんだバンプ30と回路基板22の電極部31とを
はんだ接合している。The semiconductor chip 21 and the semiconductor chip 23
Each is sealed with resin 25. Semiconductor chip 21
Are solder-bonded between the solder bumps 28 provided on the semiconductor chip 21 and the electrode portions 29 of the circuit board 22. In the semiconductor chip 23, the solder bumps 30 provided on the semiconductor chip 23 and the electrode portions 31 of the circuit board 22 are soldered in the same manner as in the first embodiment.
【0037】上面および下面に搭載する半導体チップを
共に、そのアクティブエリアを回路基板22側に接する
ように搭載したことにより、半導体装置26の小型化が
達成できる。The size of the semiconductor device 26 can be reduced by mounting the semiconductor chips mounted on the upper and lower surfaces so that the active areas thereof are in contact with the circuit board 22 side.
【0038】図2(a)に示した半導体装置を製造する
には、例えば回路基板22の上面の半導体チップ21を
第1実施例と同様な方法でリフロー接続させた後に、回
路基板22の下面の半導体チップ23とはんだボール2
4を第1実施例と同様な方法でリフロー接続させ、その
後洗浄によりはんだペーストのフラックスを除去し、半
導体チップ21、23を樹脂25で封止し、半導体装置
26を得るものである。In order to manufacture the semiconductor device shown in FIG. 2A, for example, the semiconductor chip 21 on the upper surface of the circuit board 22 is reflow-connected in the same manner as in the first embodiment, and then the lower surface of the circuit board 22 is manufactured. Semiconductor chip 23 and solder ball 2
4 is subjected to reflow connection in the same manner as in the first embodiment, and thereafter, the flux of the solder paste is removed by washing, and the semiconductor chips 21 and 23 are sealed with a resin 25 to obtain a semiconductor device 26.
【0039】図2(b)に、図2(a)に示した半導体
装置26とプリント基板27との接続構造を示す。図2
(b)の接続構造は第1実施例と同じであるので、説明
を省略する。FIG. 2B shows a connection structure between the semiconductor device 26 and the printed circuit board 27 shown in FIG. FIG.
The connection structure of (b) is the same as that of the first embodiment, and the description is omitted.
【0040】本実施例では、回路基板22の上面と下面
をそれぞれ別にリフロー加工を施したが、回路基板22
の上面の半導体チップ21と下面の半導体チップ23と
はんだボール24を同時にリフロー加熱し、はんだ接合
を行なってもよい。In this embodiment, the upper surface and the lower surface of the circuit board 22 are separately subjected to reflow processing.
The semiconductor chip 21 on the upper surface, the semiconductor chip 23 on the lower surface, and the solder ball 24 may be simultaneously subjected to reflow heating to perform solder joining.
【0041】本例で、半導体装置26は良好な電気特性
が得られた。また半導体装置26と回路基板27に接合
された構造体も良好な電気特性が得られ、従来の2チッ
プ2パッケージ構造のものよりも低ノイズ化が図れた。In this example, the semiconductor device 26 has good electrical characteristics. In addition, the structure joined to the semiconductor device 26 and the circuit board 27 also has good electrical characteristics, and has lower noise than the conventional two-chip two-package structure.
【0042】[0042]
【発明の効果】請求項1に記載された本発明により、従
来の2チップ2パッケージのものが、2チップ1パッケ
ージ化されたことにより、見かけ上1パッケージの部品
点数が減ったことにより、高密度化が得られた。また、
下面に搭載する半導体チップのアクティブエリアを回路
基板側に設けることにより、半導体装置の多ピン化が可
能となる。According to the first aspect of the present invention, the conventional two-chip, two-package package is made into two-chip, one-package, and the apparent number of components in one package is reduced. Densification was obtained. Also,
By providing the active area of the semiconductor chip mounted on the lower surface on the circuit board side, the number of pins of the semiconductor device can be increased.
【0043】また、従来パッケージ間の信号伝達はプリ
ント基板を経由していたが、1パッケージ内で処理可能
で配線長が短くなったことにより、電気信号の遅延が少
なくなり、また低ノイズ化が図れた。このことは電気信
号速度が増せば増すほど顕著な効果が得られた。Conventionally, signal transmission between packages has been performed via a printed circuit board. However, since the signal can be processed in one package and the wiring length is shortened, the delay of electric signals is reduced, and the noise is reduced. It was planned. This has a remarkable effect as the electric signal speed increases.
【0044】請求項2に記載された本発明は、上記効果
に加え、半導体装置の小型化が可能となる。According to the second aspect of the present invention, in addition to the above effects, the size of the semiconductor device can be reduced.
【0045】請求項3に記載した本発明は、高密度実装
および電気信号の高速化と低ノイズ化が可能な接合構造
を提供することができる。According to the third aspect of the present invention, it is possible to provide a bonding structure capable of high-density mounting, high-speed electric signal and low noise.
【図1】(a)は本発明の一実施形態を示す半導体装置
の断面図であり、(b)は本発明の半導体装置とプリン
ト基板との接合構造を示す断面図。FIG. 1A is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view illustrating a bonding structure between the semiconductor device of the present invention and a printed circuit board.
【図2】(a)は本発明の他の一実施形態を示す半導体
装置の断面図であり、(b)は本発明の半導体装置とプ
リント基板との接合構造を示す断面図。FIG. 2A is a cross-sectional view of a semiconductor device showing another embodiment of the present invention, and FIG. 2B is a cross-sectional view showing a joint structure between the semiconductor device of the present invention and a printed circuit board.
【図3】(a)は従来の半導体装置の断面図であり、
(b)は従来の半導体装置とプリント基板との接合構造
を示す断面図。FIG. 3A is a sectional view of a conventional semiconductor device,
FIG. 3B is a cross-sectional view illustrating a conventional bonding structure between a semiconductor device and a printed circuit board.
1 半導体装置 2、10 電極部 3 外部端子の電極部 4 回路基板 5、6 半導体チップ 7 はんだボール 8、11 樹脂 12 電極部 13 プリント基板 26 半導体装置 29、31 電極部 32 外部端子の電極部 22 回路基板 21、23 半導体チップ 24 はんだボール 25 樹脂 27 プリント基板 33 電極部 101 回路基板 102 半導体チップ 103 樹脂 104 電極部 105 はんだボール 106 半導体装置 107 プリント基板 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2, 10 Electrode part 3 External terminal electrode part 4 Circuit board 5, 6 Semiconductor chip 7 Solder ball 8, 11 Resin 12 Electrode part 13 Printed board 26 Semiconductor device 29, 31 Electrode part 32 External terminal electrode part 22 Circuit boards 21, 23 Semiconductor chip 24 Solder balls 25 Resin 27 Printed board 33 Electrode unit 101 Circuit board 102 Semiconductor chip 103 Resin 104 Electrode unit 105 Solder ball 106 Semiconductor device 107 Printed board
Claims (3)
上面および下面にそれぞれ半導体チップが電極部と接合
されており、下面の半導体チップが接合された領域の近
傍に外部端子である金属球を設けた半導体装置であっ
て、下面に接合する半導体チップのアクティブエリアを
回路基板側に設けたことを特徴とする半導体装置。1. A circuit board having a plurality of electrode portions on both surfaces, a semiconductor chip is bonded to an electrode portion on each of an upper surface and a lower surface, and a metal ball as an external terminal is provided near a region on the lower surface where the semiconductor chip is bonded. Wherein an active area of a semiconductor chip bonded to a lower surface is provided on a circuit board side.
ブエリアを回路基板側に設けたことを特徴とする請求項
1に記載の半導体装置。2. The semiconductor device according to claim 1, wherein an active area of the semiconductor chip bonded to the upper surface is provided on the circuit board side.
置の外部端子である金属球とプリント基板の電極部がは
んだ接合されたことを特徴とする半導体装置の接合構
造。3. A bonding structure for a semiconductor device, wherein a metal ball as an external terminal of the semiconductor device according to claim 1 and an electrode portion of a printed circuit board are soldered.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000054537A JP2001244405A (en) | 2000-02-29 | 2000-02-29 | Semiconductor device and its junction structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000054537A JP2001244405A (en) | 2000-02-29 | 2000-02-29 | Semiconductor device and its junction structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001244405A true JP2001244405A (en) | 2001-09-07 |
Family
ID=18575779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000054537A Pending JP2001244405A (en) | 2000-02-29 | 2000-02-29 | Semiconductor device and its junction structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2001244405A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006295156A (en) * | 2005-04-14 | 2006-10-26 | Samsung Electronics Co Ltd | Semiconductor module and method for manufacturing same |
JP2014216650A (en) * | 2013-04-23 | 2014-11-17 | 巨擘科技股▲ふん▼有限公司Princo Corp. | Electric system and core module therefor |
-
2000
- 2000-02-29 JP JP2000054537A patent/JP2001244405A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006295156A (en) * | 2005-04-14 | 2006-10-26 | Samsung Electronics Co Ltd | Semiconductor module and method for manufacturing same |
JP2014216650A (en) * | 2013-04-23 | 2014-11-17 | 巨擘科技股▲ふん▼有限公司Princo Corp. | Electric system and core module therefor |
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