JP2001218239A - Phone interface circuit for digital exchange - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phone interface circuit for a digital exchange that can relieve a load, with respect to transmission processing or reception processing of a processing means. SOLUTION: A processing circuit (CPU) 11 sets control data to a transmission buffer 12, to start transmission start to a transmission control circuit 15. Data are read from the transmission buffer 12 in response to a transmission rate to apply parallel/serial conversion in a parallel/serial(P/S) conversion circuit 13, a 2B+D multiplexer circuit 14 multiplexes the data with voice data, the resulting data are sent to a telephone set. Since the transmission buffer 12 transmits control data to the 2B+D multiplexer 14, without the intervention of the processing circuit 11, the load on the processing circuit 11 with respect to the transmission processing can be relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a telephone interface circuit of a digital exchange, such as a key telephone and a PBX, for transmitting and receiving data to and from a telephone, such as a digital telephone, connected thereto.

[0002]

2. Description of the Related Art As shown in FIG. 3 (a), in a digital telephone interface circuit 30 provided on a digital exchange (not shown) such as a key telephone, a PBX, etc. To a telephone (not shown), two channels of audio data (Bch) and one channel of downlink control data (Dch) to a digital telephone are multiplexed and transmitted. Here, multiplexing is performed with two Bchs and one Dc
This is performed by a 2B + D multiplexing circuit 32 that multiplexes h.

In the conventional system, the processing circuit (CPU) 31 of the digital telephone interface circuit 30 is a Dch
Is transmitted to the 2B + D multiplexing circuit 32 one bit at a time in accordance with the reference clock signal from the transmission rate creation circuit 33 for determining the transmission rate. For example, as shown in FIG. 3 (b), when the transmission rate of the transmission data is 4 Kbps, the transmission data of 1 Byte is transmitted to the 2B + D multiplexing circuit 3 by 1 bit every 4 KHz.
2 had been sent.

In such a system, a processing circuit (CPU) 3
No. 1 requires transmission data to be transmitted in accordance with the transmission rate. Therefore, when trying to increase the transmission rate, there is a problem that the load involved in the transmission processing is significantly increased.

As shown in FIG. 4A, a digital telephone (not shown) receives voice data (not shown) from a digital telephone (not shown) provided to a digital telephone interface circuit 30 provided on a digital exchange (not shown). Two channels (Bch) and one channel of uplink control data (Dch) are multiplexed and transmitted.

In the digital telephone interface circuit 30, the received 2B + D multiplexed data is separated into two Bch and one Dch by a 2B + D separation circuit 41.

Also in this case, in the conventional system, the processing circuit (CPU) in the digital telephone interface circuit 30 is used.
31 synchronizes the received data with the reference clock signal from the transmission rate creation circuit 42 for determining the transmission rate,
It was received from the 2B + D separation circuit 41 for each it. For example, as shown in FIG. 4B, when the transmission rate of the received data is 4 Kbps, the transmission data of 1 Byte is
The signal was read out and received from the 2B + D separation circuit 41 one bit at a time for each Hz.

In such a system, the processing circuit (CPU) 3
No. 1 needs to receive the received data in accordance with the transmission rate. Therefore, when trying to increase the transmission rate, there is a problem that the load related to the reception processing is significantly increased.

[0009]

As described above, the processing circuit (C) of the digital telephone interface circuit 30 is used.
PU) 31 converts the transmission data into 2B according to the transmission rate.
Since it is necessary to transmit to the + D multiplexing circuit 32 and receive from the 2B + D demultiplexing circuit 41 in accordance with the transmission rate, if the transmission rate in transmission or reception is to be increased, the transmission processing of the processing circuit (CPU) 31 Alternatively, there has been a problem that the load related to the reception processing is significantly increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a telephone interface circuit of a digital exchange which can reduce a load relating to transmission processing or reception processing of processing means. Aim.

[0011]

According to the present invention, there is provided a telephone interface circuit of a digital exchange for multiplexing voice data and control data from a processing means by a multiplexing means and transmitting the multiplexed data to a telephone. Transmission buffer means for temporarily storing data output from the processing means between the means and the multiplexing means, and converting parallel data output from the transmission buffer means into serial data and outputting the serial data to the multiplexing means And a transmission control means for controlling the transmission buffer means and the parallel / serial conversion means by a signal from the processing means.

According to such a configuration, if the processing means writes the control data in the transmission buffer means, the data transmission from the transmission buffer means to the multiplexing means is performed without the intervention of the processing means according to the transmission rate. Therefore, the load related to the transmission processing of the processing means can be reduced, and the load on the processing means does not increase significantly even if the transmission rate is increased.

According to a second aspect of the present invention, there is provided a telephone interface circuit of a digital exchange for separating received data from a telephone into voice data and control data by a separating means and inputting the separated control data to a processing means. A serial / parallel conversion means for converting serial data output from the separation means into parallel data between the separation means and the processing means, and transmitting data input from the serial / parallel conversion means to the processing means. It is characterized in that a receiving buffer means for temporarily storing and a receiving control means for controlling the serial / parallel converting means and the receiving buffer means are provided.

According to such a configuration, the control data separated by the separating means is written to the receiving buffer according to the transmission rate, and the processing means outputs the data if the data has been written to the receiving buffer. Reading can be performed. Therefore, the data reception from the demultiplexing unit to the receiving buffer is performed without the intervention of the processing unit according to the transmission rate, so that the load on the reception processing of the processing unit can be reduced, and the processing can be performed even if the transmission rate is increased. The load on the means is not significantly increased.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following drawings, the same symbols indicate the same or corresponding parts.

(First Embodiment) FIG. 1A shows the configuration of a telephone interface circuit of a digital exchange according to a first embodiment of the present invention.

As shown in FIG. 1, a key telephone, a PBX,
And the like, a digital telephone interface circuit 10 provided on the side of a digital exchange (not shown) provides voice data (Bc) from the digital telephone interface circuit 10 to the digital telephone (not shown).
h) Two channels and one channel of downlink control data (Dch) are multiplexed and transmitted. Here, multiplexing is performed by multiplexing two Bchs and one Dch.
This is performed by the B + D multiplexing circuit 14.

The processing circuit (CPU) 11, the transmission buffer 12, and the transmission control circuit 15 are connected via an address bus and a data bus. Parallel / Serial (P /
S) The conversion circuit 13 includes the transmission buffer 1 on the parallel input side.
2, the serial output side is connected to the 2B + D multiplexing circuit 14.

A connection is made so that a buffer read (RD) signal is supplied from the transmission control circuit 15 to the transmission buffer 2 and a parallel data load (LD) signal is supplied to the parallel / serial (P / S) conversion circuit 13. Have been. The transmission rate creation circuit 16 is connected to the transmission control circuit 15 and the parallel / serial (P / S) conversion circuit 13 so that a reference clock (CLK) signal of the transmission rate is supplied.

Next, this operation will be described.

The processing circuit (CPU) 11 writes transmission data (downlink control data) into the transmission buffer 12 and activates the transmission control circuit 15 to start transmission. Processing circuit (C
The PU 11 does not need to adjust this processing to the reference clock of the transmission rate.

The transmission control circuit 15 activated for transmission first outputs a buffer read (RD) signal of transmission data to the transmission buffer 12 in accordance with the reference clock (CLK) signal of the transmission rate. , Parallel transmission data is output to the parallel / serial (P / S) conversion circuit 13.

Thereafter, the transmission control circuit 15 outputs a parallel data load (LD) signal to the parallel / serial (P / S) conversion circuit 13, and the transmission data is taken into the parallel / serial (P / S) conversion circuit 13. . After that,
The parallel / serial (P / S) conversion circuit 13 outputs the transmission data to the 2B + D multiplexing circuit 14 as serial data in accordance with a reference clock (CLK) signal of the transmission rate, and the data is transmitted to the digital telephone.

As described above, in this embodiment, the processing circuit (CPU) 11 sets the transmission data in the transmission buffer 12 and activates the transmission control circuit 15 to start the transmission, whereby the transmission is performed according to the transmission rate. The transmission data is read from the trust buffer 12, the parallel / serial (P / S) conversion circuit 13 performs a parallel / serial conversion operation, and the data is transmitted to the 2B + D multiplexing circuit 14. Since data transmission from the transmission buffer 12 to the 2B + D multiplexing circuit 14 is performed without the intervention of the processing circuit (CPU) 11 according to the transmission rate, even if the transmission rate is increased, the load on the processing circuit (CPU) 11 is remarkable. It does not increase.

Further, the transmission buffer 12 is, for example,
By using an FO (first-in first-out) circuit or the like to increase the number of stages, or by using an empty signal in the transmission buffer 12 as an interrupt signal to the processing circuit (CPU) 11, the transmission of the processing circuit (CPU) 11 is further performed. Load related to processing can be reduced.

For example, as shown in FIG. 1B, when the transmission rate of the transmission data is 16 Kbps, which is four times the conventional rate, and the number of transmission buffers 12 is four, the processing circuit (CPU)
In step 11, the transmission data is set to 4 bytes in the transmission buffer 12 based on the empty signal from the transmission buffer 12, and the transmission control circuit 15 may be activated to start transmission.

(Second Embodiment) FIG. 2A shows the configuration of a telephone interface circuit of a digital exchange according to a second embodiment of the present invention.

As shown in the figure, a digital telephone (not shown) is connected to a digital telephone interface circuit 10 provided on a digital exchange (not shown) side.
After that, two channels of audio data (Bch) and one channel of uplink control data (Dch) are multiplexed and transmitted.

The digital dedicated telephone interface circuit 10 is configured to separate the received 2B + D multiplexed data into two Bchs and one Dch by the 2B + D separation circuit 21.

The 2B + D separating circuit 21 has a serial /
A parallel (S / P) conversion circuit 22 is connected. The parallel output side of the serial / parallel (S / P) conversion circuit 22 is connected to a reception buffer 23. The output side of the receiving buffer 23 is connected to the processing circuit (CPU) 11 via an address bus and a data bus.

The reception control circuit 24 supplies a parallel data latch (Latch) signal to the serial / parallel (S / P) conversion circuit 22 and a buffer write (WR) signal to the reception buffer 23. It is connected. From the transmission rate creation circuit 25, the reception control circuit 24,
The serial / parallel (S / P) conversion circuit 22 is connected so that a reference clock (CLK) signal of a transmission rate is supplied.

Next, this operation will be described.

The data received from the digital telephone is separated into audio data (Bch) and uplink control data (Dch) by the 2B + D separation circuit 21, and the uplink control data (Dch) is serial / parallel (S / P) The serial / parallel conversion is performed by the conversion circuit 22 in accordance with the reference clock (CLK) signal of the transmission rate.

At the same time, serial / parallel (S /
The P) conversion circuit 22 activates the reception control circuit 24 when detecting the presence of the received data, and the reception control circuit 24 transmits the serial / parallel (S / P) conversion circuit 22 at the end of the serial / parallel conversion. And outputs a parallel data latch (Latch) signal to latch parallel received data.

Thereafter, the reception control circuit 24 outputs a buffer write (WR) signal to the reception buffer 23, and the reception data is taken into the reception buffer 23. Processing circuit (C
The PU) 11 monitors the presence / absence of data in the reception buffer 23, and reads out the reception data from the reception buffer 23 if there is data.

Thus, in this embodiment, 2B + D
The received data separated by the separation circuit 21 is converted into a serial / parallel (S / P) conversion circuit 22 according to the transmission rate.
The serial / parallel conversion is performed, and writing to the receiving buffer 23 is performed. The processing circuit (CPU) 11 reads out the data if the received data is written in the receiving buffer 23. Since the data reception from the 2B + D separation circuit 21 to the reception buffer 23 is performed without the intervention of the processing circuit (CPU) 11 according to the transmission rate, the load on the processing circuit (CPU) 11 is significantly increased even if the transmission rate is increased. It does not increase.

The receiving buffer 23 may be multi-staged using a FIFO (first-in first-out) circuit or the like, or the data present signal of the receiving buffer 23 may be used as an interrupt signal to the processing circuit (CPU) 11. Thus, the load related to the reception processing of the processing circuit (CPU) 11 can be further reduced.

For example, as shown in FIG. 2B, when the transmission rate of the received data is 16 Kbps, which is four times the conventional rate, and the number of stages of the receiving buffer 23 is four, the processing circuit (CPU)
Reference numeral 11 may read out 4 bytes of received data from the reception buffer 23 based on the data presence signal from the reception buffer 23.

[0039]

As described above, according to the telephone interface circuit of the digital exchange of the present invention, it is possible to reduce the load related to the transmission processing or the reception processing in the processing means, and to reduce the transmission rate of the transmission data or the reception data. Does not significantly increase the load on the processing means.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the configuration and operation of a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the configuration and operation of a second embodiment of the present invention.

FIG. 3 is a diagram illustrating the configuration and operation of a conventional example.

FIG. 4 is a diagram for explaining the configuration and operation of another conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Digital telephone interface circuit 11 ... Processing circuit (CPU) 12 ... Transmission buffer 13 ... Parallel / serial (P / S) conversion circuit 14 ... 2B + D multiplexing circuit 15 ... Transmission control circuit 16, 25 ... Transmission rate creation circuit 21 2B + D separation circuit 22 Serial / parallel (S / P) conversion circuit 23 Reception buffer 24 Reception control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference)

Claims (2)

[Claims] 1. A telephone interface circuit of a digital exchange for multiplexing voice data and control data from a processing means by a multiplexing means and transmitting the multiplexed data to a telephone, wherein said processing means is provided between said processing means and said multiplexing means. Transmission buffer means for temporarily storing data output from the means, parallel / serial conversion means for converting parallel data output from the transmission buffer means into serial data and outputting the serial data to the multiplexing means, A telephone interface circuit for a digital exchange, further comprising transmission buffer means for controlling the transmission buffer means and the parallel / serial conversion means in accordance with a signal from the means. 2. A telephone interface circuit of a digital exchange which separates received data from a telephone into voice data and control data by a separating means and inputs the separated control data to a processing means. Serial / parallel conversion means for converting serial data output from the demultiplexing means into parallel data, and reception for temporarily storing data input from the serial / parallel conversion means to the processing means; A telephone interface circuit for a digital exchange, comprising: a buffer for receiving data; and a reception controller for controlling the serial / parallel converter and the buffer for reception.