JPH0427230A - Communication equipment for digital auxiliary signal - Google Patents

Communication equipment for digital auxiliary signal

Info

Publication number
JPH0427230A
JPH0427230A JP13183790A JP13183790A JPH0427230A JP H0427230 A JPH0427230 A JP H0427230A JP 13183790 A JP13183790 A JP 13183790A JP 13183790 A JP13183790 A JP 13183790A JP H0427230 A JPH0427230 A JP H0427230A
Authority
JP
Japan
Prior art keywords
signal
circuit
input
signals
auxiliary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13183790A
Other languages
Japanese (ja)
Inventor
Mika Itou
伊藤 美夏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP13183790A priority Critical patent/JPH0427230A/en
Publication of JPH0427230A publication Critical patent/JPH0427230A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To sent the digital auxiliary signals of plural lines including a sound signal with a single transmission line by providing a time division multiplex circuit having a discriminator, a controller, a memory, a multiplexing circuit, and a separating circuit for separating the multiplexing. CONSTITUTION:Input signals including plural sound digital signals inputted from the digital auxiliary signal input terminal 1 of a transmission side are stored tentatively in a memory 2, and simultaneously, a discriminator 3 detects whether the input signal is present thereon or not. A control circuit 4A inputs this result and sends out a control signal to a memory 2A and a multiplexing circuit 5. In the case the discriminator 3 discriminates that the input signal is only one piece, its input signal is outputted as it is to a signal processing part 6. In the case it is discriminated that plural input signals are present thereon, its input signals are stored tentatively in the memory 2A and outputted to the circuit 6. In the circuit 5, in the case the sound digital signal is included in the input signal, a sound input port A and other data input ports B, C are multiplexed by an 8-bit unit and a bit unit, respectively as shown in a separate figure, and a time division multiplexing auxiliary signal is outputted.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はディジタル補助信号用通信装置に関し、特に音
声のディジタル信号を含んだディジタル補助信号を伝送
する通信装置において、単一のディジタル補助信号伝送
路を用いて複数のディジタル補助信号を伝送するディジ
タル補助信号用通信装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a communication device for digital auxiliary signals, and particularly in a communication device for transmitting digital auxiliary signals including audio digital signals, the present invention relates to a communication device for transmitting digital auxiliary signals including a digital audio signal. The present invention relates to a communication device for digital auxiliary signals that transmits a plurality of digital auxiliary signals using a channel.

〔従来の技術〕[Conventional technology]

従来のディジタル補助信号用通信装置は、第2図に示す
ように、送信側のディジタル補助信号入力端子1に入力
された複数列の入力信号は各々のディジタル補助信号の
複数本の伝送路9Aを用いて信号処理回路6に伝送され
る。信号処理回路6は多重化された対向局に向けて送信
される。また、対向局から入力された多重化信号は信号
処理回路6により複数の補助信号に分離され、各々のデ
ィジタル補助信号の複数本の伝送路9Bを用いてディジ
タル補助信号出力端子8より外部に送出される。
In the conventional digital auxiliary signal communication device, as shown in FIG. 2, multiple lines of input signals input to the digital auxiliary signal input terminal 1 on the transmitting side are transmitted through multiple transmission lines 9A for each digital auxiliary signal. The signal is used to be transmitted to the signal processing circuit 6. The signal processing circuit 6 transmits the signal to the multiplexed opposing station. Furthermore, the multiplexed signal input from the opposite station is separated into a plurality of auxiliary signals by the signal processing circuit 6, and sent to the outside from the digital auxiliary signal output terminal 8 using a plurality of transmission lines 9B for each digital auxiliary signal. be done.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のディジタル補助信号用通信装置は、ディ
ジタル補助信号の各入出力端子から信号処理回路にそれ
ぞれ1本ずつディジタル補助信号伝送路を用意する必要
があるので、補助信号入力のない場合には、伝送路が空
きとなり伝送容量が無駄になるという欠点がある。
In the conventional digital auxiliary signal communication device described above, it is necessary to prepare one digital auxiliary signal transmission line from each digital auxiliary signal input/output terminal to the signal processing circuit, so when there is no auxiliary signal input, , the disadvantage is that the transmission path becomes empty and the transmission capacity is wasted.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のディジタル補助信号用通信装置は、送信側では
、複数のディジタル補助信号を並列に入力し、この入力
される補助信号の有無およびその補助信号がデータか音
声かを検出する判別器と、前記補助信号が複数の場合に
それらの信号を記憶するメモリと、前記メモリにより読
み出された各信号列を時分割多重する多重化回路と、前
記判別器の結果により音声のディジタル信号を含む複数
列の入力信号が判定された場合は音声のディジタル信号
は8ビット単位で、他のデータ信号は1ビットごとに時
分割多重するように前記多重化回路を制御する制御回路
と、外部から入力される主信号と前記多重化回路の出力
信号とを1つのフレームに精成する信号処理回路とを有
し、受信側では、対向局から送られて来る主信号と時分
割多重補助信号とを分離する信号処理回路と、この時分
割多重補助信号が複数の補助信号を分離して出力する分
離回路およびメモリ回路とを有する。
The communication device for digital auxiliary signals of the present invention includes, on the transmission side, a discriminator that inputs a plurality of digital auxiliary signals in parallel and detects the presence or absence of the input auxiliary signals and whether the auxiliary signals are data or voice; a memory for storing a plurality of auxiliary signals; a multiplexing circuit for time-division multiplexing each signal string read out by the memory; and a plurality of auxiliary signals including audio digital signals based on the results of the discriminator. When a column input signal is determined, the audio digital signal is time-division multiplexed in 8-bit units, and other data signals are time-division multiplexed in 1-bit units. and a signal processing circuit that combines the main signal sent from the opposite station and the output signal of the multiplexing circuit into one frame, and the receiving side separates the main signal sent from the opposite station and the time division multiplexed auxiliary signal. The time division multiplexed auxiliary signal has a separation circuit and a memory circuit that separates and outputs a plurality of auxiliary signals.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

第1図において、送信側において送信側のディジタル補
助信号入力端子1から入力される複数の音声ディジタル
信号を含む入力信号をメモリ2に一時記憶させると同時
に、判別器3は複数の入力信号の有無を検出する。制御
回路4Aはこの検出結果を入力して、この情報に基づき
メモリ2Aおよび多重化回路5へ制御信号を送出する0
判別器3が入力信号1本のみと検出された場合には、そ
の入力信号がそのまま信号処理部6に出力される。
In FIG. 1, on the transmitting side, an input signal including a plurality of audio digital signals inputted from a digital auxiliary signal input terminal 1 on the transmitting side is temporarily stored in a memory 2, and at the same time, a discriminator 3 detects the presence or absence of a plurality of input signals. Detect. The control circuit 4A inputs this detection result and sends a control signal to the memory 2A and the multiplexing circuit 5 based on this information.
If the discriminator 3 detects only one input signal, that input signal is output as is to the signal processing section 6.

判別器3が複数の入力信号あつと検出された場合には、
その入力信号はメモリ2Aに一時記憶され、伝送速度を
変えずに多重化回路5により多重され、信号処理回路6
に出力される。この時多重化回路5は複数列の入力信号
に音声のディジタル信号が含まれている場合には、第3
図(a)に示すように音声入力ボートAは8ビット単位
で、他のデータ信号は第3図(b)、(c)に示すよう
にデータ入力ボートB、Cはビット単位で多重化され、
第3図(d)に示すような出力ボートYの時分割多重補
助信号が出力される。なお、制御回路4Aは判別器3の
結果に基づいて多重化回路5を制御するように精成され
ている。信号処理回路6では主信号と多重化回路5の出
力である時分割多重された補助信号が1つのフレームを
精成するように処理がなされる。この時フレーム中の制
御用ビットには、補助信号が多重化された場合に、目印
となるフラグ信号も挿入される。
When the discriminator 3 detects that there are multiple input signals,
The input signal is temporarily stored in the memory 2A, multiplexed by the multiplexing circuit 5 without changing the transmission speed, and then multiplexed by the signal processing circuit 6.
is output to. At this time, if the multiplexing circuit 5 includes audio digital signals in the input signals of multiple columns, the multiplexing circuit 5
As shown in Figure 3(a), audio input port A is multiplexed in 8-bit units, and other data signals are multiplexed in bit units for data input ports B and C as shown in Figures 3(b) and (c). ,
A time division multiplexed auxiliary signal of output port Y as shown in FIG. 3(d) is output. Note that the control circuit 4A is refined to control the multiplexing circuit 5 based on the result of the discriminator 3. The signal processing circuit 6 processes the main signal and the time-division multiplexed auxiliary signal, which is the output of the multiplexing circuit 5, to refine one frame. At this time, a flag signal that serves as a mark is also inserted into the control bit in the frame when the auxiliary signal is multiplexed.

一方、受信側においては対向局から送られて来る時分割
多重化補助信号と主信号とが信号処理回路6で分離され
、さらにフラグ信号が制御回路4Bに送出されると、制
御回路4Bはこのフラグ信号によりメモリ2Bおよび分
離回路を制御する。
On the other hand, on the receiving side, the time division multiplexed auxiliary signal and the main signal sent from the opposite station are separated by the signal processing circuit 6, and furthermore, when the flag signal is sent to the control circuit 4B, the control circuit 4B The memory 2B and the separation circuit are controlled by the flag signal.

これにより、送信側の入力状態に応じメモリ2Bより複
数に分離されたディジタル補助信号がディジタル補助信
号出力端子8へ送出される。
Thereby, a plurality of digital auxiliary signals separated from the memory 2B are sent to the digital auxiliary signal output terminal 8 according to the input state on the transmitting side.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は判別器、制御器、メモリ、
多重化回路、多重化を分離する分離回路を有する時分割
多重回路系を備えることにより、音声信号を含む複数列
のディジタル補助信号を単一の伝送路で送ることができ
る。したがって伝送容量を有効に利用することによりさ
らに多量の情報を多重伝送することができるという効果
がある。
As explained above, the present invention includes a discriminator, a controller, a memory,
By providing a time division multiplexing circuit system having a multiplexing circuit and a demultiplexing circuit for demultiplexing, it is possible to send multiple columns of digital auxiliary signals including audio signals through a single transmission path. Therefore, by effectively utilizing the transmission capacity, it is possible to multiplex transmit even more information.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図は従来
のディジタル補助信号用通信装置のブロック図、第3図
(a>、(b)、(c)、(d)は本実施例のディジタ
ル補助信号のタイミングチャートである。 1・・・ディジタル補助信号入力端子、2A、2B・・
・メモリ、3・・・判別器、4A、4B・・・制御回路
、5・・・多重化回路、6・・・信号処理回路、7・・
・分離回路、8・・・ディジタル補助信号出力端子、9
A、9B・・・伝送路。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional digital auxiliary signal communication device, and FIG. It is a timing chart of the digital auxiliary signal of the embodiment. 1...Digital auxiliary signal input terminal, 2A, 2B...
・Memory, 3... Discriminator, 4A, 4B... Control circuit, 5... Multiplexing circuit, 6... Signal processing circuit, 7...
・Separation circuit, 8...Digital auxiliary signal output terminal, 9
A, 9B...Transmission line.

Claims (1)

【特許請求の範囲】[Claims] 送信側では、複数のディジタル補助信号を並列に入力し
、この入力される補助信号の有無およびその補助信号が
データか音声かを検出する判別器と、前記補助信号が複
数の場合にそれらの信号を記憶するメモリと、前記メモ
リにより読み出された各信号列を時分割多重する多重化
回路と、前記判別器の結果により音声のディジタル信号
を含む複数列の入力信号が判定された場合は音声のディ
ジタル信号は8ビット単位で、他のデータ信号は1ビッ
トごとに時分割多重するように前記多重化回路を制御す
る制御回路と、外部から入力される主信号と前記多重化
回路の出力信号とを1つのフレームに構成する信号処理
回路とを有し、受信側では、対向局から送られて来る主
信号と時分割多重補助信号とを分離する信号処理回路と
、この時分割多重補助信号が複数の補助信号を分離して
出力する分離回路およびメモリ回路とを有することを特
徴とするディジタル補助信号用通信装置。
On the transmission side, a discriminator inputs multiple digital auxiliary signals in parallel and detects the presence or absence of the input auxiliary signals and whether the auxiliary signals are data or voice, and a discriminator that detects the presence or absence of the input auxiliary signals and whether the auxiliary signals are data or voice. a multiplexing circuit for time-division multiplexing each signal string read out by the memory; and a multiplexing circuit for time-division multiplexing each signal string read out by the memory; A control circuit that controls the multiplexing circuit so that the digital signal is time-division multiplexed in units of 8 bits and other data signals in units of 1 bit, and a main signal input from the outside and an output signal of the multiplexing circuit. and a signal processing circuit that configures the time division multiplexed auxiliary signal into one frame, and on the receiving side, a signal processing circuit that separates the main signal sent from the opposite station and the time division multiplexed auxiliary signal, and the time division multiplexed auxiliary signal. 1. A communication device for digital auxiliary signals, comprising a separation circuit that separates and outputs a plurality of auxiliary signals, and a memory circuit.
JP13183790A 1990-05-22 1990-05-22 Communication equipment for digital auxiliary signal Pending JPH0427230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13183790A JPH0427230A (en) 1990-05-22 1990-05-22 Communication equipment for digital auxiliary signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13183790A JPH0427230A (en) 1990-05-22 1990-05-22 Communication equipment for digital auxiliary signal

Publications (1)

Publication Number Publication Date
JPH0427230A true JPH0427230A (en) 1992-01-30

Family

ID=15067262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13183790A Pending JPH0427230A (en) 1990-05-22 1990-05-22 Communication equipment for digital auxiliary signal

Country Status (1)

Country Link
JP (1) JPH0427230A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012529817A (en) * 2009-06-12 2012-11-22 アルカテル−ルーセント Variable bit rate equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012529817A (en) * 2009-06-12 2012-11-22 アルカテル−ルーセント Variable bit rate equipment

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