JP2001216800A - 半導体集積回路および半導体集積回路の特性調整方法 - Google Patents

半導体集積回路および半導体集積回路の特性調整方法

Info

Publication number
JP2001216800A
JP2001216800A JP2000023912A JP2000023912A JP2001216800A JP 2001216800 A JP2001216800 A JP 2001216800A JP 2000023912 A JP2000023912 A JP 2000023912A JP 2000023912 A JP2000023912 A JP 2000023912A JP 2001216800 A JP2001216800 A JP 2001216800A
Authority
JP
Japan
Prior art keywords
circuit
signal
adjustment
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000023912A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001216800A5 (enExample
Inventor
Nobuyoshi Wakasugi
信嘉 若杉
Koji Kato
好治 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP2000023912A priority Critical patent/JP2001216800A/ja
Priority to KR1020010004576A priority patent/KR100665632B1/ko
Priority to US09/773,002 priority patent/US6438013B2/en
Publication of JP2001216800A publication Critical patent/JP2001216800A/ja
Publication of JP2001216800A5 publication Critical patent/JP2001216800A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2000023912A 2000-02-01 2000-02-01 半導体集積回路および半導体集積回路の特性調整方法 Pending JP2001216800A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000023912A JP2001216800A (ja) 2000-02-01 2000-02-01 半導体集積回路および半導体集積回路の特性調整方法
KR1020010004576A KR100665632B1 (ko) 2000-02-01 2001-01-31 반도체 집적 회로 및 반도체 집적 회로의 특성 조정 방법
US09/773,002 US6438013B2 (en) 2000-02-01 2001-01-31 Semiconductor integrated circuit and method for adjusting characteristics of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000023912A JP2001216800A (ja) 2000-02-01 2000-02-01 半導体集積回路および半導体集積回路の特性調整方法

Publications (2)

Publication Number Publication Date
JP2001216800A true JP2001216800A (ja) 2001-08-10
JP2001216800A5 JP2001216800A5 (enExample) 2006-09-28

Family

ID=18549994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000023912A Pending JP2001216800A (ja) 2000-02-01 2000-02-01 半導体集積回路および半導体集積回路の特性調整方法

Country Status (3)

Country Link
US (1) US6438013B2 (enExample)
JP (1) JP2001216800A (enExample)
KR (1) KR100665632B1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006008796A1 (ja) * 2004-07-16 2006-01-26 Fujitsu Limited 半導体記憶装置
US7596051B2 (en) 2007-02-15 2009-09-29 Elpida Memory, Inc. Semiconductor memory integrated circuit

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002093197A (ja) * 2000-09-07 2002-03-29 Toshiba Microelectronics Corp 半導体集積回路のテスト回路
KR101008990B1 (ko) * 2008-12-05 2011-01-17 주식회사 하이닉스반도체 버퍼인에이블신호 생성회로 및 이를 이용한 입력회로
US9601193B1 (en) 2015-09-14 2017-03-21 Intel Corporation Cross point memory control

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237567A (en) * 1990-10-31 1993-08-17 Control Data Systems, Inc. Processor communication bus
JP3993717B2 (ja) * 1998-09-24 2007-10-17 富士通株式会社 半導体集積回路装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006008796A1 (ja) * 2004-07-16 2006-01-26 Fujitsu Limited 半導体記憶装置
JPWO2006008796A1 (ja) * 2004-07-16 2008-05-01 富士通株式会社 半導体記憶装置
CN100550196C (zh) * 2004-07-16 2009-10-14 富士通微电子株式会社 半导体存储装置
US7719915B2 (en) 2004-07-16 2010-05-18 Fujitsu Microelectronics Limited Semiconductor memory device including a terminal for receiving address signal and data signal
US7596051B2 (en) 2007-02-15 2009-09-29 Elpida Memory, Inc. Semiconductor memory integrated circuit
US8199605B2 (en) 2007-02-15 2012-06-12 Elpida Memory, Inc Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
US6438013B2 (en) 2002-08-20
KR20010078208A (ko) 2001-08-20
US20010010653A1 (en) 2001-08-02
KR100665632B1 (ko) 2007-01-10

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