JP2001210748A - Semiconductor element, method of checking mounted state and connected state of semiconductor elements and electronic apparatus using semiconductor elements - Google Patents

Semiconductor element, method of checking mounted state and connected state of semiconductor elements and electronic apparatus using semiconductor elements

Info

Publication number
JP2001210748A
JP2001210748A JP2000019823A JP2000019823A JP2001210748A JP 2001210748 A JP2001210748 A JP 2001210748A JP 2000019823 A JP2000019823 A JP 2000019823A JP 2000019823 A JP2000019823 A JP 2000019823A JP 2001210748 A JP2001210748 A JP 2001210748A
Authority
JP
Japan
Prior art keywords
connection means
external connection
semiconductor element
electrically connected
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000019823A
Other languages
Japanese (ja)
Inventor
Toshiyuki Sugitani
俊幸 杉谷
Shigeki Yagi
重樹 八木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000019823A priority Critical patent/JP2001210748A/en
Publication of JP2001210748A publication Critical patent/JP2001210748A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element having no electric influence on semiconductor devices in the semiconductor element when the connected state or mounted state of the semiconductor element to a substrate is inspected by input/output of electric energies to the terminals of the semiconductor element. SOLUTION: Connection terminals 10a, 10b; 20a, 20b, disposed at the corners of a semiconductor element 1 are electrically connected to the semiconductor element inside by inner connecting means 11, 21, and the connection terminals 10a, 10b; 20a, 20b are electrically insulated from semiconductor devices of the semiconductor element 1 or an electric circuit 30 composed of semiconductor devices.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、外部回路との電気
的接続を行う複数の外部接続手段を有した半導体素子
と、その半導体素子を実装した基板において半導体素子
の実装状態の良否の判定を行う判定方法と、半導体素子
の接続手段と基板の配線手段の接続状態の良否の判定を
行う判定方法と、前記半導体素子を用いた電子機器に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of external connection means for making an electrical connection to an external circuit, and a method for judging whether or not a semiconductor element is mounted on a substrate on which the semiconductor device is mounted. The present invention relates to a determination method for performing, a determination method for determining whether or not a connection state between a connection unit of a semiconductor element and a wiring unit of a substrate is good, and an electronic apparatus using the semiconductor element.

【0002】[0002]

【従来の技術】基板に実装される半導体素子において、
実装面積の縮小のために半導体素子の底面に外部回路と
の接続端子を有する半導体素子が、近年、多数見受けら
れる。具体例としては、半導体部品の底面に半球形状の
接続用の端子が方形環状に設けられたボールグリッドア
レイ(BGA)型のパッケージに収められた半導体部品
などが挙げられる。
2. Description of the Related Art In a semiconductor device mounted on a substrate,
In recent years, a large number of semiconductor elements having a connection terminal with an external circuit on the bottom surface of the semiconductor element for reducing the mounting area have been found. As a specific example, there is a semiconductor component housed in a ball grid array (BGA) type package in which hemispherical connection terminals are provided in a square ring on the bottom surface of the semiconductor component.

【0003】また、上記半導体素子を実装した基板にお
いて半導体素子の接続手段と基板の配線手段の接続状態
や実装状態の良否の判定を行う判定方法としては、半導
体素子の接続手段に電気的に接続された基板の配線手段
と基板に設けられた回路のグランドに接続された配線手
段間のインピーダンスの測定を行って、測定されたイン
ピーダンスの値が適正値の範囲内であるか否かによって
実装状態の良否や半導体素子の接続手段と基板の配線手
段との接続状態の良否の判定を行うものがあった。
[0003] Further, as a method of determining the connection state of the connection means of the semiconductor element and the wiring means of the substrate on the board on which the semiconductor element is mounted, and the quality of the mounting state, a method of electrically connecting to the connection means of the semiconductor element is used. Measurement of the impedance between the wiring means of the board and the wiring means connected to the ground of the circuit provided on the board, and the mounting state is determined based on whether or not the measured impedance value is within an appropriate value range. And the quality of the connection between the connecting means of the semiconductor element and the wiring means of the substrate is determined.

【0004】また、ボールグリッドアレイ(BGA)型
のパッケージに収められたROM、RAMやCPU等の
半導体部品が使用された電子機器、たとえば、携帯電話
等が実用化されている。
Further, electronic devices using semiconductor components such as ROM, RAM, and CPU contained in a ball grid array (BGA) type package, for example, mobile phones have been put to practical use.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記の
半導体素子の接続手段は、半導体素子の内部回路に電気
的に接続しているか、半導体素子の内部回路及び他の接
続手段と電気的に絶縁されていたため、半導体素子の内
部回路に電気的影響を及ぼすことなく1つの接続手段に
入力した電気信号を他の接続手段から出力することがで
きなかった。
However, the connection means of the semiconductor element is electrically connected to the internal circuit of the semiconductor element or is electrically insulated from the internal circuit of the semiconductor element and other connection means. Therefore, an electric signal input to one connection means cannot be output from another connection means without having an electric influence on an internal circuit of the semiconductor element.

【0006】また、上記従来の半導体素子を実装した基
板において半導体素子の接続手段と基板の配線手段の実
装状態や接続状態の良否の判定を行う判定方法は、半導
体素子が実装される基板上に、半導体素子の任意の接続
端子に対し半導体素子との接続を確認するための検査用
のランドを設け、そのランドとグランド間の電位やイン
ピーダンスの電気特性の測定によって良否の判定を行う
方法では、検査の際に半導体素子の任意の接続端子に電
気的なエネルギー、たとえば、直流電位を与える必要が
有り、半導体素子の内部の回路にダメージを与え、結果
として、この検査により半導体素子の信頼性を低下させ
てしまうという問題点を有していた。
Further, the above-mentioned conventional method for determining the mounting state of the connection means of the semiconductor element and the wiring means of the substrate on the board on which the semiconductor element is mounted and the quality of the connection state are described on the board on which the semiconductor element is mounted. In a method of providing an inspection land for confirming connection with a semiconductor element to an arbitrary connection terminal of the semiconductor element, and determining a pass / fail by measuring an electric property of a potential or impedance between the land and the ground, At the time of inspection, it is necessary to apply electric energy, for example, a DC potential, to any connection terminal of the semiconductor element, which damages the internal circuit of the semiconductor element, and as a result, the reliability of the semiconductor element is reduced by this inspection. There was a problem that it was lowered.

【0007】また、ボールグリッドアレイ(BGA)型
のパッケージに収められたROM、RAMやCPU等の
半導体部品が使用された電子機器は、その電子機器を落
下するなどして衝撃が加わり、基板がたわんだ場合、ボ
ールグリッドアレイ(BGA)型のパッケージのコーナ
ー部分に位置する接続端子に最も大きなストレスが発生
し、コーナー部分の接続端子から順に半田剥がれによる
接続不良が発生し、電子機器がまったく動作しなくなっ
てしまう場合が有るという問題点を有していた。
Also, electronic devices using semiconductor components such as ROMs, RAMs, and CPUs housed in a ball grid array (BGA) type package are subjected to an impact by dropping the electronic devices or the like, and the substrate is damaged. If it bends, the largest stress will be applied to the connection terminals located at the corners of the ball grid array (BGA) type package, and connection failures will occur from the connection terminals at the corners in order from the connection terminals, and the electronic device will not operate at all. There is a problem that it may not be performed.

【0008】本発明は上記のような問題を解決し、接続
状態や実装状態の良否の検査による信頼性の低下のない
半導体素子と半導体素子の信頼性の低下をなくした実装
状態ならびに接続状態の良否の判定方法と半導体素子の
コーナー部分の接続端子の半田剥がれが発生した場合、
接続不良発生状態として動作可能な半導体装置の提供を
目的としている。
SUMMARY OF THE INVENTION The present invention solves the above-described problems, and provides a semiconductor device which does not have a decrease in reliability by inspecting the connection state and the quality of the mounting state. If the method of judging the pass and fail of solder peeling of the connection terminal at the corner of the semiconductor element,
It is an object of the present invention to provide a semiconductor device operable in a connection failure occurrence state.

【0009】[0009]

【課題を解決するための手段】上記課題を解決するため
に本発明の半導体素子は、外部回路との電気的接続を行
うための複数の外部接続手段と、少なくとも1組の2つ
以上の前記外部接続手段を半導体素子内部で電気的に接
続する内部接続手段と、前記内部接続手段によって電気
的に接続された前記外部接続手段以外の外部接続手段に
電気的に接続された電気回路手段を有し、前記内部接続
手段によって電気的に接続された前記外部接続手段は、
前記電気回路手段と電気的に絶縁されているようにした
ものである。
In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises a plurality of external connection means for making an electrical connection with an external circuit, and at least one set of two or more external connection means. There are internal connection means for electrically connecting the external connection means inside the semiconductor element, and electric circuit means electrically connected to external connection means other than the external connection means electrically connected by the internal connection means. The external connection means electrically connected by the internal connection means,
The electric circuit means is electrically insulated from the electric circuit means.

【0010】この構成により、接続状態や実装状態の良
否の検査による信頼性の低下のない半導体素子を提供す
ることができる。
With this configuration, it is possible to provide a semiconductor device that does not have a decrease in reliability due to inspection of the connection state and the mounting state.

【0011】また、本発明の半導体素子の実装状態の判
定方法は、外部回路との電気的接続を行うための複数の
外部接続手段と、少なくとも1組の2つ以上の前記外部
接続手段を半導体素子内部で電気的に接続する内部接続
手段と、前記内部接続手段によって電気的に接続された
前記外部接続手段以外の外部接続手段に電気的に接続さ
れた電気回路手段を有し、前記内部接続手段によって電
気的に接続された前記外部接続手段は、前記電気回路手
段と電気的に絶縁されていることを特徴とした半導体素
子と、前記内部接続手段によって電気的に接続された前
記外部接続手段毎に電気的に接続され、各々が電気的に
絶縁され、外部から電気的接続が可能な複数の配線手段
を設けた基板において、前記半導体素子を前記基板に実
装し、前記基板に設けられた各々の配線手段間の電気的
導通の有無を検査し、電気的導通が有のとき前記半導体
素子の実装状態が良好であり電気的導通が無のとき実装
状態が不良であると判定するようにしたものである。
Further, according to the present invention, there is provided a method for judging a mounted state of a semiconductor device, comprising: a plurality of external connection means for making an electrical connection to an external circuit; and at least one set of the two or more external connection means. Internal connection means for electrically connecting inside the element, and electric circuit means electrically connected to external connection means other than the external connection means electrically connected by the internal connection means; Wherein the external connection means electrically connected by the means is electrically insulated from the electric circuit means, and the external connection means electrically connected by the internal connection means Electrically connected to each other, each is electrically insulated, in a substrate provided with a plurality of wiring means that can be electrically connected from the outside, the semiconductor element is mounted on the substrate, the substrate Inspection of the presence or absence of electrical continuity between each of the wiring means is performed. When the electrical continuity is present, the mounting state of the semiconductor element is determined to be good, and when the electrical continuity is absent, the mounting state is determined to be defective. It is something to do.

【0012】この構成により、実装状態の良否の判定に
際して半導体素子の信頼性の低下を招くことの無い実装
状態の判定方法を提供することができる。
With this configuration, it is possible to provide a method of determining the mounting state without lowering the reliability of the semiconductor element when determining the quality of the mounting state.

【0013】また、本発明の半導体素子の接続状態の判
定方法は、実装される半導体素子は、外部回路との電気
的接続を行うための複数の外部接続手段と、少なくとも
1組の2つ以上の前記外部接続手段を半導体素子内部で
電気的に接続する内部接続手段と、前記内部接続手段に
よって電気的に接続された前記外部接続手段以外の外部
接続手段に電気的に接続された電気回路手段を有し、前
記内部接続手段によって電気的に接続された前記外部接
続手段は、前記電気回路手段と電気的に絶縁されている
ことを特徴とした半導体素子であって、前記内部接続手
段によって電気的に接続された前記外部接続手段毎に電
気的に接続され、各々が電気的に絶縁され、外部から電
気的接続が可能な複数の配線手段を設けた前記半導体素
子が実装、接続された基板において、前記基板に設けら
れた各々の配線手段間の電気的導通の有無を検査し、電
気的導通が有のとき前記半導体素子の前記接続手段と前
記基板の配線手段の接続状態が良好であり電気的導通が
無のとき前記半導体素子の前記接続手段と前記基板の配
線手段の接続状態が不良であると判定するようにしたも
のである。
Further, in the method for determining the connection state of a semiconductor element according to the present invention, the mounted semiconductor element includes a plurality of external connection means for making an electrical connection to an external circuit, and at least one set of two or more external connection means. Internal connection means for electrically connecting the external connection means inside the semiconductor element, and electric circuit means electrically connected to external connection means other than the external connection means electrically connected by the internal connection means. Wherein the external connection means electrically connected by the internal connection means is electrically insulated from the electric circuit means. The semiconductor element provided with a plurality of wiring means electrically connected to each of the external connection means which are electrically connected, each of which is electrically insulated, and which can be electrically connected from the outside, is mounted and connected. The substrate is inspected for the presence or absence of electrical continuity between the respective wiring means provided on the substrate, and when there is electrical continuity, the connection state between the connection means of the semiconductor element and the wiring means of the substrate is good. And when there is no electrical continuity, it is determined that the connection between the connection means of the semiconductor element and the wiring means of the substrate is defective.

【0014】この構成により、接続状態の良否の判定に
際して半導体素子の信頼性の低下を招くことの無い接続
状態の判定方法を提供することができる。
With this configuration, it is possible to provide a method of determining the connection state without lowering the reliability of the semiconductor element when determining the quality of the connection state.

【0015】また、本発明の電子機器は、少なくとも1
つの底面部に方形環状に複数の外部接続手段を有した半
導体素子が実装された基板を有した電子機器であって、
前記半導体素子は、外部回路との電気的接続を行うため
の複数の外部接続手段と、方形環状に配された前記外部
接続手段の中で各コーナー部分に配された4つの前記外
部接続手段を2つずつ半導体素子内部で電気的に接続す
る2つの内部接続手段を有し、前記基板は、入力された
電圧を検知する検知手段と、すべての前記半導体素子の
内部接続手段によって接続された外部接続手段を電気的
に直列に接続する少なくとも1つの第1の配線手段と、
前記直列に接続された外部接続手段の一方を基板の回路
のグランドに接続する第2の配線手段と、前記直列に接
続された外部接続手段の他方を前記検知手段に接続する
第3の配線手段と、前記第3の配線手段に接続された抵
抗を介して電位を与えるプルアップ手段と、前記検知手
段で検知された電位に応じて装置全体の制御を行う制御
手段とを備え、前記検知手段で検出された電位がグラン
ドレベルでないときに装置全体の動作を前記半導体素子
の接続不良発生時の制御状態に変えるように制御するよ
うにしたものである。
Further, the electronic device of the present invention has at least one
An electronic device having a substrate mounted with a semiconductor element having a plurality of external connection means in a square ring on two bottom portions,
The semiconductor element includes a plurality of external connection means for making an electrical connection with an external circuit, and four of the external connection means arranged in each of the corners among the external connection means arranged in a square ring. The substrate has two internal connection means for electrically connecting two inside each other, and the substrate has a detection means for detecting an input voltage and an external connection connected by the internal connection means of all the semiconductor elements. At least one first wiring means for electrically connecting the connection means in series;
Second wiring means for connecting one of the serially connected external connection means to the ground of a circuit on the substrate; and third wiring means for connecting the other of the serially connected external connection means to the detection means. A pull-up means for applying a potential via a resistor connected to the third wiring means; and a control means for controlling the entire apparatus in accordance with the potential detected by the detection means; When the potential detected in step (1) is not at the ground level, the operation of the entire device is controlled so as to change to the control state when the connection failure of the semiconductor element occurs.

【0016】この構成により、半導体素子のコーナー部
分の接続端子の半田剥がれが発生した場合、接続不良発
生状態として動作可能な半導体装置を提供することがで
きる。
With this configuration, it is possible to provide a semiconductor device that can operate as a connection failure when a connection terminal at a corner of a semiconductor element has been peeled off by solder.

【0017】また、本発明の電子機器は、少なくとも1
つの底面部に方形環状に複数の外部接続手段を有した半
導体素子が実装された基板を有した電子機器であって、
前記半導体素子は、外部回路との電気的接続を行うため
の複数の外部接続手段と、方形環状に配された前記外部
接続手段の中で各コーナー部分に配された4つの前記外
部接続手段を2つずつ半導体素子内部で電気的に接続す
る2つの内部接続手段を有し、前記基板は、入力された
電圧を検知する検知手段と、すべての前記半導体素子の
内部接続手段によって接続された外部接続手段を電気的
に直列に接続する少なくとも1つの第1の配線手段と、
前記直列に接続された外部接続手段の一方を基板の回路
の電源に接続する第2の配線手段と、前記直列に接続さ
れた外部接続手段の他方を前記検知手段に接続する第3
の配線手段と、前記第3の配線手段に接続された抵抗を
介してグランドに接続するプルダウン手段と、前記検知
手段で検知された電位に応じて装置全体の制御を行う制
御手段とを備え、前記検知手段で検出された電位が電源
レベルでないときに装置全体の動作を前記半導体素子の
接続不良発生時の制御状態に変えるように制御するよう
にしたものである。
The electronic device of the present invention has at least one
An electronic device having a substrate mounted with a semiconductor element having a plurality of external connection means in a square ring on two bottom portions,
The semiconductor element includes a plurality of external connection means for making an electrical connection with an external circuit, and four of the external connection means arranged in each of the corners among the external connection means arranged in a square ring. The substrate has two internal connection means for electrically connecting two inside each other, and the substrate has a detection means for detecting an input voltage and an external connection connected by the internal connection means of all the semiconductor elements. At least one first wiring means for electrically connecting the connection means in series;
A second wiring means for connecting one of the serially connected external connection means to a power supply of a circuit on a substrate; and a third wiring means for connecting the other of the serially connected external connection means to the detection means.
Wiring means, pull-down means connected to ground via a resistor connected to the third wiring means, and control means for controlling the entire apparatus according to the potential detected by the detection means, When the potential detected by the detection means is not at the power supply level, the operation of the entire device is controlled to be changed to a control state at the time of occurrence of a connection failure of the semiconductor element.

【0018】この構成により、半導体素子のコーナー部
分の接続端子の半田剥がれが発生した場合、接続不良発
生状態として動作可能な電子機器を提供することができ
る。
With this configuration, it is possible to provide an electronic device that can operate as a connection failure occurrence state when solder peeling of a connection terminal at a corner portion of a semiconductor element occurs.

【0019】[0019]

【発明の実施の形態】本発明の請求項1に記載の発明
は、外部回路との電気的接続を行うための複数の外部接
続手段と、少なくとも1組の2つ以上の外部接続手段を
半導体素子内部で電気的に接続する内部接続手段と、内
部接続手段によって電気的に接続された外部接続手段以
外の外部接続手段に電気的に接続された電気回路手段を
有し、内部接続手段によって電気的に接続された外部接
続手段は、電気回路手段と電気的に絶縁されているよう
にしたものであり、半導体素子の電気回路手段に電気的
エネルギーを与えること無く、上記内部接続手段によっ
て電気的に接続された外部接続手段の1つに電気的エネ
ルギーを与え、他の上記内部接続手段によって電気的に
接続された外部接続手段から電気的エネルギーを出力す
ることができるという作用を有する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS According to a first aspect of the present invention, a plurality of external connection means for making an electrical connection to an external circuit and at least one set of two or more external connection means are provided by a semiconductor. An internal connection means for electrically connecting inside the element, and an electric circuit means electrically connected to external connection means other than the external connection means electrically connected by the internal connection means; The external connection means electrically connected to the electric circuit means is electrically insulated from the electric circuit means of the semiconductor element without applying electric energy to the electric circuit means of the semiconductor element. The electric energy can be supplied to one of the external connection means connected to the external connection means, and the electric energy can be output from the external connection means electrically connected to the other internal connection means. It is having an effect.

【0020】本発明の請求項2に記載の発明は、請求項
1に記載の発明において、半導体素子のすべての外部接
続手段の中で、2つの外部接続手段の物理的距離が最も
大きい外部接続手段またはその近傍の外部接続手段の少
なくとも1つを内部接続手段で他の外部接続手段に電気
的に接続したようにしたものであり、内部接続手段によ
って電気的に接続された外部接続手段間に接続された基
板側の配線手段の電気的導通によって実装状態のずれを
検査する際に、半導体素子が正規の位置から回転するよ
うにずれて実装されていた場合に、半導体素子の外部接
続手段とそれに対応する基板の配線手段の接続用のラン
ド部分のずれが大きく現れるため、その部分の検査を行
うだけで、部品の実装ずれが許容値以下か否かを判別で
きるという作用を有する。
According to a second aspect of the present invention, in the first aspect of the present invention, the external connection in which the physical distance between the two external connection means is the largest among all the external connection means of the semiconductor element. Means or at least one of the external connection means in the vicinity thereof is electrically connected to another external connection means by an internal connection means, and between the external connection means electrically connected by the internal connection means. When inspecting the mounting state shift due to the electrical continuity of the connected wiring means on the substrate side, when the semiconductor element is mounted so as to rotate from a proper position, the external connection means of the semiconductor element and Since the displacement of the connection land portion of the wiring means of the board corresponding thereto appears greatly, it is possible to determine whether the component displacement is below the allowable value only by inspecting the portion. To.

【0021】本発明の請求項3に記載の発明は、請求項
1に記載の発明において、底面部に方形環状に複数の外
部接続手段を有した半導体素子であって、方形環状に配
された外部接続手段の中で、外周、かつ、コーナー部分
またはその近傍に配された少なくとも1つの外部接続手
段を内部接続手段で他の外部接続手段に電気的に接続し
たものであり、半導体素子が使用された機器が落下等の
衝撃によって半導体素子と基板の接続部の半田剥がれに
よる機器の動作不良が発生し、その場所を特定するため
に半導体素子の外部接続手段と基板の対応する配線手段
の接続状態を検査する場合、半導体素子において落下等
の衝撃によって最もはんだ剥がれが発生しやすい、方形
環状に配された外部接続手段の中で、外周、かつ、コー
ナー部分またはその近傍に配された半導体素子の外部接
続手段とそれに対応する基板の配線手段の電気的導通に
よって接続状態の検査が可能となり、効率的に不良発生
個所の特定が行えるという作用を有する。
According to a third aspect of the present invention, in accordance with the first aspect of the present invention, there is provided a semiconductor device having a plurality of external connection means in a rectangular shape on a bottom surface, wherein the semiconductor device is arranged in a rectangular shape. In the external connection means, at least one external connection means disposed on the outer periphery and at or near a corner portion is electrically connected to another external connection means by an internal connection means, and the semiconductor element is used. The dropped device causes an operation failure due to the peeling of the solder between the connection part of the semiconductor element and the board due to an impact such as dropping, and the connection between the external connection means of the semiconductor element and the corresponding wiring means of the board to identify the location. When inspecting the condition, the outer periphery and the corners or the corners of the external connection means arranged in a square ring where the solder is most likely to be peeled off by the impact of a drop or the like on the semiconductor element. Checking the status by electrical conduction of the external connection means and interconnection means of the substrate corresponding to that of the semiconductor elements arranged in the vicinity is possible, such an action identified capable of efficiently failure location.

【0022】本発明の請求項4に記載の発明は、外部回
路との電気的接続を行うための複数の外部接続手段と、
少なくとも1組の2つ以上の外部接続手段を半導体素子
内部で電気的に接続する内部接続手段と、内部接続手段
によって電気的に接続された外部接続手段以外の外部接
続手段に電気的に接続された電気回路手段を有し、内部
接続手段によって電気的に接続された外部接続手段は、
電気回路手段と電気的に絶縁されていることを特徴とし
た半導体素子と、内部接続手段によって電気的に接続さ
れた外部接続手段毎に電気的に接続され、各々が電気的
に絶縁され、外部から電気的接続が可能な複数の配線手
段を設けた基板において、半導体素子を基板に実装し、
基板に設けられた各々の配線手段間の電気的導通の有無
を検査し、電気的導通が有のとき半導体素子の実装状態
が良好であり電気的導通が無のとき実装状態が不良であ
ると判定するようにしたものであり、半導体素子の内部
回路手段に電気的エネルギーを加えること無く実装状態
の良否の判定が可能となる作用を有する。
According to a fourth aspect of the present invention, a plurality of external connection means for making an electrical connection with an external circuit,
An internal connection means for electrically connecting at least one set of two or more external connection means inside the semiconductor element, and an external connection means other than the external connection means electrically connected by the internal connection means. External connection means having electrical circuit means, and electrically connected by internal connection means,
A semiconductor element characterized by being electrically insulated from the electric circuit means, and electrically connected to each of the external connection means electrically connected by the internal connection means, each being electrically insulated and On a substrate provided with a plurality of wiring means that can be electrically connected from, a semiconductor element is mounted on the substrate,
The presence or absence of electrical continuity between the respective wiring means provided on the substrate is inspected, and when the electrical continuity is present, the mounting state of the semiconductor element is good, and when there is no electrical continuity, the mounting state is defective. The determination is performed, and has the effect that the quality of the mounted state can be determined without applying electric energy to the internal circuit means of the semiconductor element.

【0023】本発明の請求項5に記載の発明は、実装さ
れる半導体素子は、外部回路との電気的接続を行うため
の複数の外部接続手段と、少なくとも1組の2つ以上の
外部接続手段を半導体素子内部で電気的に接続する内部
接続手段と、内部接続手段によって電気的に接続された
外部接続手段以外の外部接続手段に電気的に接続された
電気回路手段を有し、内部接続手段によって電気的に接
続された外部接続手段は、電気回路手段と電気的に絶縁
されていることを特徴とした半導体素子であって、内部
接続手段によって電気的に接続された外部接続手段毎に
電気的に接続され、各々が電気的に絶縁され、外部から
電気的接続が可能な複数の配線手段を設けた半導体素子
が実装、接続された基板において、基板に設けられた各
々の配線手段間の電気的導通の有無を検査し、電気的導
通が有のとき半導体素子の接続手段と基板の配線手段の
接続状態が良好であり電気的導通が無のとき半導体素子
の接続手段と基板の配線手段の接続状態が不良であると
判定するようにしたものであり、半導体素子の内部回路
手段に電気的エネルギーを加えること無く接続状態の良
否の判定が可能となる作用を有する。
According to a fifth aspect of the present invention, in the semiconductor device to be mounted, a plurality of external connection means for making an electrical connection with an external circuit and at least one set of two or more external connection means are provided. Internal connection means for electrically connecting the means inside the semiconductor element, and electric circuit means electrically connected to external connection means other than the external connection means electrically connected by the internal connection means; The external connection means electrically connected by the means is a semiconductor element characterized by being electrically insulated from the electric circuit means, and for each external connection means electrically connected by the internal connection means. A semiconductor element provided with a plurality of wiring means which are electrically connected and electrically insulated from each other and which can be electrically connected from the outside is mounted on and connected to each other between the respective wiring means provided on the substrate. of The presence or absence of gas conduction is inspected. When the electric conduction is present, the connection state between the connection means of the semiconductor element and the wiring means of the substrate is good, and when the electric conduction is not present, the connection means of the semiconductor element and the wiring means of the substrate Is determined to be defective, and has the effect of making it possible to determine the quality of the connection state without applying electric energy to the internal circuit means of the semiconductor element.

【0024】また、接続状態の良否の判定に際して半導
体素子の信頼性の低下を招くことの無い接続状態の判定
方法を提供することができる。
Further, it is possible to provide a method of determining the connection state without lowering the reliability of the semiconductor element when determining the quality of the connection state.

【0025】本発明の請求項6に記載の発明は、少なく
とも1つの底面部に方形環状に複数の外部接続手段を有
した半導体素子が実装された基板を有した電子機器であ
って、半導体素子は、外部回路との電気的接続を行うた
めの複数の外部接続手段と、方形環状に配された外部接
続手段の中で各コーナー部分に配された4つの外部接続
手段を2つずつ半導体素子内部で電気的に接続する2つ
の内部接続手段を有し、基板は、入力された電圧を検知
する検知手段と、すべての半導体素子の内部接続手段に
よって接続された外部接続手段を電気的に直列に接続す
る少なくとも1つの第1の配線手段と、直列に接続され
た外部接続手段の一方を基板の回路のグランドに接続す
る第2の配線手段と、直列に接続された外部接続手段の
他方を検知手段に接続する第3の配線手段と、第3の配
線手段に接続された抵抗を介して電位を与えるプルアッ
プ手段と、検知手段で検知された電位に応じて装置全体
の制御を行う制御手段とを備え、検知手段で検出された
電位がグランドレベルでないときに装置全体の動作を半
導体素子の接続不良発生時の制御状態に変えるように制
御するようにしたものであり、半導体素子のコーナー部
分の接続端子の半田剥がれが発生した場合、接続不良発
生状態として動作するという作用を有する。
According to a sixth aspect of the present invention, there is provided an electronic apparatus having a substrate on which at least one bottom surface is provided with a semiconductor element having a plurality of external connection means in a rectangular ring shape, Is a semiconductor device comprising a plurality of external connection means for making an electrical connection with an external circuit, and two external connection means arranged at each corner of the external connection means arranged in a square ring. The substrate has two internal connection means for electrically connecting inside, and the substrate electrically connects in series the detection means for detecting the input voltage and the external connection means connected by the internal connection means of all the semiconductor elements. At least one first wiring means, one of the external connection means connected in series, the second wiring means connecting one of the external connection means to the ground of the circuit on the substrate, and the other of the external connection means connected in series. For detection means A third wiring means, a pull-up means for applying a potential via a resistor connected to the third wiring means, and a control means for controlling the entire apparatus according to the potential detected by the detection means. When the potential detected by the detecting means is not at the ground level, the operation of the entire device is controlled to be changed to the control state at the time of occurrence of a connection failure of the semiconductor element, and the connection of the corner part of the semiconductor element is controlled. When the solder is peeled off from the terminal, the terminal operates as a connection failure occurrence state.

【0026】本発明の請求項7に記載の発明は、少なく
とも1つの底面部に方形環状に複数の外部接続手段を有
した半導体素子が実装された基板を有した電子機器であ
って、半導体素子は、外部回路との電気的接続を行うた
めの複数の外部接続手段と、方形環状に配された外部接
続手段の中で各コーナー部分に配された4つの外部接続
手段を2つずつ半導体素子内部で電気的に接続する2つ
の内部接続手段を有し、基板は、入力された電圧を検知
する検知手段と、すべての半導体素子の内部接続手段に
よって接続された外部接続手段を電気的に直列に接続す
る少なくとも1つの第1の配線手段と、直列に接続され
た外部接続手段の一方を基板の回路の電源に接続する第
2の配線手段と、直列に接続された外部接続手段の他方
を検知手段に接続する第3の配線手段と、第3の配線手
段に接続された抵抗を介してグランドに接続するプルダ
ウン手段と、検知手段で検知された電位に応じて装置全
体の制御を行う制御手段とを備え、検知手段で検出され
た電位が電源レベルでないときに装置全体の動作を半導
体素子の接続不良発生時の制御状態に変えるように制御
するようにしたものであり、半導体素子のコーナー部分
の接続端子の半田剥がれが発生した場合、接続不良発生
状態として動作するという作用を有する。
According to a seventh aspect of the present invention, there is provided an electronic apparatus having a substrate on which a semiconductor element having a plurality of external connection means in a rectangular ring is mounted on at least one bottom surface, Is a semiconductor device comprising a plurality of external connection means for making an electrical connection with an external circuit, and two external connection means arranged at each corner of the external connection means arranged in a square ring. The substrate has two internal connection means for electrically connecting inside, and the substrate electrically connects in series the detection means for detecting the input voltage and the external connection means connected by the internal connection means of all the semiconductor elements. At least one first wiring means, one of the external connection means connected in series, a second wiring means for connecting one of the external connection means to the power supply of the circuit on the substrate, and the other of the external connection means connected in series. Connect to detection means A third wiring means, a pull-down means connected to the ground via a resistor connected to the third wiring means, and a control means for controlling the entire apparatus in accordance with the potential detected by the detection means. When the potential detected by the detecting means is not at the power supply level, the operation of the entire device is controlled to be changed to a control state at the time of occurrence of a connection failure of the semiconductor element, and a connection terminal at a corner portion of the semiconductor element is provided. Has the effect of operating as a connection failure occurrence state when solder peeling occurs.

【0027】(実施の形態1)図1は、本発明の実施の
形態1にかかる半導体素子の平面図である。図1におい
て、1は本発明の半導体素子であり、部品底面に外周1
辺12個、内周10個の総計80個の外部回路に接続す
るための方形環状に配された外部接続手段である接続端
子を有する。10a、10b、20a、20bは、半導
体素子1の方形環状に配された接続端子のうち各コーナ
ー部分に配置された接続端子である。11は、接続端子
10aと接続端子10bを半導体素子1内部で接続する
ための内部接続手段である。同様に、21は、接続端子
20aと接続端子20bを半導体素子1内部で接続する
ための内部接続手段である。30は半導体素子1の電気
的動作を決める電気回路であり、半導体デバイスや半導
体デバイスを用いた電気回路で構成され、外部接続手段
である接続端子のうち10a、10b、20a、20b
以外の接続端子と電気的に接続されている。
(First Embodiment) FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor element of the present invention,
It has connection terminals as external connection means arranged in a square ring for connection to a total of 80 external circuits with 12 sides and 10 inner circumferences. 10a, 10b, 20a, and 20b are connection terminals arranged at each corner of the connection terminals arranged in a square ring of the semiconductor element 1. Reference numeral 11 denotes an internal connection means for connecting the connection terminals 10a and 10b inside the semiconductor element 1. Similarly, reference numeral 21 denotes internal connection means for connecting the connection terminals 20a and 20b inside the semiconductor element 1. Reference numeral 30 denotes an electric circuit which determines the electric operation of the semiconductor element 1, which is constituted by a semiconductor device or an electric circuit using the semiconductor device, and includes 10a, 10b, 20a, and 20b among connection terminals which are external connection means.
Are electrically connected to other connection terminals.

【0028】次に、以上のように構成された半導体素子
の動作に付いて説明を行う。半導体素子1の接続端子1
0aに電気的エネルギーたとえば直流電位を加えた場
合、その電気的エネルギーは、内部接続手段11を通り
接続端子10bから出力される。同様に、半導体素子1
の接続端子20aに電気的エネルギーたとえば直流電位
を加えた場合、その電気的エネルギーは、内部接続手段
21を通り接続端子20bから出力される。この時、接
続端子10a、10b、20a、20b及び内部接続手
段11,21は半導体素子1の電気回路30とは、電気
的に分離された構成になっており、接続端子10a、2
0aから加えられた電気的エネルギーが電気回路30に
影響を及ぼすことはない。
Next, the operation of the semiconductor device configured as described above will be described. Connection terminal 1 of semiconductor element 1
When electric energy, for example, a DC potential, is applied to Oa, the electric energy is output from the connection terminal 10b through the internal connection means 11. Similarly, the semiconductor element 1
When electrical energy, for example, a DC potential, is applied to the connection terminal 20a, the electrical energy is output from the connection terminal 20b through the internal connection means 21. At this time, the connection terminals 10a, 10b, 20a, 20b and the internal connection means 11, 21 are electrically separated from the electric circuit 30 of the semiconductor element 1, and the connection terminals 10a,
The electric energy added from 0a does not affect the electric circuit 30.

【0029】図2は本発明の実施の形態1にかかる半導
体素子の底面図、図3は本発明の実施の形態1にかかる
半導体素子の側面図である。図2及び図3に示すよう
に、半導体素子1は、部品底面に外周1辺12個、内周
10個の総計80個の外部回路に接続するための方形環
状に配された外部接続手段である接続端子を有し、内部
接続手段に接続される接続端子10a、10b、20
a、20bは、半導体素子1の方形環状に配された接続
端子のうち各コーナー部分に配置されている。
FIG. 2 is a bottom view of the semiconductor device according to the first embodiment of the present invention, and FIG. 3 is a side view of the semiconductor device according to the first embodiment of the present invention. As shown in FIGS. 2 and 3, the semiconductor element 1 is a square ring-shaped external connection means for connecting to a total of 80 external circuits of 12 outer sides and 10 inner sides on the bottom surface of the component. Connection terminals 10a, 10b, 20 having certain connection terminals and connected to internal connection means
Reference numerals a and 20b are arranged at respective corners of the connection terminals arranged in a square ring of the semiconductor element 1.

【0030】なお、図2に示すような半導体部品の底面
に半球形状の接続用の端子が方形環状に設けられたボー
ルグリッドアレイ(BGA)型のパッケージに収められ
た半導体部品においては、半導体素子の電気回路が構成
されたウェハーを外部接続用の接続端子が設けられた基
板上に配し、ウェハー上の回路部分と基板の接続端子に
つながる配線ランドをワイヤーで接続するように構成さ
れているが、本実施の形態における内部接続手段は、半
導体素子の各コーナー部分の接続端子をウェハーが載せ
られた基板上の配線パターンで直接接続するか、半導体
素子の各コーナー部分の接続端子につながる配線ランド
間をワイヤーで接続するようにして構成する。
As shown in FIG. 2, in a semiconductor component housed in a ball grid array (BGA) type package in which hemispherical connection terminals are provided in a square ring on the bottom surface of the semiconductor component as shown in FIG. Is arranged on a substrate provided with connection terminals for external connection, and a circuit land on the wafer and a wiring land connected to the connection terminal of the substrate are connected by wires. However, the internal connection means in the present embodiment is either a method of directly connecting the connection terminal of each corner of the semiconductor element with a wiring pattern on a substrate on which a wafer is mounted, or a method of connecting a connection terminal of each corner of the semiconductor element. The lands are connected by wires.

【0031】(実施の形態2)図4は、本発明の実施の
形態2にかかる半導体素子の実装状態ならびに接続状態
を判定する検査装置の概略構成図である。以下、図4を
用いて、動作の説明を行う。
(Embodiment 2) FIG. 4 is a schematic configuration diagram of an inspection apparatus for judging a mounting state and a connection state of a semiconductor device according to Embodiment 2 of the present invention. Hereinafter, the operation will be described with reference to FIG.

【0032】図4において、1は底面に外部接続用の端
子が設けられた半導体素子であり、部品底面に外部接続
端子を有する。10a、10b、20a、20bは半導
体素子1の底面に設けられた外部接続端子の内本発明の
検査に用いるための接続端子である。200は半導体素
子1が実装されるプリント基板であり、半導体素子1の
底面に設けられた外部接続端子に対応した接続用の配線
パターンを含む各回路の配線パターンを有する。210
a、210b、220a、220bはプリント基板20
0上に設けられた半導体素子1の外部接続端子に接続さ
れる配線パターンの内、実施の形態1で説明した半導体
素子の検査に用いるために接続端子10a、10b、2
0a、20bに接続される検査用配線パターンであり、
接続端子10a、10b、20a、20bに接続するた
めのランド部と半導体素子1を実装後の検査の際に外部
から電気的な接続が可能となるランド部とを有する。3
00は直流的な導通の検査を行う検査装置である。30
1a、301bは、検査装置300の入力部である。検
査装置300の入力部301a、301bを被検査物に
接触させると、入力部301a、301b間に接続され
た部分が直流的に導通していた場合、検査装置300
は、入力部301a、301b間に接続された部分が直
流的に導通していたことを表示する。
In FIG. 4, reference numeral 1 denotes a semiconductor element having a terminal for external connection provided on the bottom surface, and has an external connection terminal on the bottom surface of the component. Reference numerals 10a, 10b, 20a, and 20b denote external connection terminals provided on the bottom surface of the semiconductor element 1 for use in the inspection of the present invention. Reference numeral 200 denotes a printed circuit board on which the semiconductor element 1 is mounted, and has a wiring pattern of each circuit including a wiring pattern for connection corresponding to an external connection terminal provided on the bottom surface of the semiconductor element 1. 210
a, 210b, 220a, 220b are printed circuit boards 20
Of the wiring patterns connected to the external connection terminals of the semiconductor element 1 provided on the semiconductor chip 1, the connection terminals 10a, 10b, and 2 are used for the inspection of the semiconductor element described in the first embodiment.
0a, 20b are wiring patterns for inspection,
It has lands for connecting to the connection terminals 10a, 10b, 20a, and 20b, and lands that allow external electrical connection at the time of inspection after mounting the semiconductor element 1. Three
Reference numeral 00 denotes an inspection device for inspecting DC conduction. 30
1a and 301b are input units of the inspection device 300. When the input portions 301a and 301b of the inspection device 300 are brought into contact with the object to be inspected, if the portion connected between the input portions 301a and 301b conducts DC, the inspection device 300
Indicates that a portion connected between the input units 301a and 301b is DC-conductive.

【0033】なお、半導体素子1は、簡略化のために接
続端子の数を変えて表示したが、実施の形態1の半導体
素子と同様の構成であり、部品底面に方形環状に配置さ
れた接続端子の内、各コーナー部分に配された接続端子
10a、10b、20a、20bは、接続端子10aと
接続端子10b、接続端子20aと接続端子20bが共
に半導体素子1内部で内部接続手段により電気的に接続
されており、また、接続端子10a、10b、20a、
20bは、半導体素子1の内部の電気回路とは電気的に
分離されている。
Although the semiconductor element 1 is shown with the number of connection terminals changed for simplicity, it has the same configuration as the semiconductor element of the first embodiment, and the connection elements arranged in a square ring on the bottom surface of the component are shown. Of the terminals, the connection terminals 10a, 10b, 20a, and 20b disposed at the corners are electrically connected to each other by the internal connection means inside the semiconductor element 1 in which the connection terminals 10a and 10b and the connection terminals 20a and 20b are both connected. And connection terminals 10a, 10b, 20a,
20b is electrically separated from the electric circuit inside the semiconductor element 1.

【0034】次に半導体素子1がプリント基板200に
実装された後に、検査装置300を用いて検査を行う方
法を説明する。半導体素子1をプリント基板200に実
装後、検査を行う場合、検査装置300の入力部301
a、301bの一方を配線パターン210aに、他方を
検査用配線パターン210bの検査用のランド部に順に
接続し、導通試験を行う。同様に、検査装置300の入
力部301a、301bの一方を配線パターン220a
に、他方を検査用配線パターン220bの検査用のラン
ド部に接続し、導通試験を行う。210aと210b、
220aと220b間が直流的に導通していた場合、半
導体素子100がプリント基板200に正しく実装接続
されたと判断する。
Next, a method of performing an inspection using the inspection apparatus 300 after the semiconductor element 1 is mounted on the printed circuit board 200 will be described. When performing inspection after mounting the semiconductor element 1 on the printed circuit board 200, the input unit 301 of the inspection apparatus 300
a and 301b are sequentially connected to the wiring pattern 210a, and the other is connected to the inspection land portion of the inspection wiring pattern 210b, and a continuity test is performed. Similarly, one of the input units 301a and 301b of the inspection apparatus 300 is connected to the wiring pattern 220a.
Then, the other is connected to the inspection land portion of the inspection wiring pattern 220b, and a continuity test is performed. 210a and 210b,
When DC conduction occurs between 220a and 220b, it is determined that semiconductor element 100 has been correctly mounted and connected to printed circuit board 200.

【0035】上記実施の形態に示すよう、検査用の接続
端子を方形環状に配された接続端子の内、接続端子間を
結ぶ物理的距離が最も大きくなる外周の各コーナー部の
接続端子を検査用の端子に選ぶことによって、半導体素
子が縦、横、あるいは回転するようにずれて実装された
場合、検査用の各コーナーの接続端子は、そのずれの影
響を最も多く受けるので、該当端子の検査によって実装
状態のずれが適正値以下か否かを簡単に判断することが
できる。また、機器の落下等によって半導体素子を基板
に接続している半田が剥がれ接続不良がおきた場合にお
いても、検査用の接続端子を方形環状に配された接続端
子の内、外周の各コーナー部の接続端子を検査用の端子
に選ぶことによって、該当端子が、機器の落下の際に生
じる基板のたわみによる応力をもっとも大きく受ける部
分になり、半田が剥がれによる接続不良が発生しやすい
ため、該当端子の接続状態を確認することによって、半
田剥がれがおきた個所の特定が容易になる。
As shown in the above embodiment, the connection terminals for inspection are inspected from among the connection terminals arranged in a square ring, at the outer peripheral corners where the physical distance connecting the connection terminals is the largest. If the semiconductor device is mounted vertically, horizontally, or rotationally displaced by selecting the terminal for inspection, the connection terminal at each corner for inspection is most affected by the deviation, so the terminal Inspection makes it possible to easily determine whether or not the deviation of the mounting state is equal to or less than an appropriate value. In addition, even when the solder connecting the semiconductor element to the substrate is peeled off due to a drop of the device or the like, and a connection failure occurs, the connection terminals for inspection are arranged at each corner of the outer periphery of the connection terminals arranged in a square ring. By selecting the connection terminal as the inspection terminal, the corresponding terminal becomes the part that receives the largest stress due to the bending of the board that occurs when the equipment falls, and the connection failure due to the peeling of the solder is likely to occur. By confirming the connection state of the terminals, it is easy to identify the place where the solder has peeled off.

【0036】(実施の形態3)図5は、本発明の実施の
形態3にかかる半導体素子の実装状態ならびに接続状態
を判定する検査装置の回路図である。以下、図5を用い
て、動作の説明を行う。
(Embodiment 3) FIG. 5 is a circuit diagram of an inspection apparatus for judging a mounting state and a connection state of a semiconductor device according to Embodiment 3 of the present invention. Hereinafter, the operation will be described with reference to FIG.

【0037】図5において、500は装置全体の制御を
行う制御部である。制御部500の501,502,5
03,504は、実施の形態1にて説明した半導体素子
の検査を行うための端子であり、501と502,50
3と504が部品内部で接続されている。509は制御
部500の入力ポートであり、入力された信号の電位が
Hi、すなわち電源電圧レベルかLow、すなわちグラ
ンドレベルかを検知する。600は、メモリであり、装
置の動作を決定するプログラムが記憶されている。メモ
リ600の601,602,603,604は、実施の
形態1で説明した半導体素子の検査を行うための端子で
あり、601と602,603と604が部品内部で接
続されている。700は、プルアップ用の抵抗であり、
一方が電源に接続され他方が制御部500の端子501
及び入力ポート509に接続されている。800は表示
部であり、制御部500からの制御に従い表示を行う。
なお、図5に示すように、制御部500、メモリ60
0、表示部800は、相互間に接続され、また、電源、
グランド等に接続されているが詳細な説明は省略する。
In FIG. 5, reference numeral 500 denotes a control unit for controlling the entire apparatus. 501, 502, 5 of the control unit 500
Reference numerals 03 and 504 denote terminals for testing the semiconductor element described in the first embodiment.
3 and 504 are connected inside the component. An input port 509 of the control unit 500 detects whether the potential of the input signal is Hi, that is, the power supply voltage level or Low, that is, the ground level. Reference numeral 600 denotes a memory in which a program for determining an operation of the apparatus is stored. Reference numerals 601, 602, 603, and 604 of the memory 600 are terminals for testing the semiconductor device described in the first embodiment, and 601, 602, 603, and 604 are connected inside the component. 700 is a pull-up resistor,
One is connected to a power supply and the other is a terminal 501 of the control unit 500.
And the input port 509. Reference numeral 800 denotes a display unit, which performs display according to control from the control unit 500.
Note that, as shown in FIG.
0, the display unit 800 is connected to each other,
Although it is connected to a ground or the like, a detailed description is omitted.

【0038】図6は、本発明の実施の形態3にかかる半
導体素子の実装状態ならびに接続状態を判定する検査装
置における処理の流れを示すフローチャートである。
FIG. 6 is a flowchart showing a flow of processing in the inspection device for determining the mounting state and the connection state of the semiconductor device according to the third embodiment of the present invention.

【0039】以下、図5に示す回路の動作についての説
明を、図6に示したフローチャートを参照して行う。
The operation of the circuit shown in FIG. 5 will be described below with reference to the flowchart shown in FIG.

【0040】制御部500、メモリ600の検査用端子
は、端子504と端子603、端子602と端子60
4、端子502と端子601がそれぞれ外部の配線によ
って接続されている。また、端子504はグランドに接
続され、端子501はプルアップ用の抵抗700と入力
ポート509に外部の配線によって接続されている。上
記接続によって、通常入力ポート509にはLowレベ
ル(グランドレベル)が入力されている。制御部500
は、入力ポート509がLowレベルであるとき、正常
状態であると判断し、ステップaよりステップbへ移行
し、メモリ600の中に記憶された正常状態時のプログ
ラムに沿って装置全体の制御を行う。
The inspection terminals of the control unit 500 and the memory 600 include terminals 504 and 603, and terminals 602 and 60.
4. The terminal 502 and the terminal 601 are respectively connected by external wiring. The terminal 504 is connected to the ground, and the terminal 501 is connected to the pull-up resistor 700 and the input port 509 by external wiring. Due to the above connection, a low level (ground level) is input to the normal input port 509. Control unit 500
Determines that the input port 509 is in the normal state when the input port 509 is at the low level, shifts from step a to step b, and controls the entire apparatus in accordance with the normal state program stored in the memory 600. Do.

【0041】端子501,502,503,504,6
01,602,603,604の内の少なくとも1つと
外部の配線が切断された場合、すなわち、部品の半田付
け部分が剥がれ部品の端子と基板の配線パターン間の接
続が不良になった場合、入力ポート509に入力される
信号はHi、すなわち電源電圧レベルとなる。制御部5
00は、入力ポート509がHi(電源電圧レベル)に
なると、部品の端子と基板の配線パターン間の接続に接
続不良が発生したと判断し、ステップaよりステップc
へ移行し、異常状態の制御を開始し、メモリ600の中
に記憶された異常状態時のプログラムにそって装置全体
の制御を行う。異常状態の制御の例であるが、ステップ
dに示すように制御部500は、表示部800に異常状
態、すなわち、部品の接続不良発生を表示し、使用者に
部品の接続不良の発生を通知する。
Terminals 501, 502, 503, 504, 6
01, 602, 603, and 604, and external wiring is cut, that is, when the soldering part of the component is peeled off and the connection between the terminal of the component and the wiring pattern of the board becomes defective, the input is performed. The signal input to port 509 is Hi, that is, the power supply voltage level. Control unit 5
When the input port 509 becomes Hi (power supply voltage level), it is determined that a connection failure has occurred in the connection between the terminal of the component and the wiring pattern on the board.
Then, control of an abnormal state is started, and control of the entire apparatus is performed according to a program for an abnormal state stored in the memory 600. In the example of the control of the abnormal state, as shown in step d, the control unit 500 displays the abnormal state, that is, the occurrence of the connection failure of the component on the display unit 800, and notifies the user of the occurrence of the connection failure of the component. I do.

【0042】端子501,502,503,504,6
01,602,603,604の部品における望ましい
配置は、実施の形態2で述べたように、BGAパッケー
ジに納めされた部品においては、検査用の端子を方形環
状に配された接続端子の内、外周の各コーナー部の接続
端子を検査用の端子に選ぶことによって、該当端子が、
機器の落下の際に生じる基板のたわみによる応力を最も
大きく受ける部分になり、半田が剥がれによる接続不良
が発生しやすいため、より効果的に異常状態の検出が可
能となる。
Terminals 501, 502, 503, 504, 6
As described in the second embodiment, the desirable arrangement of the components 01, 602, 603, and 604 is as follows. In the components housed in the BGA package, the terminals for inspection are selected from the connection terminals arranged in a square ring. By selecting the connection terminal at each corner of the outer periphery as a terminal for inspection,
This is the part that receives the greatest stress due to the deflection of the board that occurs when the equipment falls, and the connection failure due to the peeling of the solder is likely to occur, so that the abnormal state can be detected more effectively.

【0043】なお、上記実施の形態では、端子503を
グランドに、端子501を電源端子に接続されたプルア
ップ抵抗に接続し、入力ポートにHiが入力されたとき
を異常状態と判断する例を述べたが、端子503を電源
に、端子503をグランドに接続されたプルダウン抵抗
に接続し、入力ポートにLowが入力されたときを異常
状態と判断する方法も可能である。
In the above embodiment, the terminal 503 is connected to the ground, the terminal 501 is connected to the pull-up resistor connected to the power supply terminal, and when Hi is input to the input port, an abnormal state is determined. As described above, a method is also possible in which the terminal 503 is connected to a power supply and the terminal 503 is connected to a pull-down resistor connected to the ground, and when a Low is input to the input port is determined as an abnormal state.

【0044】また、上記実施の形態1にて説明した半導
体素子を携帯電話に用いた場合の動作に付いて説明を行
う。近年の携帯電話は、小型化が進んでおり、制御用の
CPUやROM、RAM等でBGAパッケージに収めら
れた半導体部品が多く用いられている。携帯電話は、持
ち歩いて使用するため、落下させてしまう場合が多く、
BGAパッケージの部品の半田剥がれによる故障が多く
発生している。製造者は、携帯電話の信頼性を向上させ
るため、半田剥がれが発生しやすいCPUやROM、R
AM等のBGAパッケージの部品のコーナー部分の端子
を、部品の動作に影響しないノンコネクトの端子にする
などしてBGAパッケージの部品の半田剥がれによる故
障の減少を図っている。しかしながら、落下を繰り返し
てしまい、半田剥がれの障害発生端子がノンコネクトの
端子以外に及んだとき、携帯電話はまったく動作できな
い状態となり、基板交換による修理が行われ、使用者が
登録した電話帳等の情報を修理後の携帯電話に移し替え
ることが困難であった。一方、携帯電話に本発明を応用
した場合、携帯電話の半田剥がれが発生しやすいCPU
やROM、RAM等のBGAパッケージの部品のコーナ
ー部分の端子に障害が発生した時点で、その表示部に障
害発生を知らせるメッセージを出力し使用者に通知す
る。使用者は、ここで修理を依頼すると、基板交換によ
って修理する際、障害が発生した基板は、CPUやRO
M、RAM等の動作は可能であるため、電話帳等の情報
を旧基板から読み出し、交換用の基板に書き込むことが
可能となり、電話帳等の情報をなくすこと無く修理品を
手にすることが可能となる。
The operation when the semiconductor device described in the first embodiment is used for a mobile phone will be described. In recent years, mobile phones have been reduced in size, and semiconductor components housed in a BGA package, such as a control CPU, ROM, and RAM, are often used. Mobile phones are often dropped because they are carried around.
Many failures due to solder peeling of BGA package components have occurred. In order to improve the reliability of the mobile phone, the manufacturer has proposed a CPU, ROM, R
The failure attributable to solder peeling of the components of the BGA package is reduced by, for example, changing the terminals at the corners of the components of the BGA package such as AM to non-connect terminals that do not affect the operation of the components. However, when the device repeatedly drops and the solder peeling failure occurs beyond the non-connect terminal, the mobile phone cannot operate at all, the board is repaired by replacing the board, and the telephone directory registered by the user is used. It is difficult to transfer such information to a mobile phone after repair. On the other hand, when the present invention is applied to a mobile phone, a CPU in which solder peeling of the mobile phone is likely to occur.
When a failure occurs in a terminal of a corner portion of a BGA package component such as a ROM, a RAM, or the like, a message notifying the occurrence of the failure is output to the display unit to notify the user. When the user requests a repair here, when the repair is performed by replacing the board, the failed board is replaced by the CPU or RO.
Since the operation of M, RAM, etc. is possible, it is possible to read the information such as the telephone directory from the old board and write it on the replacement board, and to obtain the repaired product without losing the information such as the telephone directory. Becomes possible.

【0045】[0045]

【発明の効果】以上のように本発明によれば、半導体素
子において少なくとも1組の2つの外部接続端子が電気
的に導通するように構成し、それらの外部接続端子が、
半導体素子内部の半導体デバイスや半導体デバイスを用
いた電気回路と電気的に絶縁されたように構成すること
により、半導体素子内部の半導体デバイスや半導体デバ
イスを用いた電気回路に電気的エネルギーを加えること
なく、半導体素子内部の半導体デバイスや半導体デバイ
スを用いた電気回路と電気的に絶縁された外部接続端子
から電気的エネルギー入出力することが可能となり、半
導体素子の実装状態や接続状態の検査において、半導体
素子の安全性が向上するという効果を有する。
As described above, according to the present invention, in a semiconductor device, at least one set of two external connection terminals is configured to be electrically conductive, and these external connection terminals are
By being configured to be electrically insulated from the semiconductor device inside the semiconductor element and the electric circuit using the semiconductor device, the electric energy is not applied to the semiconductor device inside the semiconductor element and the electric circuit using the semiconductor device. It is possible to input and output electrical energy from an external connection terminal that is electrically insulated from the semiconductor device inside the semiconductor element or an electric circuit using the semiconductor device. This has the effect of improving the safety of the element.

【0046】さらに、半導体素子内部の半導体デバイス
や半導体デバイスを用いた電気回路と電気的に絶縁され
各々が接続された外部接続端子を前記半導体素子のすべ
ての外部接続端子の中で、2つの外部接続端子の物理的
距離が最も大きくなる場所に配することにより、半導体
素子内部の半導体デバイスや半導体デバイスを用いた電
気回路と電気的に絶縁され各々が接続された外部接続端
子が、実装される基板の所定の位置のランドと接続して
いるかどうかを検査することにより、該当部品が正しい
位置に実装されたか否かを判断することにより実装状態
の検査が可能となり、実装状態の検査の作業性が向上す
るという効果を有する。
Further, an external connection terminal electrically insulated from the semiconductor device inside the semiconductor element and an electric circuit using the semiconductor device and connected to each other is connected to two external connection terminals among all the external connection terminals of the semiconductor element. By arranging the connection terminals at the location where the physical distance is the largest, the external connection terminals which are electrically insulated from the semiconductor device inside the semiconductor element and the electric circuit using the semiconductor device and connected to each other are mounted. By inspecting whether it is connected to the land at the predetermined position on the board, it is possible to inspect the mounting state by judging whether the corresponding part is mounted at the correct position, and the workability of the inspection of the mounting state Is improved.

【0047】さらに、また、部品底面に方形環状に外部
接続端子を有した半導体素子においては、半導体素子内
部の半導体デバイスや半導体デバイスを用いた電気回路
と電気的に絶縁され各々が接続された外部接続端子をコ
ーナー部分に配置することによって、半導体部品の実装
された基板において、落下等の衝撃により半導体素子の
半田剥がれによる障害が発生した場合、コーナー部分の
半田剥がれの危険が大きいため、半導体素子内部の半導
体デバイスや半導体デバイスを用いた電気回路と電気的
に絶縁され各々が接続された外部接続端子が、基板の所
定の位置のランドと接続しているかどうかを検査するこ
とにより、該当部品に半田剥がれが発生したか否かを判
断することにより半田剥がれの検査が可能となり、検査
の作業性が向上するという効果を有する。
Further, in the case of a semiconductor device having a rectangular ring-shaped external connection terminal on the bottom surface of the component, an external device electrically insulated from the semiconductor device inside the semiconductor device and an electric circuit using the semiconductor device and connected to each other. By arranging the connection terminals at the corners, if a failure such as dropping or the like causes the semiconductor element to be solder-peeled on the board on which the semiconductor component is mounted, there is a great risk of solder peeling at the corner part. By inspecting whether the external connection terminal, which is electrically insulated from the internal semiconductor device and the electric circuit using the semiconductor device and connected to each other, is connected to the land at the predetermined position on the board, By judging whether or not solder peeling has occurred, it is possible to inspect for solder peeling, improving the workability of the inspection. It has the effect of.

【0048】また、半導体素子において少なくとも1組
の2つの外部接続端子が電気的に導通するように構成
し、それらの外部接続端子が、半導体素子内部の半導体
デバイスや半導体デバイスを用いた電気回路と電気的に
絶縁されたように構成された半導体素子が実装された基
板において、基板側に設けられた半導体素子内部の半導
体デバイスや半導体デバイスを用いた電気回路と電気的
に絶縁され各々が接続された外部接続端子に接続された
ランド間の電気的な導通試験によって、半導体素子が正
しく実装されたか否かを判断することにより、試験の際
に、半導体素子に電気的なダメージを与える危険が無
い、信頼性の高い実装検査が可能になるという効果を有
する。
In the semiconductor device, at least one set of two external connection terminals is configured to be electrically conductive, and these external connection terminals are connected to a semiconductor device inside the semiconductor device or an electric circuit using the semiconductor device. On a substrate on which a semiconductor element configured to be electrically insulated is mounted, a semiconductor device inside the semiconductor element provided on the substrate side and an electric circuit using the semiconductor device are electrically insulated and connected to each other. The electrical continuity test between the lands connected to the external connection terminals is used to determine whether or not the semiconductor element is correctly mounted, so that there is no danger of causing electrical damage to the semiconductor element during the test. This has the effect that highly reliable mounting inspection becomes possible.

【0049】また、半導体素子において少なくとも1組
の2つの外部接続端子が電気的に導通するように構成
し、それらの外部接続端子が、半導体素子内部の半導体
デバイスや半導体デバイスを用いた電気回路と電気的に
絶縁されたように構成された半導体素子が実装された基
板において、基板側に設けられた半導体素子内部の半導
体デバイスや半導体デバイスを用いた電気回路と電気的
に絶縁され各々が接続された外部接続端子に接続された
ランド間の電気的な導通試験によって、半導体素子の半
田付け部分が正常か否かを判断することにより、試験の
際に、半導体素子に電気的なダメージを与える危険が無
い、信頼性の高い接続検査が可能になる効果を有する。
In the semiconductor device, at least one set of two external connection terminals is configured to be electrically conductive, and these external connection terminals are connected to a semiconductor device inside the semiconductor device or an electric circuit using the semiconductor device. On a substrate on which a semiconductor element configured to be electrically insulated is mounted, a semiconductor device inside the semiconductor element provided on the substrate side and an electric circuit using the semiconductor device are electrically insulated and connected to each other. The electrical continuity test between the lands connected to the external connection terminals may determine whether or not the soldered portion of the semiconductor element is normal, which may cause electrical damage to the semiconductor element during the test. There is an effect that a highly reliable connection inspection without any defect can be performed.

【0050】また、半導体素子においてコーナー部分に
設けられた少なくとも1組の2つの外部接続端子が電気
的に導通するように構成し、それらの外部接続端子が、
半導体素子内部の半導体デバイスや半導体デバイスを用
いた電気回路と電気的に絶縁されたように構成された半
導体素子が実装された基板で構成された半導体装置にお
いて、基板側に設けられた半導体素子内部の半導体デバ
イスや半導体デバイスを用いた電気回路と電気的に絶縁
され各々が接続された外部接続端子が基板のランドとの
接続不良が発生したときに、接続不良発生時の制御状態
に半導体装置を制御することにより、装置全体が接続不
良によって致命的な動作不良を起こす前に、接続不良の
発生を使用者に知らせることが可能となり、修理の作業
性が向上するという効果を有する。
In the semiconductor device, at least one set of two external connection terminals provided at a corner portion is configured to be electrically conductive, and these external connection terminals are
In a semiconductor device including a substrate on which a semiconductor element configured to be electrically insulated from a semiconductor device inside the semiconductor element or an electric circuit using the semiconductor device is mounted, the inside of the semiconductor element provided on the substrate side When the external connection terminal electrically insulated from the semiconductor device or the electric circuit using the semiconductor device and the external connection terminal connected to each other has a connection failure with the land of the substrate, the semiconductor device is brought into a control state at the time of the connection failure. By performing the control, it is possible to notify the user of the occurrence of the connection failure before the entire device causes a fatal operation failure due to the connection failure, and the repair workability is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1にかかる半導体素子の平
面図
FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention;

【図2】本発明の実施の形態1にかかる半導体素子の底
面図
FIG. 2 is a bottom view of the semiconductor device according to the first embodiment of the present invention;

【図3】本発明の実施の形態1にかかる半導体素子の側
面図
FIG. 3 is a side view of the semiconductor device according to the first embodiment of the present invention;

【図4】本発明の実施の形態2にかかる半導体素子の実
装状態ならびに接続状態を判定する検査装置の概略構成
FIG. 4 is a schematic configuration diagram of an inspection device that determines a mounting state and a connection state of a semiconductor element according to a second embodiment of the present invention;

【図5】本発明の実施の形態3にかかる半導体素子の実
装状態ならびに接続状態を判定する検査装置の回路図
FIG. 5 is a circuit diagram of an inspection device that determines a mounting state and a connection state of a semiconductor element according to a third embodiment of the present invention;

【図6】本発明の実施の形態3にかかる半導体素子の実
装状態ならびに接続状態を判定する検査装置における処
理の流れを示すフローチャート
FIG. 6 is a flowchart showing a flow of processing in an inspection device for determining a mounting state and a connection state of a semiconductor element according to a third embodiment of the present invention;

【符号の説明】[Explanation of symbols]

1 半導体素子 10a 接続端子 10b 接続端子 11 内部接続手段 20a 接続端子 20b 接続端子 21 内部接続手段 30 電気回路 200 プリント基板 210a 検査用配線パターン 210b 検査用配線パターン 220a 検査用配線パターン 220b 検査用配線パターン 300 検査装置 301a 入力部 301b 入力部 500 制御部 501 端子 502 端子 503 端子 504 端子 509 入力ポート 600 メモリ 601 端子 602 端子 603 端子 604 端子 700 プルアップ用の抵抗 800 表示部 DESCRIPTION OF SYMBOLS 1 Semiconductor element 10a Connection terminal 10b Connection terminal 11 Internal connection means 20a Connection terminal 20b Connection terminal 21 Internal connection means 30 Electric circuit 200 Printed circuit board 210a Inspection wiring pattern 210b Inspection wiring pattern 220a Inspection wiring pattern 220b Inspection wiring pattern 300 Inspection device 301a Input unit 301b Input unit 500 Control unit 501 terminal 502 terminal 503 terminal 504 terminal 509 Input port 600 Memory 601 terminal 602 terminal 603 terminal 604 terminal 700 Pull-up resistor 800 Display unit

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】外部回路との電気的接続を行うための複数
の外部接続手段と、少なくとも1組の2つ以上の前記外
部接続手段を半導体素子内部で電気的に接続する内部接
続手段と、前記内部接続手段によって電気的に接続され
た前記外部接続手段以外の外部接続手段に電気的に接続
された電気回路手段を有し、前記内部接続手段によって
電気的に接続された前記外部接続手段は、前記電気回路
手段と電気的に絶縁されていることを特徴とする半導体
素子。
A plurality of external connection means for making an electrical connection with an external circuit; an internal connection means for electrically connecting at least one set of two or more external connection means inside a semiconductor element; The external connection means electrically connected to the external connection means other than the external connection means electrically connected by the internal connection means, the external connection means electrically connected by the internal connection means A semiconductor element which is electrically insulated from the electric circuit means.
【請求項2】前記半導体素子のすべての前記外部接続手
段の中で、2つの外部接続手段の物理的距離が最も大き
い前記外部接続手段またはその近傍の前記外部接続手段
の少なくとも1つを前記内部接続手段で他の前記外部接
続手段に電気的に接続したことを特徴とする請求項1に
記載の半導体素子。
2. Among all the external connection means of the semiconductor element, at least one of the external connection means having the largest physical distance between two external connection means or the external connection means in the vicinity thereof is connected to the internal connection means. 2. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected to another external connection device by a connection device.
【請求項3】底面部に方形環状に複数の外部接続手段を
有した半導体素子であって、方形環状に配された前記外
部接続手段の中で、外周、かつ、コーナー部分またはそ
の近傍に配された少なくとも1つの外部接続手段を前記
内部接続手段で他の前記外部接続手段に電気的に接続し
たことを特徴とする請求項1に記載の半導体素子。
3. A semiconductor device having a plurality of external connection means in a square ring shape on a bottom surface, wherein the external connection means arranged in a square ring shape has an outer periphery and a corner portion or a vicinity thereof. 2. The semiconductor device according to claim 1, wherein said at least one external connection means is electrically connected to another external connection means by said internal connection means.
【請求項4】外部回路との電気的接続を行うための複数
の外部接続手段と、少なくとも1組の2つ以上の前記外
部接続手段を半導体素子内部で電気的に接続する内部接
続手段と、前記内部接続手段によって電気的に接続され
た前記外部接続手段以外の外部接続手段に電気的に接続
された電気回路手段を有し、前記内部接続手段によって
電気的に接続された前記外部接続手段は、前記電気回路
手段と電気的に絶縁されていることを特徴とした半導体
素子と、前記内部接続手段によって電気的に接続された
前記外部接続手段毎に電気的に接続され、各々が電気的
に絶縁され、外部から電気的接続が可能な複数の配線手
段を設けた基板において、前記半導体素子を前記基板に
実装し、前記基板に設けられた各々の配線手段間の電気
的導通の有無を検査し、電気的導通が有のとき前記半導
体素子の実装状態が良好であり電気的導通が無のとき実
装状態が不良であると判定することを特徴とする半導体
素子の実装状態の判定方法。
4. A plurality of external connection means for making an electrical connection with an external circuit; an internal connection means for electrically connecting at least one set of two or more external connection means inside the semiconductor element; The external connection means electrically connected to the external connection means other than the external connection means electrically connected by the internal connection means, the external connection means electrically connected by the internal connection means A semiconductor element characterized by being electrically insulated from the electric circuit means, and electrically connected to each of the external connection means electrically connected by the internal connection means, each of which is electrically connected. On a substrate provided with a plurality of wiring means that are insulated and electrically connectable from the outside, the semiconductor element is mounted on the substrate, and the presence or absence of electrical conduction between the respective wiring means provided on the substrate is detected. And method of determining the mounted state of the semiconductor element characterized in that electrical conduction is good mounting state of the semiconductor element when the organic electrical continuity is determined that the mounted state when no is defective.
【請求項5】実装される半導体素子は、外部回路との電
気的接続を行うための複数の外部接続手段と、少なくと
も1組の2つ以上の前記外部接続手段を半導体素子内部
で電気的に接続する内部接続手段と、前記内部接続手段
によって電気的に接続された前記外部接続手段以外の外
部接続手段に電気的に接続された電気回路手段を有し、
前記内部接続手段によって電気的に接続された前記外部
接続手段は、前記電気回路手段と電気的に絶縁されてい
ることを特徴とした半導体素子であって、前記内部接続
手段によって電気的に接続された前記外部接続手段毎に
電気的に接続され、各々が電気的に絶縁され、外部から
電気的接続が可能な複数の配線手段を設けた前記半導体
素子が実装、接続された基板において、前記基板に設け
られた各々の配線手段間の電気的導通の有無を検査し、
電気的導通が有のとき前記半導体素子の前記接続手段と
前記基板の配線手段の接続状態が良好であり電気的導通
が無のとき前記半導体素子の前記接続手段と前記基板の
配線手段の接続状態が不良であると判定することを特徴
とする半導体素子の接続状態の判定方法。
5. A semiconductor device to be mounted, comprising: a plurality of external connection means for making an electrical connection with an external circuit; and at least one set of two or more external connection means electrically connected inside the semiconductor element. Internal connection means for connecting, having an electric circuit means electrically connected to external connection means other than the external connection means electrically connected by the internal connection means,
The external connection means electrically connected by the internal connection means is a semiconductor element characterized by being electrically insulated from the electric circuit means, and is electrically connected by the internal connection means. Wherein the semiconductor element provided with a plurality of wiring means electrically connected to each of the external connection means, each of which is electrically insulated, and which can be electrically connected from the outside, is mounted and connected, Inspection of the presence or absence of electrical continuity between each wiring means provided in,
When there is electrical conduction, the connection between the connection means of the semiconductor element and the wiring means on the substrate is good, and when there is no electrical conduction, the connection between the connection means of the semiconductor element and the wiring means on the substrate is good. A connection state of a semiconductor element, which is determined to be defective.
【請求項6】少なくとも1つの底面部に方形環状に複数
の外部接続手段を有した半導体素子が実装された基板を
有した半導体装置であって、前記半導体素子は、外部回
路との電気的接続を行うための複数の外部接続手段と、
方形環状に配された前記外部接続手段の中で各コーナー
部分に配された4つの前記外部接続手段を2つずつ半導
体素子内部で電気的に接続する2つの内部接続手段を有
し、前記基板は、入力された電圧を検知する検知手段
と、すべての前記半導体素子の内部接続手段によって接
続された外部接続手段を電気的に直列に接続する少なく
とも1つの第1の配線手段と、前記直列に接続された外
部接続手段の一方を基板の回路のグランドに接続する第
2の配線手段と、前記直列に接続された外部接続手段の
他方を前記検知手段に接続する第3の配線手段と、前記
第3の配線手段に接続された抵抗を介して電位を与える
プルアップ手段と、前記検知手段で検知された電位に応
じて装置全体の制御を行う制御手段とを備え、前記検知
手段で検出された電位がグランドレベルでないときに装
置全体の動作を前記半導体素子の接続不良発生時の制御
状態に変えるように制御することを特徴とする電子機
器。
6. A semiconductor device having a substrate on which a semiconductor element having a plurality of external connection means in a rectangular ring is mounted on at least one bottom surface, wherein said semiconductor element is electrically connected to an external circuit. A plurality of external connection means for performing
The substrate has two internal connection means for electrically connecting two of the four external connection means disposed at each corner portion of the external connection means arranged in a square ring inside the semiconductor element by two. Detecting means for detecting an input voltage, at least one first wiring means for electrically connecting external connection means connected by internal connection means of all the semiconductor elements in series, and A second wiring means for connecting one of the connected external connection means to the ground of the circuit on the substrate; a third wiring means for connecting the other of the serially connected external connection means to the detection means; A pull-up unit for applying a potential via a resistor connected to the third wiring unit; and a control unit for controlling the entire apparatus in accordance with the potential detected by the detection unit. Taden Electronic equipment but which is characterized by controlling so as to change the operation of the entire apparatus when not in ground level in the control state at the time of connection failure of the semiconductor device.
【請求項7】少なくとも1つの底面部に方形環状に複数
の外部接続手段を有した半導体素子が実装された基板を
有した半導体装置であって、前記半導体素子は、外部回
路との電気的接続を行うための複数の外部接続手段と、
方形環状に配された前記外部接続手段の中で各コーナー
部分に配された4つの前記外部接続手段を2つずつ半導
体素子内部で電気的に接続する2つの内部接続手段を有
し、前記基板は、入力された電圧を検知する検知手段
と、すべての前記半導体素子の内部接続手段によって接
続された外部接続手段を電気的に直列に接続する少なく
とも1つの第1の配線手段と、前記直列に接続された外
部接続手段の一方を基板の回路の電源に接続する第2の
配線手段と、前記直列に接続された外部接続手段の他方
を前記検知手段に接続する第3の配線手段と、前記第3
の配線手段に接続された抵抗を介してグランドに接続す
るプルダウン手段と、前記検知手段で検知された電位に
応じて装置全体の制御を行う制御手段とを備え、前記検
知手段で検出された電位が電源レベルでないときに装置
全体の動作を前記半導体素子の接続不良発生時の制御状
態に変えるように制御することを特徴とする電子機器。
7. A semiconductor device having a substrate on which a semiconductor element having a plurality of external connection means in a rectangular ring is mounted on at least one bottom surface, wherein the semiconductor element is electrically connected to an external circuit. A plurality of external connection means for performing
The substrate has two internal connection means for electrically connecting two of the four external connection means disposed at each corner portion of the external connection means arranged in a square ring inside the semiconductor element by two. Detecting means for detecting an input voltage, at least one first wiring means for electrically connecting external connection means connected by internal connection means of all the semiconductor elements in series, and A second wiring means for connecting one of the connected external connection means to the power supply of the circuit on the substrate; a third wiring means for connecting the other of the external connection means connected in series to the detection means; Third
A pull-down means connected to the ground via a resistor connected to the wiring means; and a control means for controlling the entire apparatus in accordance with the potential detected by the detection means, wherein the potential detected by the detection means is provided. An electronic apparatus characterized in that when the power supply is not at the power supply level, the operation of the entire device is controlled to change to a control state when a connection failure of the semiconductor element occurs.
JP2000019823A 2000-01-28 2000-01-28 Semiconductor element, method of checking mounted state and connected state of semiconductor elements and electronic apparatus using semiconductor elements Pending JP2001210748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000019823A JP2001210748A (en) 2000-01-28 2000-01-28 Semiconductor element, method of checking mounted state and connected state of semiconductor elements and electronic apparatus using semiconductor elements

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Publication Number Publication Date
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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147426A (en) * 2008-12-22 2010-07-01 Fujitsu Ltd Semiconductor device and method of detecting solder joint part breakage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147426A (en) * 2008-12-22 2010-07-01 Fujitsu Ltd Semiconductor device and method of detecting solder joint part breakage

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