JP2001203315A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2001203315A5 JP2001203315A5 JP2000362327A JP2000362327A JP2001203315A5 JP 2001203315 A5 JP2001203315 A5 JP 2001203315A5 JP 2000362327 A JP2000362327 A JP 2000362327A JP 2000362327 A JP2000362327 A JP 2000362327A JP 2001203315 A5 JP2001203315 A5 JP 2001203315A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US45052499A | 1999-11-29 | 1999-11-29 | |
| US09/450524 | 1999-11-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001203315A JP2001203315A (ja) | 2001-07-27 |
| JP2001203315A5 true JP2001203315A5 (enExample) | 2008-01-10 |
Family
ID=23788426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000362327A Pending JP2001203315A (ja) | 1999-11-29 | 2000-11-29 | マルチチップ・パッケージにおけるｉｃチップのクラスタ・パッケージング |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2001203315A (enExample) |
| KR (1) | KR100806060B1 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4707446B2 (ja) * | 2005-04-26 | 2011-06-22 | 富士通セミコンダクター株式会社 | 半導体装置 |
| US7622313B2 (en) * | 2005-07-29 | 2009-11-24 | Freescale Semiconductor, Inc. | Fabrication of three dimensional integrated circuit employing multiple die panels |
| KR102080865B1 (ko) * | 2018-02-12 | 2020-02-24 | 세메스 주식회사 | 다이 본딩 방법 |
| CN113825202B (zh) * | 2021-09-28 | 2025-06-10 | 上海兆芯集成电路股份有限公司 | 跨芯片处理系统以及其路由方法 |
| CN115116880A (zh) * | 2022-07-22 | 2022-09-27 | 上海壁仞智能科技有限公司 | 芯片制造方法及设备 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52142481A (en) * | 1976-05-22 | 1977-11-28 | Toshiba Corp | Production of semiconductor device |
| JPH01235264A (ja) * | 1988-03-15 | 1989-09-20 | Toshiba Corp | 半導体集積回路装置 |
| JPH03214764A (ja) * | 1990-01-19 | 1991-09-19 | Sharp Corp | 半導体チップの製造方法 |
| US5240866A (en) * | 1992-02-03 | 1993-08-31 | At&T Bell Laboratories | Method for characterizing failed circuits on semiconductor wafers |
| JP2746093B2 (ja) * | 1993-12-30 | 1998-04-28 | 日本電気株式会社 | 半導体装置 |
| US5915231A (en) * | 1997-02-26 | 1999-06-22 | Micron Technology, Inc. | Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture |
| JPH11330256A (ja) * | 1998-05-19 | 1999-11-30 | Tif:Kk | 半導体装置およびその製造方法 |
-
2000
- 2000-11-27 KR KR1020000070909A patent/KR100806060B1/ko not_active Expired - Fee Related
- 2000-11-29 JP JP2000362327A patent/JP2001203315A/ja active Pending