JP2001197077A - Cell data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cell data processor which can reduce power consumption and improve circuit life by preventing unnecessary scrambling operation for the payload of a free cell. SOLUTION: Cell data are extracted from input data and synchronous cell data are outputted by having respective bits synchronized with a clock; and a delay means delays respective bit data of a payload part in the synchronous cell data by a time of a specific number of bits according to the clock, a header part in the synchronous cell data is repeated and outputted, and the payload part in the synchronous cell data and the output data of the delay means are put together and outputted as a descrambling result. Further, when cell data having no data at a payload part in the synchronous cell data are detected, a free cell detection signal is generated, the delay means stops operating when the free cell detection signal is generated, and a fixed value is outputted as a delay result as to a specific number bits right after the operation starts thereafter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to transmitted ATM (A
synchronous transfer mode: relates to a cell data processing device that descrambles cell data such as cell data.

[0002]

2. Description of the Related Art In an ATM communication system using ATM cells having a structure as shown in ITU-T (Telecommunication Standardization Sector of the International Telecommunication Union) recommendation I361-2,
The functions to be provided in the transmission convergence sublayer on the physical layer include HEC (Hea) of the ATM cell header.
ATM cells are extracted from the physical layer transmission frame by establishing cell synchronization using der Error Control field) bytes, and if there is a 1-bit error in the ATM cell header, the error is corrected and the ATM cell header is corrected to 2 bits or more. If there is an error, the ATM cell is discarded, a descrambling process is further performed, and an empty cell is detected and discarded.
It is specified in UT recommendation I432.1-7.3.
In particular, in the case of an SDH (Synchronous Digital Hierarchy) -based physical layer, it is defined that the descrambling process is performed using a self-synchronous scrambler of a generator polynomial × ＾ 43 + 1.

FIG. 1 is a block diagram of an entire circuit for realizing the function of a conventional transmission convergence sublayer. It comprises a cell synchronization / correction unit 1, an empty cell detection unit 2, a descrambler unit 3, and a cell format counter unit 4. The input data 101 is a data stream carried by the transmission frame of the physical layer. When the input data valid signal 103 indicates validity, the ATM cell data exists without interruption.

When the input data valid signal 103 indicates validity, the cell synchronizing / correcting unit 1 performs CRC (CRC) on the input data 101 in accordance with the provisions of ITU-T Recommendation I432.1-7.3.2.2. (Cyclic Redundancy Check) operation is performed, and the ITU-T recommendation I432.1-
Cell synchronization is established through an appropriate number of protection stages according to the provisions of 7.3.3, and cell synchronization is released through an appropriate number of protection stages. When cell synchronization is established, input data 1
01 can be extracted from the ATM cell. When cell synchronization is established, ITU-T Recommendation I432.1-7.3.2.
In accordance with the provisions of paragraph 1, using the CRC calculation result, error correction is performed on the extracted ATM cell header if there is a correctable error, and if there is an uncorrectable error, a discarded cell detection signal 105 is generated. I do. Further, it generates a synchronization state signal 106 for notifying the operation state of the cell synchronization in the cell synchronization / correction unit 1. The cell synchronization / correction unit 1 outputs the extracted cell data 104 and the discarded cell detection signal 1
05 is output to the empty cell detector 2 and the synchronization state signal 106
Is output to the cell format counter unit 4.

When the input data valid signal 103 indicates validity, the cell format counter 4 performs a counting operation for recognizing the ATM cell format in accordance with the synchronization status signal 106 from the cell synchronization / correction unit 1. The counter value 111 by the counter operation is output from the cell format counter unit 4 to the cell synchronization / correction unit 1, empty cell detection unit 2, and descrambler unit 3, respectively.

[0006] When the input data valid signal 103 indicates valid, the empty cell detecting unit 2 uses the header value of the cell data 104 from the cell synchronizing / correcting unit 1 based on the counter value 111 from the cell format counter unit 4. And I
An empty cell detection operation is performed in accordance with the provisions of TU-T Recommendation I432.1-7.3.5, and both when an empty cell is detected and when the discarded cell detection signal 105 is supplied from the cell synchronization / correction unit 1, the cell is detected. A discard signal 108 is generated. The empty cell detector 2 outputs a cell data 107 and a cell discard signal 108
Is output to the descrambler unit 3. Cell data 107
Is data obtained by simply passing the cell data 104 through the empty cell detector 2 as it is.

When the input data valid signal 103 indicates validity, the descrambler 3 recognizes the payload of the cell data 107 from the empty cell detector 2 based on the counter value 111 from the cell format counter 4. And
The descrambling operation is performed according to the provisions of ITU-T Recommendation I432.1-7.3.4. The descrambler unit 3 synchronizes the descrambled cell data 109 with the cell discard signal 108 from the empty cell detector 2 with the cell data 109, that is, the cell discard signal 110.
Is output.

FIG. 2 shows the internal configuration of the descrambler unit 3 described above. The descrambler 3 is an AND circuit 4
4, the exclusive OR circuit 45, the selector circuit 46, a D-type flip-flop circuit 47 and 49, the control signal generating circuit 48 and the D-type flip-flop circuit 50 ₁ to 50 ₄₃
Are connected in series and a 43-stage shift register circuit 50 is provided.

The cell data 107 is stored in a D-type flip-flop circuit 50 ₁ in the 43-stage shift register circuit 50.
The signals are input to the exclusive OR circuit 45 and the selector circuit 46. The clock 91 is input to the AND circuit 44, the D-type flip-flop circuits 47 and 49, and the control signal generation circuit 48. The counter value 111 is input to the control signal generation circuit 48. The cell discard signal 110 is input to the D-type flip-flop circuit 49. The control signal generation circuit 48 generates a clock valid signal 113 and a header area signal 112 as control signals in synchronization with the clock 91, and the clock valid signal 113 is supplied to the AND circuit 44, and the header area signal 112 is supplied to the selector circuit 46. Supplied. The AND circuit 44 outputs the clock 91 as the clock 92 when the clock valid signal 113 indicates valid. Its clock 92 is supplied to a D-type flip-flop circuit 50 ₁ to 50 ₄₃ which constitute the 43-stage shift register circuit 50. The shift register result output from the 43-stage shift register circuit 50 is supplied to the exclusive OR circuit 45. The descramble result, which is the output of the exclusive OR circuit 45, is supplied to the selector circuit 46. The selector circuit 46 selectively outputs one of the output signal of the exclusive OR circuit 45 and the cell data 107 according to the header area signal 112. The selection result output from the selector circuit 46 is D
It is supplied to a type flip-flop circuit 47. Each of the D-type flip-flop circuits 47 and 49 has a clock 91.
Works in sync with. D-type flip-flop circuit 4
7 and the cell discard signal output from the D-type flip-flop circuit 49 are supplied to the subsequent blocks.

FIG. 3 is a time chart showing an operation state of each section of the descrambler section 3. Note that the timing chart of FIG. 3 shows a case where the data valid signal 103 indicates valid. As shown in FIG. 3, an input data valid signal, a counter value 111, (serial) cell data, and a cell discard signal are input to the descrambler unit 3 in synchronization with the clock 91. When the counter value 111 is c0 to c39, it corresponds to the header of the cell, and when it is c40 to c423, it corresponds to the payload of the cell. The cell discard signal indicates "1" to indicate cell discard (when the header contains an error of 2 bits or more or is an empty cell), and "0" indicates not to discard. The control signal generation circuit 48 outputs the counter value 1
The header area signal 112 and the clock valid signal 113 are generated by decoding the signal 11. When the header area signal 112 indicates "1", it corresponds to the cell header,
A time indicating "0" corresponds to the payload of the cell.

The main part 43 of the descrambler 3 is
The stage shift register circuit 50 operates in response to a clock 92, and the clock 92 is obtained by calculating the logical product of the clock valid signal 113 and the clock 91 by the logical product circuit 44. Also, a 43-stage shift register circuit 50
Has stopped its operation because the clock 92 is not generated in the header area of the cell. Header area signal 112
The selector circuit 46 operates according to the header area signal 1
When 12 indicates “1”, the cell data 107 is relayed and output, and when it indicates “0”, the data of the descrambling result which is the output signal of the exclusive OR circuit 45 is relayed and output. Therefore, a descrambling processing function for the payload area excluding the header area is realized. The cell discard signal 108 is output as a cell discard signal 110 through a D-type flip-flop circuit 49 in order to match the timing with the cell data.

[0012]

However, the circuit configuration of the descrambler section in the above-described conventional cell data processing device may occupy most of the cell data depending on the system configuration or operation form of the ATM communication system. The descrambling operation is always performed for a certain empty cell. Originally, the content of the payload of an empty cell is defined in ITU-T Recommendation I432.1-7.3.5, so that the result of the descrambling operation for it is naturally fixed. Therefore, in the above-described circuit configuration, unnecessary descrambling operation is performed, and there is a problem that unnecessary power is consumed and a circuit life is shortened.

An object of the present invention is to provide a cell data processing apparatus capable of preventing unnecessary descrambling operation for a payload of an empty cell, thereby reducing power consumption and improving circuit life. That is.

[0014]

A cell data processing apparatus according to the present invention accepts input data including cell data comprising a header section and a scrambled payload section,
Cell synchronization detection means for extracting cell data from the input data, synchronizing each bit with a clock and outputting cell data, and converting each bit data of the payload portion in the cell data output from the cell synchronization detection means to a predetermined value. A delay unit for delaying according to the clock by the number of bits according to the clock; and a relay unit for relaying a header part in the cell data output from the cell synchronization detection unit, and outputting the payload part in the cell data and the output data of the delay unit. A descrambling output generating means for synthesizing and outputting as a descrambling result, the cell data having no data contained in the payload portion of the cell data output from the cell synchronization detecting means. And an empty cell detection means for detecting an empty cell detection signal. Sometimes stops operating, and and outputs a fixed value as a delay results for a predetermined number of bits from the immediately subsequent operation start.

[0015]

FIG. 4 is a block diagram of the whole apparatus showing an embodiment of the present invention. The transmission convergence sublayer device according to the present invention includes a cell synchronization / correction unit 11, an empty cell detection unit 12, a descrambler unit 13, and a cell format counter unit 14. Input data 6
1 is connected to the input of the cell synchronization / correction unit 11. The cell synchronization / correction unit 11 is the same as the cell synchronization / correction unit 1 in FIG. The clock 81 and the input data valid signal 63 are supplied to inputs of a cell synchronization / correction unit 11, an empty cell detection unit 12, a descrambler unit 13, and a cell format counter unit 14. The cell data 64 and the discarded cell detection signal 65, which are the outputs of the cell synchronization / correction unit 11, are supplied to the input of the empty cell detection unit 12, and the synchronization state signal 66 is also supplied to the input of the cell format counter unit 14.

The empty cell detecting section 12 detects an empty cell which does not include data in the payload from the cell data 64, and when an empty cell is detected, generates an empty cell detection signal during the detection. The cell data 67, the discarded cell detection signal 68, and the empty cell detection signal 72, which are the outputs of the empty cell detector 12.
Is supplied to the input of the descrambler unit 13. The discarded cell detection signal 68 is a signal obtained by passing the discarded cell detection signal 65 through the empty cell detector 12 as it is. From the descrambler 13, cell data 69 and a cell discard signal 70 are output. The counter value 71 output from the cell format counter unit 14 is supplied to inputs of the cell synchronization / correction unit 11, empty cell detection unit 12, and descrambler unit 13.

Next, the descrambler unit 13 shown in FIG.
Will be described. Descrambler part 13
5, as shown in FIG. 5, an AND circuit 24, an exclusive OR circuit 25, a selector circuit 26, D-type flip-flop circuits 27 and 29, a control signal generation circuit 28, a 43-stage shift register circuit 30, and an OR circuit 31. 43-stage shift register circuit 30 has a configuration in which D-type flip-flop circuit 30 ₁ - 30 ₄₃ having a set terminal S or the reset terminal R corresponding to the value of the payload of idle cells are connected in series.

The cell data 67 is supplied to the D-type flip-flop circuit 30 ₁ , the exclusive-OR circuit 25 and the selector circuit 26 of the 43-stage shift register circuit 30. The clock 81 is supplied to the AND circuit 24, the D-type flip-flop circuits 27 and 29, and the control signal generation circuit 28. The counter value is supplied to the control signal generation circuit 28.
The empty cell detection signal is supplied to the control signal generation circuit 28 and the OR circuit 31. The discarded cell detection signal is output from the OR circuit 3
1 is supplied. The OR result, which is the output of the OR circuit 31, is supplied to the D-type flip-flop circuit 29.
Clock valid signal 7 output from control signal generation circuit 28
4 The AND circuit 24, likewise the header area signal 73 to the selector circuit 26, also set pulse 75 D-type flip-flop circuit 30 ₁ to 30 ₄₃ set terminal S or the reset terminal of which constitutes the 43-stage shift register circuit 30 Supplied to R.

The clock 82 output from the AND circuit 24
It is supplied to a D-type flip-flop circuit 30 ₁ to 30 ₄₃ which constitute the 43-stage shift register circuit 30. 43
The shift register result which is the output of the stage shift register circuit 30 is supplied to the exclusive OR circuit 25. The descrambling result, which is the output of the exclusive OR circuit 25, is supplied to the selector circuit 26.

The selector circuit 26 performs a selecting operation in accordance with the header area signal 73. When the header area signal 73 indicates a header, the selector circuit 26 relays and outputs the cell data 67 (that is, the header portion), and the header area signal 73 indicates the payload. At times, the descrambling result output from the exclusive OR circuit 25 is relayed and output. The output of the selector circuit 26 is supplied to a D-type flip-flop circuit 27. Cell data 6 output from D-type flip-flop circuits 27 and 29
9. The cell discard signal 70 is output to the subsequent block.

In FIG. 4, input data 61 is a data flow carried by a transmission frame of a physical layer.
When the input data valid signal 63 indicates valid, the ATM cell data is packed without interruption. In the cell synchronization / correction unit 11, when the input data valid signal 63 indicates valid,
For input data 61, ITU-T Recommendation I432.1.
Perform CRC operation in accordance with the provisions of 7.3.2.2,
According to the result, ITU-T Recommendation I432.1-7.3.
Cell synchronization is established through an appropriate number of protection stages in accordance with the provisions of paragraph 3, and cell synchronization establishment is released through an appropriate number of protection stages.
When the cell synchronization is established, the input data 61
TM cells can be extracted. When cell synchronization is established, in accordance with the provisions of ITU-T recommendation I432.1-7.3.2.1, using the CRC operation result, if there is a correctable error in the extracted ATM cell header, error correction is performed. When there is an uncorrectable error, a discarded cell detection signal 65 is generated. In addition, a synchronization state signal 66 for notifying the state of cell synchronization is generated. Cell synchronization / correction unit 11
From the extracted cell data 64 and the discarded cell detection signal 6
5 to the empty cell detector 12 and the synchronization state signal 66 to the cell format counter 14.

When the input data validity signal 63 indicates validity, the cell format counter 14 performs a counting operation for recognizing the ATM cell format based on the synchronization status signal 66 from the cell synchronization / correction unit 11. The cell format counter 14 outputs the counter value 71 to the cell synchronization / correction unit 11, the empty cell detection unit 12, and the descrambler unit 1.
3 respectively.

When the input data valid signal 63 indicates valid, the empty cell detecting section 12 outputs the cell format counter 1
Cell synchronization / correction unit 1 based on the counter value 71 from
Recognize the header part of the cell data 64 from 1 and
-Perform an empty cell detection operation in accordance with the provisions of T Recommendation I432.1-7.3.5 to generate an empty cell detection signal 72. Discarded cell detection signal 65 from cell synchronization / correction section 11
Generates a discarded cell detection signal 68 in synchronization with the cell data 67. The empty cell detector 12 outputs the cell data 67, the discarded cell detection signal 68, and the empty cell detection signal 72 to the descrambler 13. Cell data 6
Reference numeral 7 denotes data obtained by simply passing the cell data 64 through the empty cell detection unit 12 as it is.

When the input data validity signal 63 indicates validity, the descrambler 13 uses the empty cell detector 1 based on the counter value 71 from the cell format counter 14.
2 recognizes the payload portion of the cell data 67 from
The descrambling operation is performed according to the provisions of TU-T Recommendation I432.1-7.3.4. At this time, the cell data 67 is output by the empty cell detection signal 72 from the empty cell detector 12.
Is determined to be an empty cell, an operation for an empty cell is performed. The descrambler 13 outputs a cell discard signal 70 generated by ORing the descrambled cell data 69 with the discarded cell detection signal 68 and the empty cell detection signal 72 from the empty cell detector 12. I do.

Next, the operation of the descrambler 13 will be described with reference to the timing chart of FIG. The timing chart of FIG. 6 shows a case where the data valid signal 63 indicates valid. An input data valid signal 63, a counter value 71, (serial) cell data 67, an empty cell detection signal 72, and a discarded cell detection signal 68 are supplied to the descrambler unit 13 in synchronization with the clock 81. When the counter value 71 is c0 to c39, it corresponds to the header of the cell, and when it is c40 to c423, it corresponds to the payload of the cell. The empty cell detection signal 72 indicates an empty cell by "1", and indicates that it has cell data by "0".
The discarded cell detection signal indicates “1” indicating cell discarding (for example, when the header contains an error of 2 bits or more), and “0” indicates not discarding. The control signal generation circuit 28 outputs the counter value 7
1 and further decodes the empty cell detection signal to
A header area signal 73, a clock valid signal 74 and a set pulse 75 are generated. In the header area signal 73, “1” indicates the cell header, and “0” indicates the cell payload. The clock valid signal 74 is generated so as to be in an invalid state in the header area of cells and the payload area of empty cells in order to control the supply / stop of the clock 82 supplied to the 43-stage shift register circuit 50.

The set pulse 75 is the information of the empty cell detection signal.
When the cell data input is determined to be an empty cell
Will be “1” at the last timing of the payload
Generated. The main part of the descrambler 13
The 43-stage shift register circuit 30 outputs a clock valid signal
Clock 82, which is the logical product of clock 74 and clock 81
It is operating, the header area of the cell and the pay
In the load region, the shift register operation, that is, the delay operation
Pauses work. Also, at the end of the empty cell payload
D-type flip-flop circuit 30 at the timing of₁~
30₄₃Set pulse to set terminal S or reset terminal R of
75 is supplied, thereby providing the payload of the empty cell.
The last 43 bits of data are D-type flip-flops
Circuit 30 ₁~ 30₄₃In the same state as set in
You. As a result, the header area signal 73 is transferred to the payload
Shows the D-type flip-flop circuit 30₁~ 30₄₃
Resumes operation in synchronization with clock 82,
The same as when the delay operation is
A 43-bit shift register circuit 30
Can be output from Therefore, the exclusive OR circuit
The descrambling result output from 25 is a 43-step shift.
Register circuit 30 delays the payload of the empty cell.
The same output data can be obtained as when
You.

As described above, a descrambling processing function can be realized without inconsistency even in a cell data stream including an empty cell. The empty cell detection signal and the discarded cell detection signal are output as a cell discard signal via a D-type flip-flop circuit 29 in order to take a logical sum and match the timing with the cell data.

[0028]

As described above, according to the cell data processing apparatus of the present invention, the delay operation is not always performed even on an empty cell as in the conventional circuit configuration of the descrambler unit. By not performing unnecessary delay operations as in the shift register circuit, the power consumed by the circuit can be reduced and the circuit life can be prolonged.

The cell data processing device of the present invention
In an ATM communication system using TM cells, ITU
The present invention can be applied to a transmission switching apparatus having a function to be provided in a transmission convergence sublayer as described in -T Recommendation I432.1-7.3.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conventional cell data processing device.

FIG. 2 is a block diagram showing a circuit configuration of a descrambler unit in the apparatus of FIG.

FIG. 3 is a timing chart showing the operation of each part of the descrambler unit shown in FIG. 2;

FIG. 4 is a block diagram showing a cell data processing device according to the present invention.

FIG. 5 is a block diagram showing a circuit configuration of a descrambler unit in the apparatus of FIG.

6 is a timing chart showing the operation of each part of the descrambler shown in FIG. 5;

[Explanation of Signs of Main Parts]

 1,11 cell synchronization / correction unit 2,12 empty cell detection unit 3,13 descrambler unit 4,14 cell format counter unit 30,50 43-stage shift register unit

Claims (5)

[Claims] 1. A cell for receiving input data including cell data comprising a header section and a scrambled payload section, extracting cell data from the input data, synchronizing each bit with a clock, and outputting cell data. Synchronization detection means, delay means for delaying each bit data of the payload portion in the cell data output from the cell synchronization detection means by a predetermined number of bits in accordance with the clock, and from the cell synchronization detection means A descrambling output generating means for relay-outputting a header part in the output cell data, synthesizing a payload part in the cell data and the output data of the delay means and outputting the result as a descramble result;
A cell data processing device comprising: a cell data processing device comprising: a cell data processing unit that detects cell data in which a data portion is not included in a payload portion of cell data output from the cell synchronization detection unit and generates a vacant cell detection signal. Wherein the delay means stops the operation when the empty cell detection signal is generated, and outputs a fixed value as a delay result for the predetermined number of bits immediately after the start of the subsequent operation. Cell data processing device. 2. The delay means comprises a shift register circuit for the predetermined number of bits, wherein the fixed value is set in the shift register circuit immediately after the vacant cell detection signal disappears. The cell data processing device according to claim 1. 3. The cell data processing device according to claim 1, wherein said delay means serially outputs fixed values corresponding to said predetermined number of bits. 4. The cell data processing device according to claim 1, wherein said descramble output generation means is an exclusive OR circuit. 5. The discard cell detection means for performing error correction on cell data extracted from the input data and outputting cell data for which error correction cannot be performed, instructing discarding of the cell data. The cell data processing device according to claim 1, wherein the cell data processing device outputs a signal.