JPH08125667A - Atm cell synchronization system and its circuit - Google Patents

Abstract

PURPOSE: To use the system for error correction processing after synchronization establishment or abort processing of erroneous cells while attaining low speed operation by the parallel processing as the cell synchronization system by receiving an ATM cell flow, decoding an output of a divider to generate a cell synchronizing pulse for cell synchronization processing thereby eliminating the need for addition of a storage circuit to store cell headers. CONSTITUTION: An 8-bit ATM cell flow is given to 5-stage D flip-flop circuits 1a-1e and outputted to an adder circuit 5a via a residue arithmetic circuit 3. The adder 5a calculates exclusive OR between the output of the residue arithmetic circuit 3 and the received cell and the result of arithmetic operation is given to the D flip-flop circuit 1f via an adder 5b. An output of the D flip-flop circuit 1f is given to a parallel processing CRC arithmetic circuit 7 and a decoder 9. An output of the CRC arithmetic circuit 7 is given to the adder 5b and a cell synchronizing pulse is outputted from the decoder 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM cell synchronization system and circuit.

[0002]

2. Description of the Related Art In recent years, B-ISDN (Broadband Aspect)
s of Integrated Services Digital Network) has been provided. ATM (Asynchronous Transfer Mode), which is a transmission method used in this B-ISDN, divides data including various information such as voice and image into a certain length and transfers it with destination information called a header. This is a system, and this information unit is called a cell.

According to the ITU-T recommendation (old CCITT recommendation), a cell is composed of a header of 5 bytes and an information field of 48 bytes, which is a total of 53 bytes. The 5 bytes (40 bits) of the cell header are X6 + X4 + X2 in a shortened cyclic code in which 32 bits are information points and 8 bits are check points called HEC (Header Error Control).
+1 (the pattern of 01010101) is added. The generator polynomial of the shortened cyclic code is X8 + X2
+ X + 1.

In the ATM, a cell-based method in which cells are directly transferred to a transmission line and an S-based method in which cells are once embedded in a data block called an SDH frame and then transmitted
There are two options for the DH based method. Also ITU
-In addition to the T recommendation, NT is not available during the transition to high-speed ATM.
Secondary group velocity frame in T cell relay system,
A frame different from the SDH frame may be used in some cases. In the method that uses these frames, byte-wise delimiters are found when synchronizing frames, so
By using this delimiter, parallel processing can be performed for each byte, which facilitates speeding up.

In ATM, it is necessary to find cell delimiters in order for the receiving side to correctly take out cells that are continuously transferred in the transmission path. This process is called cell synchronization,
It is specified to use the header added to the beginning of the cell. Specifically, since the shortened cyclic code can be divided by the generator polynomial, if 40 bits of the header are divided on the receiver side by the generator polynomial, X6 + X4 + X2 +1 added on the transmitter side becomes a remainder, so this property To use.

That is, when the cell delimiter position is not known (hunting state), a header size of 40 bits is extracted from the received data and division is performed by the generator polynomial, and when the remainder is X6 + X4 + X2 +1, The 40 bits extracted at that time are determined to be the header, and the pre-synchronization state is set. If they are different, the same inspection is performed on the 40 bits shifted to the next one bit position, and this inspection is continued until the pre-synchronization state is reached. Further, in the pre-synchronization state, the position assumed to be the header of the next cell is sequentially inspected a prescribed number of times, and if it is correct, the synchronization state is set to be complete.

In the synchronous state, error detection and error correction processing is performed on this header. Generator polynomial X8 + X
2 + X + 1 has a 1-bit error correction capability and a multi-bit error detection capability for a 40-bit header. For error detection, the header is divided by the generator polynomial, and the remainder is X6.
When not + X4 + X2 +1 it is judged that an error exists. In error correction, the position of the error bit is specified and corrected from the residue pattern.

Next, a concrete divider circuit is shown in FIG. This division circuit is an adder 11 to which data such as a header is input.
a and eight-stage registers (flip-flop circuits) 13a, 13b, 13c, 1 connected to the adder 11a
3d, 13e, 13f, 13g, 13h, and an adder 1 connected between the register 13a and the register 13b
1b and an adder 11c connected between the register 13b and the register 13c. The 8-bit feedback shift register is generally used as a divider. The output of each shift register when 40 bits are just input to this divider becomes the remainder.

Therefore, it is only when all 40 bits of the header are input to the divider that the presence of an error in the header or which bit is incorrect can be known for the first time. That is, the error determination processing such as processing the cell as a correct cell, correcting the processing as an error cell, or discarding the error cell is performed 40 times after the cell input is started.
The determination will be made after the bit time has elapsed. Therefore, it is necessary to hold 40-bit data in a storage circuit such as a shift register connected in parallel with the divider.

FIG. 5 shows an example of a conventional cell phase detection circuit. The cell phase detection circuit shown in FIG. 5 is composed of the same registers 23a to 23h as the divider shown in FIG. 4 and a divider including an adder (not shown) and a 40-bit shift register 2.
1 (0), 21 (39) and the decoder 25 are connected in parallel. In order to obtain the remainder for 40 bits of the header, the output of the shift register 21 of 40 bits is fed back to the input of the register 23 corresponding to X6, X5, X of the divider. This gives X40 as a generator polynomial G (X) =
This is because the remainder divided by X8 + X2 + X + 1 becomes X6 + X5 + X. Further, each output of the register 23 is input in parallel to the decoder 25 and is output as a cell synchronization pulse. This method uses a 40-bit shift register 2
Since 1 is used in parallel with the divider, it is not necessary to add a memory circuit for holding data in order to have an error correction function or a function to discard an error cell. However, 1
Since bit-by-bit processing is performed, it is difficult to increase the speed.

Another conventional example is shown in FIG. 6 (Japanese Patent Laid-Open No. 5-19).
1430). The cell phase detection circuit shown in FIG. 6 is based on a method of operating a divider with 8-bit parallel input / output. Register (D type flip-flop circuit) 31 capable of 8-bit parallel input / output and CR connected to this register 31 capable of 8-bit parallel input / output
The output of the C arithmetic circuit 33d is passed through the adder circuit 37 for adding the same pattern as that added by the transmitting side, and then the comparison circuit 3
9 and the comparison result of the comparison circuit 39 is output as a cell synchronization pulse via the coincidence detection circuit 41.

Next, a concrete design method of the CRC calculation circuit 33 in FIG. 6 will be described. In the divider circuit of FIG. 4, the current state of each register is F0 (n) to F7 (n), the next state is F0 (n + 1) to F7 (n + 1), and the input data is D (n). Then, the generator polynomial of CRC operation G (X) = X8 + X2 + X
Since it is +1, the following expression (1) is established (however, addition is an exclusive OR). F7 (n + 1) = F6 (n) F6 (n + 1) = F5 (n) F5 (n + 1) = F4 (n) F4 (n + 1) = F3 (n) F3 (n + 1) = F2 (n) F2 (n + 1) = F1 (n) + F7 (n) F1 (n + 1) = F0 (n) + F7 (n) F0 (n + 1) = D (n + 1) + F7 ( n) (1) When parallel processing is performed, the output in the next state of F0 (n) to F7 (n) is F0 (n + 8) to F7 (n + 8). If these are obtained from the above equation (1), the following equation (2) is obtained. F7 (n + 8) = F7 (n) + F6 (n) + F5 (n) + D (n + 1) F6 (n + 8) = F6 (n) + F5 (n) + F4 (n) + D (n + 2 ) F5 (n + 8) = F5 (n) + F4 (n) + F3 (n) + D (n + 3) F4 (n + 8) = F4 (n) + F3 (n) + F2 (n) + D (n + 4) ) F3 (n + 8) = F7 (n) + F3 (n) + F2 (n) + F1 (n) + D (n + 5) F2 (n + 8) = F6 (n) + F2 (n) + F1 (n) + F0 (n) + D (n + 6) F1 (n + 8) = F6 (n) + F1 (n) + F0 (n) + D (n + 7) F0 (n + 8) = F7 (n) + F6 (n) + F0 (n) + D (n + 8) (2) The parallel CRC operation circuit is designed so as to comply with the equation (2). FIG. 3 shows a specific circuit diagram.

In FIG. 6, four CRC calculation circuits 33 described above are included. This circuit enables a low-speed operation by performing parallel processing using byte delimiters that are known when frame synchronization is achieved. Since the input data passes through the CRC calculation circuit 33 in the circuit, the original data is not retained. Therefore, in order to perform the correction process after the synchronization is established or the process of discarding the error cell, it is necessary to add a storage circuit such as a register for holding the original data in parallel with this circuit.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is a cell synchronization system that enables a low-speed operation by parallel processing without adding a storage circuit for storing a cell header. An object of the present invention is to provide an ATM cell synchronization system and circuit that can be used for error correction processing after establishment or processing for discarding error cells.

[0015]

SUMMARY OF THE INVENTION In order to achieve the above object, in the first invention of the present application, a divider which is processed in parallel to enable low speed operation and a storage circuit such as a shift register which is processed in parallel are connected in parallel to each other. At the same time, the ATM cell flow is input, the output from the storage circuit is fed back to a predetermined input of the divider, and the output of the divider is decoded to generate a cell synchronization pulse to perform cell synchronization processing, and the storage is performed. The circuit is characterized by storing the header of the ATM cell, which eliminates the need for newly adding a memory circuit necessary for the error correction process after the cell synchronization is established or the process of discarding the error cell.

Further, according to the second invention of the present application, the first register having a predetermined number of stages to which the ATM cell flow is inputted, and the first register.
Remainder arithmetic circuit for computing and outputting the remainder from the output of the register, a first adder for adding the remainder output from the remainder arithmetic circuit and the input ATM cell flow, and the first adder Is provided between the first register and the second register, a second register to which the addition result of is input, a CRC calculation circuit that performs a CRC calculation based on the output of the second register, A second adder for adding the addition result of the first adder and the CRC calculation output of the CRC calculation circuit;
And a decoder for decoding the output of the second register to generate and output a cell synchronization pulse.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an ATM cell synchronizing circuit to which the ATM cell synchronizing method according to the present invention is applied. First, the schematic structure of the present embodiment will be described with reference to FIG. The 8-bit ATM cell flow has five stages of D-type flip-flop circuits 1a, 1b, 1c,
It is input to 1d and 1e and is output to the addition (exclusive OR) circuit 5a via the remainder calculation circuit 3. This adder 5
At a, the exclusive OR of the output of the remainder calculation circuit 3 and the input cell is calculated, and the calculation result is input to the D type flip-flop circuit 1f via the adder 5b.
The output of the D-type flip-flop circuit 1f is a parallel processing CRC whose generator polynomial is represented by X8 + X2 + X + 1.
It is input to the arithmetic circuit 7 and the decoder 9. The output of the CRC calculation circuit 7 is input to the adder 5b, and the decoder 9 outputs a cell synchronization pulse.

Next, the operation of this embodiment will be described. First, the formulas on which the ATM cell synchronizing circuit shown in FIG. 1 is based will be sequentially derived. In FIG. 5 described above, in the divider,
The current states of the registers are F0 (n) to F7 (n), the next states are F0 (n + 1) to F7 (n + 1), and the input data is D (n). Further, when the output of the 40-bit shift register is H39 (n), since the feedback is made to X6 + X5 + X of the divider, the following relationship is established. F7 (n + 1) = F6 (n) F6 (n + 1) = F5 (n) + H39 (n) F5 (n + 1) = F4 (n) + H39 (n) F4 (n + 1) = F3 ( n) F3 (n + 1) = F2 (n) F2 (n + 1) = F1 (n) + F7 (n) F1 (n + 1) = F0 (n) + F7 (n) + H39 (n) F0 (n +1) = D (n + 1) + F7 (n) (3) Further, in the 40-bit shift register, the state after the time t of H39 (n) is the value of the shift register before the time t. Therefore, the following formula is established. H39 (n + t) = H39-t (n) From the above relationship, F0 (n) to F7 in parallel processing
When the outputs F0 (n + 8) to F7 (n + 8) in the next state of (n) are obtained, the following expression (4) is obtained. F7 (n + 8) = D (n + 1) + F7 (n) + F6 (n) + F5 (n) + H39 (n) + H38 (n) + H34 (n) + H33 (n) F6 (n + 8) = D ( n + 2) + F6 (n) + F5 (n) + F4 (n) + H38 (n) + H37 (n) + H33 (n) + H32 (n) F5 (n + 8) = D (n + 3) + F5 (n) + F4 (n) + F3 (n) + H37 (n) + H36 (n) + H32 (n) F4 (n + 8) = D (n + 4) + F4 (n) + F3 (n) + F2 (n) + H39 (n) + H36 (n) + H35 (n) F3 (n + 8) = D (n + 5) + F7 (n) + F3 (n) + F2 (n) + F1 (n) + H38 (n) + H35 (n) + H34 (n) F2 (n + 8) = D (n + 6) + F6 (n) + F2 (n) + F1 (n) + F0 (n) + H39 (n) + H37 (n) + H34 (n) + H33 (n) F1 (n + 8) ) = D (n + 7) + F6 (n) + F1 (n) + F0 (n) + H39 (n) + H36 (n) + H34 (n) + H32 (n) F0 (n + 8) = D (n + 8) + F7 (n) + F6 (n) + F0 (n) + H39 (n) + H35 (n) + H34 (n) (4) When this equation (4) is constructed by a circuit, the block diagram shown in FIG. 1 is obtained.

In order to realize the equation (4), the ATM cell synchronizing circuit in this embodiment has two arithmetic circuits, that is, a CRC arithmetic circuit and a remainder arithmetic circuit. The CRC arithmetic circuit is composed of exclusive OR gates as shown in FIG. Further, since the input of the remainder arithmetic circuit is the output of the parallelized 40-bit shift register, each of H32 (n)
H39 (n), and when these are inputs 0 to 7, the remainder arithmetic circuit is composed of an exclusive OR gate as shown in FIG.

As described above, in the configuration of FIG. 1, since 40 bits of data can be secured, another data is secured to perform error correction processing after synchronization establishment or processing for discarding error cells. No need to leave. Further, since the 8-byte parallel processing is performed by using the byte delimiter obtained at the time of frame synchronization in the previous stage, it is possible to operate at a low speed clock. As described above, the present invention enables low speed operation by parallel processing as a cell synchronization method,
In addition, since the input data for the header size is retained,
It can also be used for error correction processing after synchronization establishment or processing for discarding erroneous cells, and does not require addition of a storage circuit such as a new shift register for storing a cell header. In this embodiment, the delay circuit and the like for establishing synchronization are not particularly described, but it goes without saying that they are appropriately provided as needed.

[0021]

As described above, the present invention does not require the addition of a memory circuit for storing a cell header, enables a low-speed operation by parallel processing as a cell synchronization method, and corrects errors after synchronization is established. It can also be used for processing or discarding erroneous cells.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a remainder arithmetic circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a CRC calculation circuit shown in FIG.

FIG. 4 is a block diagram showing a configuration of a conventional divider circuit.

FIG. 5 is a block diagram showing a configuration of a conventional cell phase detection circuit.

FIG. 6 is a block diagram showing a configuration of a conventional cell phase detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 D type flip-flop circuit 3 Remainder operation circuit 5 Addition (exclusive OR) circuit 7 CRC operation circuit 9 Decoder 11 Addition (exclusive OR) circuit 13 Register (flip-flop circuit) 21 Shift register 23 Register 25 Decoder 31 D Type flip-flop circuit 33 CRC arithmetic circuit 35 Exclusive OR circuit 37 Adder 39 Comparison circuit 41 Match detection circuit

Claims (2)

[Claims] 1. A divider which is parallel-processed to enable a low-speed operation and a memory circuit which is parallel-processed are connected in parallel with each other, and an ATM cell flow is input, and an output from the memory circuit is input to the divider. An ATM characterized by feeding back to a predetermined input and generating a cell synchronization pulse by decoding the output of the divider to perform cell synchronization processing, and storing the header of an ATM cell in the memory circuit.
Cell synchronization method. 2. A first register having a predetermined number of stages to which an ATM cell flow is input, a residue arithmetic circuit for calculating and outputting a residue from the output of the first register, and a residue output from this residue arithmetic circuit. A first adder circuit for adding the above-mentioned input ATM cell flow, a second register to which the addition result of the first adder circuit is input, and a CRC operation based on the output of the second register CR to do
A C arithmetic circuit, provided between the first adder circuit and the second register, the addition result of the first adder circuit and the CR of the CRC arithmetic circuit.
An ATM cell synchronization circuit comprising: a second adder circuit for adding the C operation output; and a decoder for decoding the output of the second register to generate and output a cell synchronization pulse.