JPS58177050A - Bidirectional communication system - Google Patents

Abstract

PURPOSE:To constitute a flexible network equipment and to improve the quality of communication and the reliability, by using terminals of two nodes on a transmission line as both ends, and forming the reciprocating transmission line with a part corresponding to a looped-circuit type transmission line. CONSTITUTION:An output of a synchronizing shift register 14 is reduced to zero is detected at a synchronizing detection circuit 13 and the output of the circuit 13 resets a polyphase clock generating circuit 16. A code of one frame inputted to a reception terminal is inputted to a buffer register 12 together with a register 14 and a time when the one frame code is finished is generated from the circuit 16 and the copy of the register 14 is transferred to a shift register 11. The reception code outputted from the register 12 is corrected and transferred to a buffer register 17 of the next stage. To execute the division of the transmission frame received succeedingly, the remainder of the register 14 is cleared with a reset signal from a reset circuit 15. The flexible network equipment is constituted, and the quality of communication and the reliability are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bidirectional communication system, and particularly to a bidirectional communication system applied to a special case of a loop-shaped transmission line.

Conventionally, in data transmission, information codes are transmitted continuously from the transmitting side, and the receiving side changes the conversion point of this code (from "1" to "0").
, a certain c/) takes out the timing for reception by "0" to "1"), detects the received code at that timing and synchronizes, and the synchronization method uses one character, such as the start-stop method. Add start bit °'01 at the beginning,
By adding a stop bit "1" to the end of the character bit and sending it from the transmitting side, the receiving side can detect the start bit and know the beginning of the character, and the stop bit and know the beginning of the character. Knowing the end,
There is an asynchronous method in which synchronization is achieved for each character, in which the receiving operation is performed at the same timing as the transmitting side.

In the synchronization method, a method is actually used in which self-timing is generated on the receiving side and the reception timing obtained by NZ from the conversion point of the reception code is corrected.

Furthermore, frame transmission is performed to obtain a large number of code transmission channels on one line, and in this case frame synchronization is required.

In other words, conventionally, in order to synchronize with the transmission frame,
Function codes for synchronization not related to information blocks (
For example, a method is used in which a reset pulse is sent to the frame receiving circuit by transmitting a frame by frame (for example, "SYN", etc.), and detecting the function code described above at the same time as the frame is received by the shift register on the receiving side. There is.

In this way, it is possible to detect synchronization by adding a function code regardless of the information block, or if an erroneous symbol occurs in the transmission frame and a point changes to a function code in the information field. , erroneous synchronization occurs on the receiving side.

This is because as the number of bits of the function code decreases, the frequency of occurrence of training synchronization increases. When erroneous synchronization occurs in a link with high multiplicity in a digital transmission system, the reliability of the transmission is lowered. Also, when automatically correcting erroneous symbols that occur during code transmission on the receiving side, it is necessary to transmit the same number of information symbols as the symbols transmitted for correction, so transmission is suspended for that time. Must. Furthermore, conventional transmission systems do not have scalability to a loop-shaped transmission network, making it impossible to configure a flexible network.

In order to solve these conventional problems, it is an object of the present invention to ensure frame synchronization, eliminate transmission pause time for one erroneous bit, and minimize erroneous bits that occur due to erroneous synchronization. Another object of the present invention is to provide a two-way communication system that can create flexible transmission equipment in a loop-like network configuration.

In order to achieve the above object, the bidirectional communication method of the present invention includes:
In a loop transmission method, frames of fixed length are repeatedly transmitted in one direction from each 7-mode terminal on a transmission path forming a closed circuit. A round trip transmission line is formed in a portion corresponding to the transmission line.

Embodiments of the present invention will be described below with reference to the drawings.

(a) Synchronization method Figure 1 shows the synchronization method on the transmitting side. FIG. 3 is a logic diagram of a division circuit using a generator polynomial.

A code word is created by dividing a polynomial having an arbitrary information symbol as a coefficient and having a frequency of (K-1) or less by its generating polynomial g00. now,
A vector whose components are the logical values of each bit constituting a code word is called a code vector. In general, a code vector is constructed to consist of a given number of information symbols followed by (n-) check symbols.

This check symbol corresponds to a self-correcting code.

Among the encoding methods described above, there is a method to obtain what is called a cyclic code, which is calculated using the following procedure.

i, f o(X), zn-1,-p-2,...
, zn-K are arbitrary information bits, and the coefficients with a frequency smaller than n-K are 0. This corresponds to a vector in which the first n-K components are O and the following x components are arbitrary information bits. Such a polynomial fo(X
) by the generator polynomial g(X), the following relational expression holds true. .

fo(X) −g(X)q(X) + r(X) ・・
==・(1) In the above equation α), r(3) is g(X)
It has a power smaller than n - K, which is the power of .

Therefore, the following equation is derived from the above equation α).

f o (X) - direction - g (1) q (X)...
...(2) In the above equation (2), f, (1) - r (the coset (fooo-r(X)) representing taste is a code vector. r(X) is n -K Since it has smaller power, all terms of power n - K or more are 0. However, all terms of power less than n - K of fo(X) are 0, so fo(X ) −(X) is the given information bit, and the low frequency term is the check bit determined by the information bit −,
). Such a combined code vector is
It can be made by the circuit shown in the figure. The division of f(, (x) by the generator polynomial g00 is shown in FIG.

The polynomial fo(X) with information bits that are K high-order coefficients and 0 as n -K low-power coefficients is a polynomial fo(X) that has information bits that are K high-order coefficients and 0 as low-order coefficients. The numerical coefficients are shifted in first. 1 for information symbols and n −K for low frequency 0s
11! It is necessary to perform a total of n1 shifts. In the M1 diagram, fQ(3)-qO-1-qIX -1-q2x2
＋・・・・・・qyuzn g(埒-go + gIX +
The operation of dividing g2X2+...gn-kX"- by .Then the first non-zero output appears, which is qn g-b-, which is the first coefficient of the quotient.-
Since the polynomial q1g(X) must be subtracted from the dividend for each coefficient of the equation, this is done by the feedback circuit shown in FIG. After a total of n shifts, the completed quotient appears in the output. And the residual r (
X) is included in the shift register. The remainder r(X) is
Since they are check bits with a negative sign added, these check bits are assigned to O at the low frequency position of (fo(X)) to form a sign vector).

Transmission is performed as follows. That is, first, each piece of information is manually shifted to the device shown in FIG. 1, and at the same time, it is transmitted to the communication channel. Once one information symbol has been input into the shift register, the n-Km bits of the register will hold the remainder. This is a check symbol with a negative sign added. Next, the feedback circuit of the shift register is disconnected by a switching circuit (b), and the contents of the shift register are shifted out. At this time, shift・−、；7
．． The switching circuit (A) outputs evening light while reversing the polarity.
out of contacts 1 and 2 of , transmits through 2 to the 1g channel. These n-K check symbols together with K information symbols complete the code vector.

Note that the circuit 3 is a circuit for sending out the start code and the end code.

FIG. 2 is a block diagram of a receiving circuit according to an embodiment of the present invention.

On the receiving side, when the code vector transmitted by the method shown in Figure 1 is input, this code is generated by the generator polynomial g(X)
It will be divisible by . The decoder comprises a buffer register 7 for storing the received code and a shift register 4 for dividing the received code by goo. If all of the remaining bits after the division become O, it means that the code vector has been received without error, and by detecting this, it is possible to synchronize the reception of the transmission frame.

In FIG. 2, the shift register 4 has memory devices rg""rn--1 and coefficient devices-go-g-n'-, etc. of FIG. 1, at the receiving terminals).
Divide the manually entered sign from. At the same time, the received code is input to the buffer register 7 and temporarily stored. The detection circuit 5 detects that all bits of the shift register 4 become O, and sends a signal to the clock generator 6. The multiphase clock generator 6 operates by being supplied with a clock from a bit clock terminal (T) in order to generate a multiphase tally for the receiving side logic circuit. The clock from the terminal (G) is also supplied to the other blocks in FIG. 2, thereby performing no operation. The output (A) of the detection circuit 5 is generated when each bit of the shift register 4 becomes 0, thereby resetting the multiphase clock generator 6. By resetting the polyphase tally clock generator 6,
In order to make the timing at which each symbol of the buffer register 7 is outputted via the logic type circuit (wa) appropriate,
The phase of the multiphase clock is set. Then, at each slot time of the transmission frame, the output terminal body)
The contents of the corresponding 7-ray A configuration hit will be published one after another. A reset pulse will be generated for each frame of the received code, but if an error occurs, naturally no reset pulse will be generated. However, assuming that the clock supplied to the multiphase clock generator 6 is unrelated to this reset pulse, if the phase of the multiphase clock matches with the reset pulse when the immediately previous transmission frame is received, then , multiple clocks with the correct phase can be obtained even if no reset is performed in the current frame. reset·
A multiphase clock will still be generated even if the pulse is a pulse, but this does not mean that a reset pulse is not necessary. Without this reset pulse, it will naturally not be possible to synchronize with the frame of the received code, so when the transmitted frame is correctly received, It is necessary to reset the multiphase clock generator 6.

The codes constituting the transmission frame are generated using the generator polynomial g (
It is divisible by X). The transmission frame is occupied by fields filled with such symbols. When the code is divisible, the multiphase tarlock generator 6 on the receiving side is reset by the reset line I) in FIG. 2, and the normal operating phase is maintained on the receiving side.

By the way, the transmission frames are transmitted continuously without any transmission stop time. In such a situation, if an erroneous bit occurs and the remainder of the division created by shift register 4 does not become 0 at the normal timing, the division will still occur even if the next transmission frame is transmitted correctly. The remainder of the calculation will not be O. Therefore, in order to prevent this from happening, it is necessary to provide a function field with a specific code structure indicating the beginning and end of the transmission frame in a field other than the code vector trajectory of the transmission frame. That is, a switching circuit (c) and a start/end code sending circuit 3 are provided on the transmitting side of FIG. 1, and before the switching circuits (a) and (b) are restored and the next information bit appears at the input terminal, The switching circuit (c) is reversed from 1 to 2, and after transmitting the starting code following the ending code from the sending circuit 3, the original state is restored.

On the receiving side, this end and start code is detected.
After i, the calculation using the generator polynomial E (X) is started. For this purpose, it is necessary to provide a circuit to detect the end and start codes.1. The shift register 8 shown in FIG. 2 fulfills this role. The shift register 8 receives the code input from the reception terminal (to) while shifting it, and outputs a reset output when the code configuration created by the logical value of each bit is the above-mentioned end and start function code configuration. Send to the shift register block to reset the remaining registers of the divider circuit.

A method of providing start and end codes and detecting them on the receiving side has been conventionally used, but in the present invention, the code vector is further detected without immediately resetting the multiphase clock circuit 6. After that, the polyphase tallock circuit 6
It resets the .

Note that in order to reset the remaining registers without using the shift register 8 in FIG. 2, it is necessary to provide a space time equal to the transmission frame length, but this is not desirable because it causes a large loss in transmission efficiency. . That is, there should not be a long pause between the end of one transmission frame and the beginning of the next transmission frame.

(b) Correction method FIG. 3 is a block diagram of an error correction circuit used in the present invention, and FIG. 4 is a block diagram of a synchronization and erroneous bit correction/parallel execution circuit showing an embodiment of the present invention.

Assume now that a code vector (f(X)) is transmitted.

Assume that an error occurs at this time, and the receiving side receives a code that differs from the code vector by IC(X).
E (X) is the error pattern. The error pattern is also divided by dividing the received code by g(X), and this division will be called a parity check. If the result of the parity check is the residual R(X), then the following equation holds.

jC (equal - g body) 8 (force + R (shu...)
(3) Multiplying the remainder R(X) by xl and dividing by g(X) can be expressed as follows.

X"R(X)-g(X)St(X)10R+(X)""
...' G4)-L The following equation is derived from equations (3) and (4).

X1E(X) -Rs(')O-X'g(X)s(X)
10g body) - 1 (force......(5) G above
5) The formula is (X11(X) Rt(-X) ) b'
symbol h) indicates that there is a te, and (XiXX)
) and (Rt(X)) should be included in the same coset. Error correction is performed by executing the left side of equation (5) above, and is carried out using the circuit shown in FIG.

In FIG. 3, 9 is the memory device (
It is a soft register that has a circuit consisting of rQ ”-rn- to -1) and its peripheral devices, and its contents are R1(X). During the code receiver (1), close the switching circuit (b) and open the switching circuit (d).
- Calculated by the division circuit 9 used during encoding over the entire vector. At the same time, the received code vector is recorded in buffer 1o. K:1 knotty check ends at the same time as the reception of the received code vector is completed, and then the above (
5) Open the switching circuit (b) and close the switching circuit (b) to perform the correction according to the formula.

The shift register 9 is sequentially shifted so that one symbol is read out.2. At the same time, one symbol is successively output from the buffer 10. This process has been reversed,
In the step where an error occurs, the error is corrected by subtracting the output symbol of the shift register 9 from the output symbol of the buffer 10 by the arithmetic unit 11. In (f), the most likely error pattern to obtain this correction is a burst error. This burst kneading pattern is expressed as (XjB(X)). therefore,
The received code at this time is (f(3)+XjB(1)).

A parity check is performed on the receiver side by dividing f(X)+XjB) by g(X), and the remainder is retained. If the residual is 0, the code word has been received correctly, but if it is not 0, it means that it contains error information.

Here, since (f(X)) is a code vector, f(
X) is divisible by g(4). Therefore, the parity check residual is equal to xjn(x) divided by g(1).

Now, assume that xjn(x) is expressed by the following equation.

xjB(car g(1)8(埒+R(3)・・・・・・・
...(6) Here, R(X) is the frequency n - K of goo
It has a smaller frequency.

The error correction method described in (3) to (0) above and the circuit shown in FIG. 3 determine the above-mentioned XjB(X).

In the above formula (3), (IC(X)) −(XjB(
X)) and i −n −j, the following equation is derived.

X'R(X) -xi+j B(X)-X1g(X)s
(X) −(X” −1)B(X)−X'g(X)s(
Sumo wrestler E(X)・・・・・・・・・(7) Here, Xn
-1 is divisible by g(X), and B(X) is g(
X) has a frequency smaller than n - K, then
B(X) must be the remainder when X1R(X) is divided by g(X). Is this the case (4) above?
, the operation of equation (5) is nothing but deleting B(X)". However, if the frequency of E(X) becomes larger than n - K, the limit of error correction ability is exceeded. Therefore, corrections will be made by other means.

Figure 2 shows a circuit that performs frame synchronization on the receiving side.
The figure shows a circuit that corrects errors on the receiving side.

In order to create a circuit capable of synchronization and error correction using these, it is necessary to improve the circuit shown in FIG. 2.

^) Shift register 4 in FIG. 2 corresponds to shift register 9 in FIG. 3, and buffer register 7 in FIG.
This corresponds to the buffer register 10 in Figure 3. Therefore, in order to improve the circuit to enable the second ship correction, it is necessary to adopt the circuit system shown in FIG. 3 for the output 11 of the buffer register 7.

However, in this state, it becomes impossible to continue receiving data from the receiving terminal (in FIG. 2) during decoding. Therefore, two shift registers shown in FIG. 2 may be provided, one of which maintains the state shown in FIG. 2, while the other performs error correction in accordance with the purpose of FIG. 3. That is, the contents of the shift register 4 are transferred to the other shift register 9 at the timing when the code is completely set in the buffer register 7 by the multiphase tarlock from the multiphase clock generation circuit 6 in FIG. It is sufficient to perform the kneading correction shown in 3wJ.

A circuit for simultaneously performing synchronization and entertainment bit correction is shown in FIG. This circuit includes a synchronization shift register 14, a synchronization detection circuit 13 that detects when its output becomes "0," a polyphase clock generation circuit 16 that is reset by the output of the synchronization detection circuit 13, and an error correction circuit. a shift register 11 for inputting signals, a buffer register 12 for manually inputting received codes, and a shift register 1 shifted by a multiphase clock.
7 and a reset circuit 15.

When the code of the l frame input to the receiving terminal) is manually input to the synchronization soft register 14 and the pan register 12, the shift register 14 converts the manually input code into goo.
Divide by and print the remainder. When the synchronization detection circuit 13 detects that the output of the soft register 14 becomes 0, the multiphase clock generation circuit 16 is reset with the output. When the multiphase clock generation circuit 16 outputs a clock indicating the time when one frame of code ends, the contents of the synchronization soft register 14 are transferred to the shift register 11 having the same logical configuration, and thereafter, The received code output from the buffer register 12 is corrected and transferred to the next stage buffer register 17.

In order to perform WiJN for the subsequently received transmission frame, the remainder of the shift register 14 must be cleared, so the output signal of the reset circuit 15 is sent to the shift register 14 via the reset line.

Extraction of information in a desired time slot of a transmission frame and transmission to another terminal are performed based on the corrected data, that is, the output side of the buffer register 17, according to instructions from a multiphase clock. R in FIG. 4 is a receiving device, and g is a transmitting device. Transfer from the buffer register 17 to the receiving device R is performed by Ii# processing gates 1.2. ．． 3 and is ANDed with the polyphase tarlock output and sent. In addition, transmission from the transmitting device 6 to the transmission system located next to the buffer register 17 is performed by performing an AND with the multiphase clock output through logic 4.5.6 and transmitting the signal to the buffer register 17.
After being temporarily stored there, the contents are shifted one bit at a time and transferred one bit at a time to the transmission system (A). In addition, the clock applied to L2, 3 is generated by a multiphase clock generator so that it appears one step earlier than the clock applied to the corresponding logic gate 4, 5, and 6. □,・1 It is necessary to configure the path 16.

(c) Transmission system In the case of the code transmission system described in (a) synchronization method and (b) error correction method, the transmission system can be configured as shown in FIGS. 5 and 6.

FIG. 5 is a connection diagram of a loop transmission system showing an embodiment of the present invention, and FIG. 6 is a block diagram of a transmission code processing section of the terminal shown in FIG.

The code format flowing through the transmission link is formed by repeating transmission frames of length -W, and each frame is divided by dividing the information part and the information code part according to the algebraic law as mentioned in (a) above. A residual code is added to form ts. Each terminal or subsystem that is a node of the transmission network is connected in a loop as shown in FIG. Fifth
In the figure, the loop network α is centered around the exchange 26,
A transmission network is formed by connecting the terminals 20° 21.22, the information processing device 23, the originating and receiving call processing device 25°, and the exchanger 24 for exchanging between the subsystems α and β in a loop. The subsystem β also forms a loop-shaped transmission path.

Each node connected to the loop-shaped transmission path σ transmits the above transmission frame in one direction and circulates it.The information part of the transmission frame is divided into a plurality of fields,
For example, it is assigned to general information in the first field, call information in the second field, and call information in the third field. Time division slots are allocated to the 7-1 card stations other than the exchange 26 and the originating/receiving call processor 25 of the α network, and the first and second fields are processed by the exchange 26, respectively, and the third field is used for the originating/receiving calls. Processed by a processor 25.

In the loop network, exchangers 24 and 26 and detection processor 2
It is necessary for node stations other than No. 5 to have the same transmission code processing function.

The transmission code processing section of the terminal 21 in FIG. 5 has #I power as shown in FIG.

In FIG. 6, a mask clock source 28 can be automatically adjusted by voltage control, and distributes a bit clock and an operation clock to each circuit.

When the damaged section 29 of the line terminator receives the signal from the upper station, it sends the scrambling baseband signal therein to the sample value data system 27.・Detect clock timing information. Sample value data system 2
7 operates based on a bit clock, and applies a voltage to the oscillation frequency word '# terminal of the master clock source 28 to control the timing information outputted from it in the direction of O.

The vector register 32 processes the next transmission frame using the operating clock and bit clock from the master clock source 28. That is, the output of the receiving IN 29 is passed through the descrambling circuit 30 to the vector register 3.
Enter 2. The vector register 32 is a shift register 1゜14 shown in Fig. 1s4, a synchronization detection circuit] 3,
In addition to the buffer register 2 and the like, it is provided with a reception code register, which shifts one bit and inputs the reception hit of the output from the descrambling circuit 30 to the lowest position. At this time, the l1lJ calculation is performed according to the above-mentioned algebraic law, and the corrected received code vector is transmitted from the highest symbol to Xil to the transmitting/receiving circuit 33 at the next stage. The transmitting/receiving tX circuit 33 is
It buffers the codes exchanged between the transmission system and the terminal device that communicates using it, and the fourth
It consists of a buffer register 7 shown in the figure and a clock generation circuit 16 that controls its contents, and is mainly composed of a shift register for the number of symbols in the information field of a transmission frame. Then, the transmitting/receiving circuit 33 receives the contents of the output code of the vector register 32 by shifting it, and sends the output of the shift register to the next division circuit 34. In parallel with this, the time given to the terminal 21
Perform the following operations in the slot.

Transmission/reception circuit: 5. The clock controlling the code exchange between '5 and the terminal device is produced by a polyphase tarlock generator circuit 16, shown in Figure 4. The operating phase of this clock generation circuit 16 is determined by the vector 1-disk 32 in FIG.
regulated by a reset pulse derived from Based on this timing, the first . Second
and the time J1 given for the terminal 21 in the third feed It•Create the timing of the slot. transmission frame
□At the timing corresponding to the first field, the contents of the shift register of the transmitting/receiving circuit 33 are transferred to the receiving register 39, and at the same time, the transmitting register 36 transfers the contents of the shift register of the transmitting/receiving circuit 33 to the receiving register 39.
Update the contents of register 3.

In the same way, the second field of the transmission frame.

At the timing given for the terminal 21, the contents of the transmitting/receiving circuit 33 are transferred to the receiving register 40, and the transmitting/receiving circuit 33 is updated with the contents of the transmitting register 37. Also, at the timing for the terminal 21 in the third field of the transmission frame, for example, the received call information is transferred from the transmitting/receiving circuit 33 to the receiving register 41, the transmitting call information is taken out from the transmitting register 38, and the contents of the transmitting/receiving circuit 33 are updated. . Transfer from the register of the transmitting/receiving circuit 33 and updating of its contents is performed in the buffer register 17 shown in FIG. ing. By being shifted, the register contents of the transmitting/receiving circuit 33 become
The code of the information to be transmitted to the communication partner terminal appears at the output of the transmitter/receiver circuit 33.

This code is input to a division circuit 34, where division is performed according to the algebraic encoding rules of the sender, as shown in FIG. When the transmission/reception circuit 33 has finished transmitting the information symbols of the transmission frame, the division circuit 34
The code resulting from the division performed up to that point is transmitted in place of the information symbol, and the system returns to transmitting the information symbol, that is, transmitting the output of the transmitting/receiving circuit 33.

The next-stage scrambling circuit 35 has a function of scrambling the code to be transmitted to the lower station, and the final stage termination circuit 42 is the termination of the transmission line to the lower station.

As shown in FIG. 6, there are two or more terminals 20 in the loop network α.
, 21, 22 are connected, the transmission frame flowing through the roof' is divided into many time slots. By the way, if there are only two terminals connected to the loop network σ and communication is to be performed between these terminals, the line connecting the terminals shown in FIG. It becomes a round-trip transmission line that connects the Then, if there are only two terminals in the loop, the time slots of the transmission frame are occupied by these two terminals.

Also, as shown in FIG. 5, when there are many terminals, each time slot of the transmission frame is
This is to secure a channel between the L22 and the exchange 26. On the other hand, when there are two terminals on the loop line, the switching center 26 becomes unnecessary and the transmission frame consists of one set of time slots and is shared by the two terminals. That is, in FIG. 6, at the timing when each symbol of the transmission frame is positioned in the shift register (transmission/reception circuit) 33 according to the transmission order, all the contents are transferred to the reception registers 39 to 4.
1, and all the contents of the shift register 33 are updated by the transmission registers ★36 to 38.

In FIG. 5, one of the plurality of terminals may accommodate a plurality of point-to-point (V) lines as described above. This case is shown in FIG.

FIG. 7 is a block diagram of a bidirectional communication system showing an embodiment of the present invention.

In FIG. 7, receiving registers 39-41. The transmit registers 36-38 and shift register 33 are the same as those shown in FIG. 6, but the number of bits in these registers in this terminal is the same as the bits in the same register in the other terminals in FIG. The number is multiplied by the number of accommodated terminals.

The plurality of terminals 51 to 59 are terminals accommodated in the above terminals, and these are connected to the time division multiplexer 44 through cables. These multiple ends *51-59 each have the same bit and frame synchronization functions as in FIG. However, the number of bits in each register can be selected as an appropriate value in consideration of code transmission efficiency, synchronization, and error correction ability.

In FIG. 7, the slots assigned to a plurality of terminals 51 to 59 are recorded in m- from the shift register 33 to the receiving registers 39 to 41, and each terminal in the shift register 33 is recorded using the contents of the transmitting registers 36 to 38. Update the corresponding partial digit. Each point-to-bore is then accommodated through a time division multiplexer 44.

Transmission frame creation, synchronization, and correction processing for the Indian line is performed using time division multiplexing. Note that the terminal corresponding to the "upper station" in FIG. 6 is the receiving terminal 60 from the time division multiplexer 44 in FIG. 7, and the terminal corresponding to the "lower station" in FIG. This is a transmission terminal 61 to the division multiplexer 44. The time division multiplexer 44 operates based on the operating clock and bit clock supplied from the master clock source 28 in FIG. Assign sequentially. On the other hand, the frame memory 45 records a control status table for controlling frame format transmission and reception for each terminal. When the time division multiplexer 44 allocates time slots to the terminals 51 to 59, it retrieves the control status table corresponding to each terminal from the frame memory 45 and performs processing according to the status and the code received from the terminal through the cable. conduct. When the processing is completed, the control status table is updated and the transmission registers 36 to 38 and the reception register 39 are
1 and the time division multiplexer 44. The contents of the control status table are: Display of the status of functions corresponding to the descrampling circuit 30, vector register 32, transmitting/receiving circuit 33, dividing circuit 34, scrambling circuit 35, etc. shown in FIG. The time division multiplexer 44 is equipped with one set of these function status indicators. In this case, the timing of ts@ received from the II number terminal δ1-5G' may deviate in the hour/minute side strip loading [44], so
It is necessary to provide a timing adjustment circuit on the receiving side of the multiplexer 44 of each point-to-point line.

As explained above, according to the present invention, a communication network can be configured in either a closed circuit or a radial circuit combination, making it possible to create flexible network equipment and improve communication quality. and reliability can be improved.

[Brief explanation of the drawing]

@11fflGf sending ffl side nio! Figure 2 is a plot diagram of the frame synchronization circuit used in the present invention, Figure 3 is a block diagram of the error correction circuit used in the present invention, and Figure 4 shows an embodiment of the present invention. FIG. 2 is a block diagram of the synchronization and error pit correction/parallel execution circuit shown in FIG. 11: t4 correction shift register, 12. Buffer register, 13: Synchronization detection circuit, 14: Synchronization register d5: Reset circuit, 16: Multiphase clock generation circuit, 17: X7A register, 18.19: Terminal device, 20.21 .22: Terminal, 23: Information processing device, 24: Inter-network exchange, 25: Call processing device, 26:
Exchange, 27: Sample 1 direct data system, 28: Master clock source, 29: Receiver, 30: Descrampling circuit, 31.42: Termination circuit, 32 Two-vector register, 33: Transmission/reception circuit, 34: Division Circuit, 35 Nis clamp ring circuit, 36-38: Transmission register, 39-
41, father fd register, 44 two-time division multiplexer, 45°7L, -me memory, 51-59 = terminals. Figure 3 Figure 5 Figure 6

Claims (2)

[Claims] (1) In a loop transmission method in which frames of a fixed length are repeatedly transmitted in one direction from the terminals of the nodes on the transmission path forming the 1% IJ@ path, the terminals of the two nodes on the transmission path are used as both ends, and the circuit is closed. A two-way communication system characterized by forming a round-trip transmission line in a portion corresponding to a shaped transmission line. (2) At each terminal of the two nodes, the code word of the transmission frame is constructed according to an algebraic law, and the condition that the code word is a code word using the above algebraic law following the start code of the transmission frame. Detect the timing that satisfies the requirements, set the reception clock phase, record the contents of the first register that records the processing result according to the above algebraic law in a second register with the same configuration, and perform the process in parallel with the reception of the transmission frame. 2. The bidirectional communication system according to claim 1, wherein an error is corrected in the frame immediately preceding the frame being received.