JPS58176754A - Self-correcting system - Google Patents

Abstract

PURPOSE:To reduce both the frequency and the time of an clearance work related to a transmission error, by detecting the timing from a code word consisting of an algebraical rule to set the phase of a receiving clock, and at the same time, by correcting a received code word. CONSTITUTION:A code word consisting of an algebraical rule and supplied to a receiving terminal (d) is fed to a synchronizing shift register SR14 and a buffer register BR12 respectively. Then the SR14 divides the fed code by a prescribed generated polynominal and delivers the remainder. When a synchronism detecting circuit 13 detects that the output of the SR14 is reduced to O. a multi-phase clock generating circuit 16 is reset with the output of the circuit 13. Then a clock showing the end time of a 1-frame code is delivered from the circuit 16, therefore, the contents of the CR14 are transcribed to an SR11 having the same logical constitution as the SR14. Thereafter, the received code delivered from the BR12 is corrected and transferred to a BR17. The output signal of a resetting circuit 15 is delivered to the SR14 in order to clear the remainder of the SR14 for execution of a transmission frame which is received subsequently.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention combats self-correction methods, and particularly relates to a method for self-correcting erroneous bits on the receiving side of a code transmission path or when reading or writing to a storage device.

Conventionally, in data transmission, information codes are transmitted continuously from the transmitting side, and the receiving side changes the conversion point of this code (from "1" to O").
There is a synchronization method in which the timing for reception is taken out by a signal (from "O" to "1") and synchronization is achieved by detecting the received code at that timing, and a synchronization method that synchronizes by detecting the reception code at that timing. 0” and a stop bit “l” at the end of the character bits,
By transmitting from the transmitting side, the receiving side can start and
Detects bits to start and stop characters.
There is an asynchronous method that synchronizes each character, rather than detecting the bit and knowing the end of a character and performing a receiving operation at the same timing as the transmitting side.

In the synchronous method, in reality, self-timing is generated on the receiving side, and wIH! is generated from the conversion point of the received code. A method of correcting the received timing is used.

Also, frame transmission is performed to obtain multiple code transmission channels in one @ stripe, but in this case frame synchronization is required◇ In other words, conventionally, in order to synchronize with the transmission frame,
information - synchronization function code not related to the block (
For example, r8YMj 1ll) is transmitted frame by frame,
On the receiving side, frames are received into a shift register. A method is used in which a reset pulse is sent to the frame receiving circuit by simultaneously detecting the funky code.

In this way, if a 7-function code is added to the information block, synchronized output is possible, but if an erroneous symbol occurs in the transmission frame and the information field changes to a funxion code, If this occurs, a second stage occurs on the receiving side.

This means that as the number of bits of the 7-anxi summer code decreases, the degree of desire for the occurrence of the IIIQI period increases. In the case of links with high multiplicity in digital transmission systems, W/j
If 4-synchronization occurs, the reliability of transmission will decrease. Also, when automatically correcting erroneous symbols that occur during code transmission on the receiving side, it is necessary to transmit the same number of information symbols as the number of symbols transmitted for correction, so transmission is suspended for that time. Must. These methods are not used when transmitting repeated frames.

The purpose of the present invention is to minimize the number of erroneous bits caused by erroneous synchronization, and to automatically correct erroneous bits, thereby eliminating transmission downtime for correction. The objective is to provide a self-correcting method.

In order to achieve the above object, the self-correction method of the present invention configures a code word including an information symbol according to an algebraic law, and then creates a code word following the initial code of the damaged code using the above algebraic law. Detects the timing when the conditions are met,
The reception clock phase is set at that timing, a code word is received at that clock phase, and in parallel, a code word received immediately before the code word is corrected.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 〇Pi) Synchronization method #I1 The diagram is a logic m* of a division circuit using a generator polynomial on the transmitting side.

A code word is created by dividing a polynomial having an arbitrary information symbol as a coefficient and having a frequency of (x-1) or less by its generating polynomial g(1). Consider a vector whose components are the logical values of each bit that constitutes a code word, and call this a code vector. In general, a code vector is constructed to consist of a given Kgi information symbols followed by <n-llll1 check symbols.

This check symbol corresponds to a self-correcting code.

Among the encoding methods described above, there is a method to obtain what is called a cyclic code, which is calculated using the following procedure.

Now, fo(7) is zm-1, x''-'+ ・-・-
Suppose that it is a polynomial such that the c coefficients are arbitrary information bits, and the coefficients with a frequency smaller than n- are 0. This corresponds to a vector in which the first n-K components are 0 and the following K components are arbitrary information bits. When such a polynomial foe is divided by the generator polynomial g(X), the following relational expression is established.

fo(x)−” g(X)q(1)+r(2)...
・・・・・・■ In the above equation α), rCx′) is g(
It has a smaller power than n-, which is the power of X).

Therefore, the following equation is derived from the above equation (2).

fo(X) r(3)-g(4)q(3)...
...(2) In the above formula (■), fo(3)-r (coset with 1 as representative (fo(4)-r(X))) is a code vector. r(X) is Since it has a power of U smaller than n -1c, all terms of power of n -K or more are 0. However, since all terms of power smaller than r- of fQ(3) are O. , f o(X) r
The higher frequency terms of (X) are the given information bits,
The term of low frequency is the check bit -r(X) determined by the information bit. Such a combined code vector can be created by the circuit shown in FIG. fQ(
The division by the generator polynomial g(X) in 1) is shown in FIG.

A polynomial foe with K information bits as high frequency coefficients and O as n -K low frequency coefficients is written as
The altitude number coefficient is shifted and input first. Against information symbols! It is necessary to perform n − K shifts for the zeros and low frequency zeros. [In Figure 1, to(
4) - No. q + (LIX + 11th x 2+)
qyu? )g(3)-ga+gIX+gsX"+・
The operation of dividing by gn - k Next, the first non-O output belongs. This is the first coefficient of the quotient at 1 QyxK n-. Since the polynomial +iig(1) must be subtracted from the dividend for each coefficient Jli of the dividing equation, this is done by the feedback circuit shown in FIG. After a total of 21 shifts, the completed quotient appears in the output. And the residual r(
3) is included in the shift register. The remainder r(3) is
Since these are check bits with a negative sign added, these check bits are assigned to 0 at the low precision position of (f<l) to form a sign vector.

Transmission is performed as follows. That is, the first fK information symbols are shifted into the device of FIG. 1 and transmitted to the communication channel in parallel. Once the K information symbols have been input into the shift register, the n- bits of the register will hold the remainder. This is a check symbol with a negative sign added. Next, the feedback circuit of the shift register is disconnected by a switching circuit, and the contents of the shift register are shifted out. At this time, the bit output from the shift register is transmitted to the communication channel through two of contacts 1 and 2 of the switching circuit (a) while inverting the polarity. These n −K check symbols are Kg
Complete the code vector with i's information symbols. Note that the circuit 3 is a circuit for sending out the start code and the end code.

FIG. 2 is a block diagram of a receiving circuit according to an embodiment of the present invention.

When a code vector transmitted using the method shown in jIllffl is input to the receiving side, this code is divisible by the generator polynomial g(X). The decoder comprises a buffer register 7 for storing the received code and a shift register for dividing the received code by g(X). If all the remaining bits of the division become ○, it means that the code vector has been received without error, and by detecting this, it is possible to synchronize the reception of the transmission frame.

In FIG. 2, the shift register registers -1 and coefficient devices -g to memory devices r0 to r□- of FIG.
9 to g-A-e, etc., and divides the code input from ) to the receiving terminal. At the same time, the received code is
The data is input to register 7 and temporarily stored.

The detection circuit 5 detects that each bit of the shift register number is all 0 and sends a signal to the clock generator 6. The multi-phase clock generator 6 operates by being supplied with a clock from the bit clock terminal (T) in order to generate a multi-phase clock for the receiving logic circuit. Terminal (G)
The clock from the block is also supplied to the other blocks in FIG. 2, thereby performing each operation. The output (E) of the detection circuit 5 is generated when each bit of the shift register number becomes O, thereby resetting the multiphase clock generator 6.

By resetting the multiphase clock generator 6, an AND circuit is generated from each symbol of the 87A register 7.
The phase of the multiphase clock is set so that the timing of output via the multiphase clock is appropriate.

Then, at each slot time of the transmission frame, the corresponding frame's 1111
The content of the client is read out. A reset pulse is generated every frame of the received code, and if a smear occurs, a reset pulse will not be generated. However, the clock supplied to the multiphase clock generator 6 is
Assuming that this reset pulse is unrelated, if the phase of the polyphase clock matches the reset pulse when the previous transmission frame is received, even if no reset is performed in the current frame, it will be correct. A multiphase clock of phases is obtained. A multiphase clock can be generated even without a reset pulse, but this does not mean that a reset pulse is not necessary; without this reset health, it will naturally not be possible to synchronize with the frame of the received code. When received, it is necessary to reset the multiphase clock generator 6.

The codes constituting the transmission frame are generated by the generator polynomial g(X
) is divisible by Seven frames of transmission are occupied by fields filled with such codes. The sign is divided,
At the time when the clock is turned off, the multiphase clock generator 0 of the receiver is reset by reset II- in FIG. 2, and the normal operating phase is maintained on the receiver side.

By the way, transmission frames are transmitted continuously without any transmission pause time. In such a situation, if an erroneous bit occurs and the remainder of the division created by Seattle register 4 does not become 0 in the normal timing, the division will still be performed even if the next transmission frame is transmitted correctly. The remainder will not be 0. Therefore, in order to prevent this from happening, it is necessary to provide a function field with a specific code structure indicating the beginning and end of the seven transmission frames in a field other than the code vector of the transmission frame. That is, a switching circuit (c) and a start and end code sending circuit 3 are provided on the transmitting side of FIG.
Before the switching circuits (a) and (b) are restored and the next information bit appears at the input terminal, the switching circuit (c) is reversed from 1 to 2, and the output signal from the sending circuit 3 starts after the end code. After transmitting the code, it returns to its original state.

On the receiving side, division by the generator polynomial g(3) is started immediately after the end and start codes are detected. For this purpose, it is necessary to provide a circuit for detecting the end and start codes, and the shift register 8 in FIG. 2 fulfills this role. The shift register 8 receives the code input from (to the receiving terminal) while shifting, and shifts the reset output when the code configuration created by the logical value of each bit is the above-mentioned end and start function code configuration. - Send to register 4 and reset the remaining registers of the divider circuit.

A method of providing a start and end N'' code and detecting them on the receiving side has been conventionally used, but in the present invention, the code vector can be detected without immediately resetting the multiphase clock circuit 6. The multiphase clock circuit 6 is reset by pressing .

Note that in order to reset the remaining registers without using the shift register 8 in FIG. 2, it is necessary to provide a space time equal to the transmission frame length, but this is not desirable because it causes a large loss in transmission efficiency. . That is, there should not be a long pause between the end of one transmission frame and the start code of the next transmission frame.

(b) Correction method FIG. 3 is a block diagram of an error correction circuit used in the present invention, and #4m is a block diagram of a synchronization and erroneous bit correction/parallel depth circuit showing an embodiment of the present invention.

Assume now that a code vector (f(7)) is transmitted.

If an error occurs at this time and the receiving side receives a code that is higher than the code vector by II(X), then
I(4) is an error pattern. Then, the received code is g
By dividing by (7), the yield pattern is also divided, and this division will be called a parity check. If the result of the parity check is the residual R(X), then the following equation holds.

E(X) -g(X) 8(3)+R(3)・・・・・・
...(3) Multiply the remainder R(1) by 11 and get g(X)
By dividing, it can be expressed as follows.

X1R(X) -g body) at(3) 10R1(1)...
(4) The following equation is derived from equation (3) above and equation (Hata).

X11i(X) R+(gradient 1g(7)S(1)10g(η81(3)......■-F Formula (5) is (X1l(X)-R1 (X)) shows that the code vector is te, and (xlx(3)) and (R1(X
)) should be included in the same coset. Error correction is carried out by executing the left side of equation (,51) above, and is carried out using the circuit shown in FIG.

In FIG. 3, 9 is the memory device (
This is a shift register having a circuit consisting of T o -rn- to -+) and its peripheral devices, and its contents are R1(3). (E) is the reception terminal of the communication channel, and the switching circuit (B) is closed during code reception, and the switching circuit ←
) is released M. Parity check is calculated by the division circuit 9 used during encoding over the entire received code vector. At the same time, the received code vector is stored in buffer 1
Recorded as 0. The parity check ends at the same time as the reception of the received code vector is completed, and then the switching circuit (b) is opened and the switching circuit (b) is closed in order to perform the correction according to the above equation (5). The shift register 9 is sequentially shifted so that when one symbol is read out, the buffer 1
One symbol is also read from o. This process is repeated, and in the step where there is an error, the output symbol of the shift register 9 is changed from the output symbol of the buffer 10 to the arithmetic unit 11! [Addition corrects the error.]

(to) is the terminal that obtains this corrected output.

The most likely type of error pattern is a burst error. This burst error pattern is (XJI(3
)). Therefore, the received code at this time is (f(3)+XjB(4)).

Receiver parity checking is performed by dividing f(3)+xjB(X) by g(X), and the remainder is retained. If the remainder is O, the codeword has been received correctly, but if it is not O, it means that it contains error information. Here, (f(3)) is a code vector or f
(X) is divisible by g(4). Therefore, parity
The remainder of the check is equal to jB(3) divided by g(4).

Now, assume that xjB(3) is expressed by the following equation.

XjB(X)-g(3)S(7)+R(4)...
...(6) Here, Huan Shu has the degree n − of g(3)
It has a power smaller than K.

The overprinting correction method explained in (1) to (5) above and the circuit shown in Figure #13 determine the above-mentioned XJB (3).

In the previous formula (3), [L(3))−(XjB(3)
) and i −n −j, the following equation is derived.

X1R(X) w, Xi+jB(X)-Xig(X)
8(X)-(xwx)n(Jz i g(1)s(x)
10m (3)・・・・・・・・・(7)Here, Xn-
1 is divisible by g(4), and B(3) is divisible by g(X
) has a frequency smaller than the frequency n −K, then
B(4) must be the remainder when xlpQQ is divided by g(3). Regarding this, (4) and (5) above,
) operation is nothing but deleting B(4).

Note that if the frequency of B(4) becomes larger than ]l-''L, the limit of the entertainment correction ability is exceeded, so correction will be performed by other means.

Figure 2 shows a circuit that performs frame synchronization on the receiving side.
The figure shows a circuit that performs error correction on the receiving side.

In order to use these to create a circuit that can perform synchronization and error correction, it is necessary to improve the circuit shown in Figure 2.

The shift register number in FIG. 2 corresponds to shift register 9 in FIG. 3, and buffer register 7 in FIG. 2 corresponds to buffer register 10 in the third [iU. Therefore, in order to improve the circuit shown in FIG. 2 to be correctable, it is necessary to adopt the threshold method shown in FIG. 3 on the output side of the buffer register 7.

However, in this state, it becomes impossible to continue receiving data from the receiving terminal (in FIG. 2) during decoding. Therefore, it is sufficient to provide two shift register numbers as shown in FIG. 2, one to maintain the state shown in FIG. 2, and the other to perform error correction according to the purpose shown in FIG. In other words, the contents of the shift register 4 are transferred to the other shift register 9 at the timing when the code is completely set in the buffer register 7 by the multiphase tarlock from the second multiphase clock generation circuit 6.
7, and then perform the error correction shown in FIG. 113.

FIG. 4 shows a circuit that simultaneously performs synchronization and correction of erroneous bits. This enclosure includes a synchronization shift register 14, a synchronization detection circuit 13 that detects when its output becomes 0,
A multiphase clock generation circuit 16 that is reset by the output of the synchronization detection circuit 13, and a shift register 1 for kneading correction.
1, a buffer register 12 for manually inputting the II code,
Shift register 17 shifted by multiphase clocks
and a reset circuit 15.

When the code of one frame inputted to the receiving terminal) is inputted to the synchronization shift register 14 and the buffer register 12, the shift register 14 converts the input code into goo.
Divide by and print the remainder. When the synchronization detection circuit 13 detects that the output of the shift register 14 becomes 0, the multiphase clock generation circuit 16 is reset with the output. When the multiphase lock generation circuit 16 outputs a clock indicating the time when the code of one frame ends, the contents of the synchronization shift register 14 are transferred to the shift register 11 having the same logical configuration, and thereafter , corrects the received code output from the buffer register 12 and transfers it to the next stage buffer register 17.

dl Since the remainder of the shift register 14 must be cleared in order to perform division of the subsequently received transmission frame, the output signal of the reset circuit 15 is sent to the shift register 14 via the reset line. Send to.

Extraction of information in a time slot of a new value of a transmission frame and transmission to another terminal are performed on the corrected data, that is, on the output side of the buffer register 17, in accordance with instructions from a polyphase clock. R of the 4th WJ is a receiving device, and S
is the transmitting device. The transfer from the buffer register 17 to the □receiving device member is performed by moving the logic game) 1.2.3, performing an AND with the #coffin lock output, and transmitting the result. Further, transmission from the transmitting device S to the transmission system located next to the buffer register 17 is performed through logic gate keys 5 and 6, ANDed with the multiphase clock output, and outputted to the buffer register 17. After temporarily storing the contents, the contents are shifted one hint at a time and transferred one bit at a time to the transmission system (A).

Note that the clock applied to logic gates L2, 3 appears one step earlier than the clock applied to the corresponding logic gate 4.5.6.
It is necessary to configure the multiphase clock generation circuit 16.

In the above explanation, error bits in frame transmission are self-corrected, but it can also be applied to writing to and reading from external storage devices used in information processing/systems, etc., and writing and reading are coded. By making the changes and corrections correspond to each other, it is possible to improve the credibility of the external storage device.

1. FIGS. 5, 6, and 7 all illustrate the operation I1. of the present invention. These are diagrams for explaining coral, in which Figure 5 is a circuit that divides an arbitrary polynomial by a specific polynomial, Figure 6 is a specific example of a division circuit on a field consisting of two elements, and Figure 7 is Figure 6. When dividing by hand, the following are shown.

Now, g(X)-go + gIX + ・・・・-+
= grxr a(x) −eL6+(LIX+...
...If you create a circuit to control +clnXn, it will look like the one shown in Figure 6.

Input the altitude number term in order, zr term to register 29, X''m sequentially...X term to register 22, register 21
Store 0 term in . Note - The device must be turned on initially. For the first r shift in which the first input symbol arrives at the last stage of the shift register, the output is O
It is. Then the first non-zero output appears. This is +ingψ and is the first coefficient of the quotient. For each coefficient gi of the dividing equation, the polynomial 'Jig(X) must be subtracted from the dividend. This is done by the feedback connection of FIG. After a total of nine shifts, the completed quotient appears at the output and the remainder remains in the shift register.

Figure 6 shows g(X)-1 on a field consisting of two elements.
+x"+ x'+ x5+ This is a circuit that divides the input polynomial by x@.Here, X1'+ zl+14+
xs+ 1 TEXl'l-x"+ x"+ xfu+X4
+X''+ In the case of the hand calculation shown in the figure, the advanced number terms are on the left, whereas in the shift registers 31-36 of FIG. 6, the advanced number terms are on the right.

In FIG. 6, the first six shifts have no correspondence with FIG. 7. Shift registers 31 after 6 degrees 7 degrees
The contents of ~36 correspond to part A in Figure 7.4. The first coefficient is the first quotient symbol and is also the output after the -7 sheets. The feed nick corresponds to the polynomial marked B and the next step is lowered to 717". After the 7th shift, the contents of the soft register become the polynomial marked D. The matching feedback is then 11 times t also matches E, F is the same as the input, and after the 8th shift, the contents of the shift register match G. This process is 14 This continues until the shift is repeated until 5 ft·l for each coefficient of the dividend.
- The register holds the quotient, and the quotient coefficient is output.

As described above, according to the present invention, the occurrence of erroneous synchronization and erroneous bits in a transmission system can be extremely reduced, and the transmission quality of a communication channel can be improved. Furthermore, it is possible to reduce the frequency and time of post-processing related to the transmission line at a terminal station or terminal using the transmission system. Furthermore, when applied to an external storage device, reliability can be improved.

[Brief explanation of the drawing]

Figure 111 is a logic diagram of the division circuit on the transmitting side, Figure 2 is a block diagram of the frame synchronization circuit used in the present invention, Figure 3 is a block diagram of the entertainment correction circuit used in the present invention, and Figure 4 is the block diagram of the entertainment correction circuit used in the present invention. Block diagram of a self-correction circuit showing an embodiment of jB
5, 6 and 7 are all explanatory diagrams of the operation of the division circuit of the present invention. 11: Error correction shift register, 12: Buffer register, 13: Synchronization detection circuit, 14: Synchronization shift register, 15: Reset circuit, 16: Multiphase clock generation circuit, 17: Buffer register 7, 21 to 36: Registers forming shift registers (Patent applicant Rico Co., Ltd.
People 0. □ 1 ゎ 4 True;'・.

Claims (1)

[Claims] α) A code word containing an information symbol is constructed according to an algebraic law, and following the start code of the received code, the above algebraic law is used to detect the timing that satisfies the condition of the code word. The self-correction method is characterized in that the reception clock phase is set at the timing, the code word is received at the reception clock phase, and the code word received before the code is corrected in parallel. method. (2) Correction of the code word is performed by changing the contents of the register jlJl, which has been confirmed to satisfy the algebraic law, to #! of the same configuration as the first register. 2. The self-correction method according to claim 1, wherein the self-correction method is stored in two registers and the content of the second register is used for the self-correction.