JP2952051B2 - Cell synchronous operation circuit in ATM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM for transmitting and receiving information in the form of cells by adding some redundancy to information .
The present invention relates to a cell synchronous operation circuit .

[0003]

2. Description of the Related Art In recent years, ATMs (Asynchronous) have been used.
Various studies have been made on broadband communication using a transfer mode (Transfer Mode) technique, and various discussions have been made in CCITT and the like to unify the schemes.
The communication by ATM is a communication in which a fixed-length packet called a cell is transmitted. The CCITT has been discussing the standardization of the communication system using this cell, and the content of the recommendation in the CCITT will be described below.

[0004] The cell length is 53 bytes, of which the header part is 5 bytes and the payload part is 48 bytes. Of the 5 bytes, that is, the 40-bit cell header, the first 32 bits are the cell type and VPI (Vir).
dual PathIdentifier), VCI
(Virtual Channel Identify
er) is written. The remaining 8 bits are a redundant portion for the 32 bits, and are HEC (Header Error Con).
troll). This HEC part takes advantage of the property of taking a value depending on the previous 32 bits,
As described later, it is used for cell synchronization and error correction / detection of a cell header on the receiving side and the receiving terminal unit of each node.

[0005] Here, the VPI and VCI in the cell header do not always take the same value from the transmitting terminal to the receiving terminal, and are often rewritten by nodes in the middle. Therefore, the HEC part needs to be calculated and added at the output device side of each transmitting device and each switching node.

[0006] The method of generating the HEC part is based on the characteristics of the cyclic code. First, 8 bits of HEC corresponding to the fifth byte of the cell header are all set to 0, and 40 bits of the cell header are represented by M (X) as a polynomial expression. For example, the cell header is expressed in binary notation of 0, 1 (000010001 0
0000010 00100001 00000110
00000000), M (X) becomes M (X) = X ³⁵ + X ³² + X ²⁵ + X ²¹ + X ¹⁶ + X ¹⁰ + X ⁹ (1) Here, the generator polynomial is G (X), and the above M
Assuming that the remainder obtained by dividing (X) by G (X) is R (X), for example, for the above M (X), R (X) = M (X) mod G (X) = X ⁷ + X ⁶ + X ⁴ + X ³ +1 (2) G (X) = X ⁸ + X ² + X + 1 When this R (X) is converted to a binary representation of 0, 1 (1,1,0,1,1,0,0,1), (0,1,0,1,0,1) , 0, 1) is added to the fifth byte of the header as the value of the HEC part, which is obtained by adding modulo 2 to a predetermined fixed pattern by a bitwise operation. That is, in the above example, the value of the HEC part is (1,1,0,1,1,0,0,0) (+) (0,1,0,1,0,1,0,1) = ( 1,0,0,0,1,1,0,1) (3), and therefore the cell header is represented in binary notation (000010).
01 0000001000100001 00000
110 10001101). Here, (+) indicates addition for each bit in modulo 2.

[0007] In communication using the ATM technology, since the transmitting side and the receiving side are not synchronized, it is not known when a cell arrives. Therefore, it is necessary to find the beginning of the cell in some way. Even if the cell synchronization can be achieved once, the phase at the head position may change due to circumstances such as a bit shift or the like, so that it is necessary to continuously monitor the phase. According to the recommendation of CCITT, a method of achieving cell synchronization by the above-described method using the HEC part is described.

First, the cell header generated as described above has the following properties. A 40-bit cell header generated by the above-described algorithm is represented as H (X) by a polynomial expression as described above. Now, a polynomial expression of (0, 1, 0, 1, 0, 1, 0, 1) in binary notation is subtracted from H (X). As a result, C (X) is C (X) = H (X) − (X ⁶ + X ⁴ + X ² +1) = M (X) + R (X) (4) In fact, C (X) is G (X) ) Is a code word of a shortened cyclic code in which C (X) is a generator polynomial, so that C (X) is divisible by G (X).

Using this, cell synchronization is achieved. That is, first, the 34th, 36th, 38th, and 40th bits are inverted with respect to the 40 bits that are considered to be cell-synchronous, and then the 40 bits are divided by G (X). , And the head of the cell header is regarded as the head of the cell.

By the way, the HUNT state, P
There are three states, a RESYNC state and a SYNCH state, which will be described.

First, a state in which cell synchronization is not achieved at all is H
It is called UNT state. At this time, the head position of the cell is searched for each bit. That is, after performing the above-described bit inversion on an arbitrary 40 bits, division by G (X) is performed, and a portion where the remainder becomes 0 is searched.

Once a part which can be correctly divided is found in this way, it is regarded as a temporary cell header and PR
It goes into the ESYNC state. In the PRESYNC state, the assumed header portion is fixed, so that the header portion is divided for each cell. If the data is divided by DELTA times consecutively and correctly, it is almost certainly regarded as a cell header portion, and a SYNCH state is set. However, if an erroneous cell header is obtained even once, the state returns to the HUNT state again.

In the SYNCH state, the method of calculating the cell header is exactly the same. However, in this state, if the division for the cell header cannot be continuously performed by ALPHA times, the state returns to the HUNT state. Otherwise, keep this state.

As described above, when the cell header is correct,
If it is expressed as H (X) in a polynomial expression, the corresponding C (X)
Is a code word. Since this code uses G (X) as a generator polynomial, the minimum Hamming distance is 4. That is, each codeword has at least a 4-bit difference of 0 and 1 from other codewords. Because G (X) is expressed as follows: G (X) = X ⁸ + X ² + X + 1 = (X + 1) (X ⁷ + X ⁶ + X ⁵ + X ⁴ + X ³ + X ² +1) (5) This is because it is factored into polynomial products. Therefore, when this is used, 1 of the cell header is used.
Bit error correction / 2-bit error detection or 3-bit error detection is possible.

In the SYNCH state, a search is performed for each cell by the same operation as that used for cell synchronization. In addition to determining whether the cell is divisible, if the cell cannot be divided, the header is regarded as having an error. Corrects or detects errors. The method depends on designation of one of the error correction mode and the error detection mode.

In the error correction mode, if an erroneous header is determined, if the header error at that time is one bit, it is corrected. If an error of 2 bits or more is found, the cell is discarded. In the error detection mode, on the other hand, when the cell header is found to be incorrect, the cell is discarded.

When the state shifts from the PRESYNC state to the SYNCH state, the operation starts from the error correction mode. As long as the correct header is obtained in this mode, the mode remains as it is. If an incorrect header is obtained, correct or detect the header according to the wrong number of bits,
Transition to the error detection mode. In the error detection mode, if a correct cell header is obtained once, the mode transits to the error correction mode. If there is an error in the header, it indicates that it has been detected.

Next, there are two types of cell transmission, one with and without an external frame, the one without an external frame is cell-based, and the one with an external frame is SDH.
(Synchronous Digital Hier
achy) called the base. In the case of the SDH base, a byte cycle can be obtained from information from the frame. That is, if the input data sequence is divided into 8 bits on the receiving side, it is possible to obtain information as to which bit of the 8 bits the head of the cell is. Therefore, in this case, the cell synchronization described above only needs to be checked for each byte using the specific bit as a starting point.

In the case of the SDH base, the transmitting side scrambles only the 48-byte payload portion. This is because it is extremely difficult to achieve bit synchronization if 0 or 1 continues in succession in the information portion intentionally or accidentally. On the other hand, on the receiving side, in the PRESYNC state and the SYNCH state, the cell header and the payload portion can be separated, so that only the 48-byte payload portion is descrambled. This is a self-synchronous scrambler / descrambler, and the generator polynomial is F (X) = X ⁴³ +1 (6). Whether or not the data used for the scrambling and descrambling includes a header portion is not specified, but it is usually interpreted to exclude the header portion. Since the payload portion is not clear in the HUNT state, this descrambler is not performed. Note that another scrambling scheme has been proposed for the cell-based case.

By the way, what has been described above is the recommendation of CCITT for standardization. As a specific circuit realizing method for the CCITT recommendation, for example, Toshima and Tatsuno, "Study of Cell Synchronous Circuit Configuration Method by Header Error Control" (Proceedings of IEICE Tech.
9-70), Tatsuno and Tokura, "A Study of Cell Synchronization Method Using Header Error Control" (IEICE Technical Report DSP 89-51). According to these proposals, it is shown that a cell can be synchronously searched for at least one bit on a cell basis, and one byte for an SDH based parallel input. In addition, it is described that it is possible to have both the cell synchronization function and the header error control function, but there is no description about a concrete method of realizing the circuit.

When cell synchronization is actually performed in the HUNT state, a 5-byte portion corresponding to the header length of input data is checked, and a search is made as to whether the fifth byte is the head of the cell. Sometimes, 4
It is necessary to always accumulate 3-bit data. When the 5-byte portion is considered to be the head of the cell, as described above, a PRESYNC state is entered immediately after that, and data from 43 bits before the header portion excluding the header portion is included in the descrambling of the payload portion. Because it is used. If it is determined that the inspected 5 bytes are not at the head of the cell, the data is shifted and the inspection of the next 5 bytes is performed. It becomes a part of 43-bit data. Therefore, it is necessary to accumulate the data of 5 bytes to be inspected during the inspection. That is, in order to realize the functions of cell synchronization and payload descrambling, a data storage unit for a total of 83 bits is required.

Next, when cell synchronization is to be performed in the HUNT state, when a search is to be performed for each bit or byte, re-inputting 40 bits each time to the inspection circuit requires a large processing overhead, which greatly increases the processing overhead. It takes time. Therefore, when shifting from a certain 40-bit test to the next 40-bit test, a new 1-bit or 1-byte is input, and at the same time, 1
A countermeasure is taken by using a bit or 1 byte so as to cancel the value of the old data in the inspection circuit. In this case, it is necessary to accumulate 1-bit or 1-byte data 5 bytes before to cancel when newly inspecting.

Furthermore, in the error correction mode in the SYNC state, the presence or absence of the header error is checked for the input cell header, and in the case of a one-bit error, a correction pattern is generated, and the exclusive OR is added to the header part. In general, it is necessary to add a circuit for storing the cell header from when the header is input to the header error check circuit until the correction pattern is output.

Regarding the necessity of the storage circuit as described above,
Although not described in the above document, in the prior art, in this case, these circuits can be interpreted as being provided separately. Therefore, there is a problem that the circuit scale becomes large due to these storage circuits.

Regarding the HEC generation method in the transmission side circuit, Tanaka, Yanagi, Takase, Furuya, Takasaki, “Parallel H
Examination of EC calculation circuit "(1990-76
FIG. 6 shows a generation method using a divider circuit for both serial input and parallel input according to 5). This prior art is also used in the examples for comparison. However, in this conventional method, only the divider circuit is used, all the last 8 bits in the cell header 40 bits must be set to 1 in advance, and the HEC portion is generated after inputting all 40 bits. Therefore, H generated after the last data is input
There is a problem that an 8-bit delay occurs before the EC portion comes out, which not only takes extra time but also increases the 8-bit delay circuit.

[0026]

As described above,
In the conventional HEC generation circuit on the transmission side corresponding to CCITT, there is a problem that an input / output delay corresponding to 8 bits and a delay circuit corresponding thereto are added because only the divider circuit is used.

On the receiving side, a data storage circuit in a cell header portion for simultaneously realizing a cell synchronization function and a descrambling function, and correction necessary for generating a correction pattern for performing header error correction are performed. The input data to the storage circuit of the power cell header section and the input circuit to the inspection circuit for cell synchronization should be at least one bit per serial input and at least one bit per 8 bit parallel input.
When updating every byte, it is considered that a circuit for storing the oldest data of 1 bit or more or 1 byte or more to be removed from the inspection circuit is considered to be necessary. As a method of realizing a synchronous circuit and an error control circuit, there is no method considering these storage circuits, and it has been assumed that these circuits are separately provided.

The present invention has been made in view of the above points, and an object of the present invention is to generate an HEC on an ATM transmitting side capable of minimizing a delay and reducing a circuit size of an input cell header. Is to provide a circuit.

Another object of the present invention is to provide an ATM receiving circuit system capable of reducing the circuit scale of a data storage unit in achieving a cell synchronization function and a descrambling function.

[Structure of the Invention]

[0031]

SUMMARY OF THE INVENTION The feature of the present invention is that an ATM is used.
In the transmission circuit system, at least multiplication using the first polynomial and division using the second polynomial are performed simultaneously on the input cell header, and redundant bits for the cell header are generated using the remainder of the division circuit. A cell header generation circuit having an HEC generation circuit is provided.

Another feature of the present invention is that in an ATM receiving circuit system, a function of storing data of a cell to be inspected for cell synchronization, and a function of updating data input to the inspection circuit for cell synchronization. And a function of storing data to be removed from the check circuit at the time of error correction, and when performing error correction on the whole or a part of the cell using the redundant bits, the redundant data is stored until a correction pattern of the corrected data is generated. The function to store the data of the cell protected by the bit,
That is, the shift register circuit provided at the same time is provided.

[0033]

On the transmitting side of the ATM according to the present invention, when generating redundant bits for the cell header, the remainder obtained by directly multiplying the original data by a certain polynomial and dividing the output by the polynomial of the corresponding division circuit is used. , A redundant bit can be generated immediately after the original data is input, and this is immediately added to the cell header of the packet, thereby minimizing the delay in the circuit from the input of the data signal to the output of the data signal. be able to. This also eliminates the need for a delay circuit required when there is a delay, thereby reducing the circuit scale.

On the receiving side of the ATM according to the present invention, a data storage function of a cell header portion necessary for simultaneously realizing descrambling applied to a payload portion of a cell and cell synchronization, and a function for cell synchronization. When the input data to the inspection circuit is updated at least every bit in the case of serial input and at least every byte in the case of 8-bit parallel input, one or more bits or one or more bytes to be removed from the inspection circuit are updated. The function of storing data and the use of redundant bits are used to check for errors in the whole or part of the cell. If an error is found, the error correction pattern is generated when the error is corrected. By using a shift register circuit that has the function of storing until the
The circuit scale can be reduced.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The following embodiments will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a cell generation operation circuit in an ATM transmission circuit system according to the present invention.

As input signals, a cell clock 101,
There is a cell length data signal 102, and the cell clock 101 is inputted while maintaining some relationship with the head of the cell of the cell data. For example, the input pattern is such that the cell clock 101 rises at the same time as the first bit of the cell length data signal 102 is input, holds it for a fixed number of clocks, and then falls. The cell length data signal 102 input here has a header portion rewritten or written in the previous stage of this circuit, and therefore, although the cell length is maintained, the fifth byte of the header is correct. An input signal that does not always take the value of HEC is assumed.

The cell counter 10 has a cell clock 101
Is reset by detecting the rising or falling edge of. Also, when just one cell length is counted, it automatically returns to the original state. Therefore, normally, the counter 1
By looking at the output value from 0, it is possible to know which part of the cell is currently being input or output. Thus, the control circuit 1 that has received the output signal 103 of the counter value
1 outputs a necessary control signal as appropriate based on these values. Further, once the cell clock 101 is input, the previous timing is retained as long as the timing does not change. Therefore, it is not always necessary to input the cell clock 101 every time. In addition, even if there is some abnormality in the previous circuit and the data length may temporarily change, etc., the correct state can be restored by inputting the first correct cell clock signal after recovery from the abnormal state. it can.

In the HEC generation circuit 12, the control signal 104
, The first 4 bytes of the header portion are taken from the cell data input and the fifth byte HEC is generated. Therefore, the output signal 109 from the HEC generation circuit 12 is a signal in the form of a complete cell having a cell header of 5 bytes and a payload of 48 bytes as specified. Details of this circuit will be described later.

The selector 13, the shift register circuit (A) 15, and the shift register circuit (B) 16 together perform self-synchronous scrambling by F (X) shown in the above equation (6). This scramble is referred to as scramble (P) to distinguish it from other scrambles described later.
I will call it. The shift register circuit (A) 15
It has a 43-bit register, and the output signal 110 from the selector 13 is directly input to the register.
The shift register circuit (B) 16 has a register having a length of 40 bits, and the output signal 106 from the shift register circuit (A) 15 is directly input to the register.

The cell data signal 109 output from the HEC generation circuit 12 is divided into three, the first being to the selector 13 as it is, and the second being to the shift register circuit (A) 15
Is exclusive-ORed with the output signal 106 from the
The signal reaches the selector 13 as 08, and the third signal is exclusive-ORed with the output signal 112 from the shift register circuit (B) 16, and reaches the selector 13 as a signal 107. In the selector 13, the signal 109 from the control circuit 11 selects the signal 109 when the header portion passes, the signal 107 for the 43-bit clock after passing the header, and the signal 108 otherwise, and selects the signal 108 as the output signal 110. Output.

The details of this selection operation are shown in FIGS.
(B) and FIG. 2 (C). As described above, the scrambling (P) by F (X) is applied only to the payload portion of the cell. Therefore, when the head bit of the cell arrives at the signal 109, the selector sets the signal 1 as shown in FIG.
09 is connected to output 110. That is, it passes without operating anything. This header part is the shift register circuit (A) 15
Are sequentially input and shifted.

When the 40-bit cell header passes through the selector 13, the signal 109 becomes the first payload bit. Therefore, it is necessary to scramble (P) here. In scrambling by F (X), it is necessary to take an exclusive OR of the scrambled (P) payload bits 43 bits before. At this time, the shift register circuit ( A) 15 has a header of 40 bits, which is not used as scramble (P) data. The required payload signal 43 bits ahead is the bit of the signal 112 output from the shift register circuit (B) 16.
Therefore, as shown in FIG.
The signal 107 obtained by performing an exclusive OR operation with 09 is selected and output as the signal 110. In this manner, the contents of each shift register circuit are sequentially shifted. Since the total of the payload bits 19 in both shift register circuits is always 43 while the cell header 40 bits are in both shift register circuits, During that time, the signal 107 is selected.

When all the 40 bits of the cell header enter the shift register circuit (B) 16, all 43 bits of the shift register circuit (A) 15 become scrambled data of the payload portion. (A) Output signal 106 from 15 and signal 1
A signal 108 obtained by performing an exclusive OR operation with 09 is newly scrambled data. Therefore, this signal is selected and output as a signal 110. This continues until the signal at the head of the next cell arrives as the signal 109. The above is repeated in order.

FIG. 3 shows another embodiment relating to the scrambling (P) of the payload. Reference numeral 109A denotes a complete cell signal similar to the signal 109 in FIG. 15A
Indicates a shift register circuit having a length of 43 bits, which has an enable terminal 15B. According to the signals H and L inputted thereto, whether an external signal is input and shifted or the current data is held. Is determined.
The output 112A signal of the shift register circuit 15A takes an exclusive OR with the signal 109A and reaches the selector 13A as a signal 108A. Either the signal 109A or the signal 108A is selected according to the value of the signal 105A, which is a control signal to the selector 13A, and is output as the signal 110A. The signal 110A is an input signal to the 43-bit shift register circuit 15A. The signal 105A also serves as a control signal to the enable terminal of the shift register circuit 15A.

When the cell header portion passes as signal 109A, selector 13A selects signal 109A and outputs it to signal 110A. At this time, the shift register circuit 15A contains an enable signal, the signal input to the register is ignored, and the contents of the register are held. When the payload of the cell passes as signal 109A, selector 13A selects signal 108A and outputs it to signal 110A. At this time, the shift register circuit 1
5A contains no enable signal, the signals are sequentially input to the register, and the signal 108A is a signal that has been scrambled (P) by F (X).

FIG. 3 except for the enable terminal 15B is the same as the scramble (P) described in the section of the prior art.
It contains the header as the data for use. That is, the correct HEC is stored in the 43-bit shift register circuit 15A.
The cell header to which the portion is added and the scrambled (P) payload are sequentially input, and the payload portion is scrambled using this data.

Returning to FIG. 1, the output signal of 110 can be output as it is, or can be output as an output signal 111 through the cell scramble circuit 14. The cell scramble circuit 14 is a self-synchronous scrambler applied to the entire cell. The purpose is that when this signal is transmitted as an optical signal, H or L is long and continuous when converted to an electric signal on the receiving side.
It is to prevent the bit clock from being unable to be extracted. This scramble is referred to as scramble (Q) to distinguish it from the above-described scramble of only the payload portion. FIGS. 4 and 5 show a detailed configuration example of the scramble (Q) circuit. In the D flip-flops described in the following description, the first, second, third, and the like are shown in order from the left in the drawing to distinguish them.

FIG. 4 shows the simplest method for realizing the above-mentioned object. Reference numeral 20 denotes D flip-flops, which are arranged in order of seven in this example. The contents of the seven D flip-flops 20 are values delayed from 1 to 7 bits of the output signal 111, respectively. Reference numeral 113 denotes a signal which becomes H only when the contents of the above seven flip-flops are all H or L. The fact that this signal 113 is H means that the output of the latest 7-bit signal 111 is L Or H was continuous. 11
0 indicates cell data in which only the payload portion has been scrambled. The data is exclusive-ORed with the signal 113 and then output to the outside as a signal 111. That is, in FIG. 4, the signal 110 and the signal 111 are normally output as they are as the signal 111. However, if the signal 111 includes an H or L signal that is continuous for 7 bits,
The next signal 111 has a relationship such that the signal 110 is inverted.

FIG. 5 shows an example in which the following E1 (X) is used as the scramble (Q) polynomial.

E1 (X) = X ⁷ + X + 1 (7) There are seven D flip-flops 20. As in FIG. 4, the contents are the values of the output signal 111 delayed by 1 to 7 bits. The signal 114 is output from the seven D flip-flops 20.
Is a signal which becomes H when the contents of all are L, and a signal 115 is a D flip-flop 2
Exclusive OR of the values at both ends of 0. The signal 110 is the same input signal as in FIG.
4 and the signal 115 are exclusive ORed,
Output as signal 111.

The difference between the embodiments of FIGS. 4 and 5 is that the signal 113 is the latest 7-bit H or L of the signal output 111.
Signal 114 becomes H due to the continuation of only the L signal, while the signal 114 becomes H due to the continuation of. This is to consider which configuration to use depending on the input pattern of the signal 110.
When the ratio of the continuation of the signal is very small compared to the ratio of the continuation of the L signal, the continuity of the L signal and the H signal is reduced by using the signal 114 rather than by using the signal 113. Similarly, there is also a method of performing an exclusive OR operation with the signal 110 only when the H signal is continuous with the signal 111.

In FIG. 5, the data is further scrambled so that the H and L signals are mixed well. Although a seventh-order polynomial is used in this embodiment, the optimal polynomial order should be changed depending on the performance of an O / E converter for converting an optical signal into an electric signal, and is not specifically described here. .

As described above, the case of serial input has been described with reference to FIGS. 1 to 5, but the same configuration can be applied to the case of parallel input. Further, since all the operations are caused by the cell clock input as described above, this circuit does not require a reset signal. Further, the signal 102 can be output as the signal 110 or the signal 111 without delay of one bit clock.

FIGS. 6 and 7 show an example of the configuration of the above-described HEC generation circuit. FIG. 6 shows a conventional example using only a dividing circuit according to a conventional method, and FIG. 7 shows an example of a system according to the present invention, in which a dividing circuit and a multiplying circuit are combined.

That is, in the conventional example of FIG. 6, the circuit portion 21 fed back via the switch 22A and subjected to exclusive OR as described later corresponds to a division circuit, and in the embodiment of FIG. As will be described later, the circuit portion 24 that is fed back and XORed corresponds to a division circuit, and the forwarded and XORed circuit portion 25 corresponds to a multiplication circuit.

In the conventional example shown in FIG. 6, reference numeral 201 denotes a cell length data input similar to 102 in FIG. 1, which has a fixed cell length and the HEC portion of the fifth byte of the cell header is all input as an L signal. And The signal 201 is divided into two parts, one is input to the 8-bit shift register circuit 25, and the other goes to the switch 23A.

The switch 23A is turned ON only in the first five bytes of the cell of the input signal 201, and is turned OFF in the other parts to block the signal. While the switch 23A is OFF, the eight D flip-flops 2
0 has been reset. When the switch 23A changes from OFF to ON, the reset of each flip-flop 20 is released. At this time, the switch 22A is also turned off.
It changes from F to ON.

The signal 203 is the output signal of the eighth D flip-flop 20 as viewed from the data input side. The signal 203 is exclusive-ORed with the signal passed through the switch 23A and enters the first D flip-flop 20. . At the same time, the outputs from the first and second D flip-flops 20 are exclusive-ORed with the signal 203, and enter the second and third D flip-flops 20, respectively. This operation means that the D flip-flop 2 is applied to the 40-bit cell header passing through the switch 23A.
That is, division is performed using a circuit composed of exclusive OR of 0 and 2 inputs. When the relationship is expressed by an expression, a [40] X ³⁹ + a [39] X is expressed by a polynomial expression on GF (2) when the head of the 40-bit header is a [40] and the end is a [1]. ³⁸ +... + A [1] = (X ⁸ + X ² + X + 1) Q (X) + R (X) (8) R (X) = r [8] X ⁷ + r [7] X ⁶ + r [6] ^{X 5 + r [5] X} 4 + r [4] X 3 + r [3] X 2 + r [2] X + r [1] a [i] (i = 1~8) = 0 a [i] (i = 9~ 40) = 0 or 1 r [i] (i = 1 to 8) = 0 or 1 From the signal 203, values obtained by converting the quotient Q (X) into a bit string are sequentially output. The i-th content of the D flip-flop 20 immediately after all the 40 bits of the header have passed through the switch 23A is r [i], which corresponds to the value of each term of the remainder R (X) in the above equation.

When the 40-bit cell header has passed from the switch 23A, the switches 23A and 2
2A switches OFF. Therefore, the value of the signal 203 thereafter becomes data from r [8] to r [1].

Reference numeral 206 denotes a signal obtained by delaying the 201 signal by the 8-bit shift register, and 202 denotes 2 signal.
3 shows an inverted signal of the 03 signal. 26A indicates a selector,
According to the control signal 205, one of the signals 203, 202, and 206 is selected as an output signal 204. Normally, the signal 206 is selected.
The next timing when the bit is input, that is, the selector 26A outputs the 32nd bit of the cell header from the signal 206 to the signal 2
04 and the signal 203 and the signal 202
Is switched and selected for each bit in this order, and data for a total of 8 bit clocks is output as a signal 204. Thereafter, the signal 206 is selected again. This results in signal 204
The fifth byte of the cell data output from
[8], r [7] (+) 1, r [6], r [5] (+)
1, r [4], r [3] (+) 1, r [2], r [1]
(+) 1), which means that the HEC portion has been added.

The problem of FIG. 6 is that it is necessary to shift the input signal by 8 bits, which causes a delay of 8 bits until the input signal is output, and requires an extra circuit. That is, the value of the fifth byte of the input signal 201 must be all L. An embodiment of the present invention that solves this is shown in FIG.

The input signal 102 is the same as that shown in FIG. 1, and the value of the fifth byte of the header is arbitrary. Signal 102
Is divided into two, one being an input signal to the selector 26 as it is, and the other being an eight D flip-flop 20
The exclusive OR of the signal 207, which is the eighth output signal, is input to the switch 23.

The switch 23 is turned ON only when the input signal 102 is the first 4-byte portion of the cell, and is turned OFF in the other portions to block the signal. While the switch 23 is OFF, the eight D flip-flops 20 are reset. When the switch 23 changes from OFF to ON, the reset of each D flip-flop 20 is released.

The signal passed through the switch 23 enters the first D flip-flop 20 as it is. At this time, the exclusive-OR of the outputs from the first and second D flip-flops 20 is calculated at the same time to obtain the second and third outputs, respectively.
The D flip-flop 20 is entered. This operation means that the 32-bit cell header that has passed through the switch 23 is multiplied by X ⁸ using a circuit composed of a D flip-flop 20 and an exclusive OR of two inputs. That is, division by a polynomial of X ⁸ + X ² + X + 1 is performed. In the equation (8), a
Considering that all of [1] to a [8] are L, the left side can be modified as follows.

A [40] X ³⁹ + a [39] X ³⁸ +... + A [1] = a [40] X ³⁹ + a [39] X ³⁸ +... + A [9] X ⁸ (9 ) = X ⁸ (a [40] X ³¹ + a [39] X ³⁰ +... + A [9]) a [i] (i = 1 to 8) = 0 a [i] (i = 9 to 40) ) = 0 or 1 Therefore, from Expressions (8) and (9), X ⁸ (a [40] X ³¹ + a [39] X ³⁰ +... + A [9]) = (X ⁸ + X ² + X + 1) Q (X) + R (X) (10) R (X) = r [8] X 7 + r [7] X 6 + r [6] X 5 + r [5] X 4 + r [4] X 3 + r [3] X ² + r [2] X + r [1] a [i] (i = 9 to 40) = 0 or 1 r [i] (i = 1 to 8) = 0 or 1 At the time of input, 8 D flips r to drop 20
[8] to r [1] are entered. Therefore, when the 32-bit data passes through the switch 23, the switch is turned off.

Reference numeral 208 denotes an inverted signal of the signal 207. 2
Reference numeral 6 denotes a selector, and a control signal 10 from the control circuit 11
In accordance with 4, one of the signals 102, 207, and 208 is selected to be an output signal of 109. Normally signal 10
2 is selected, the signals 207 and 208 are output from the next timing when the 32nd bit of the cell is input from 102, that is, immediately after the selector 26 outputs the 32nd bit of the cell header from 102 as the signal 109. The data is switched and selected for each bit in order, and data for a total of 8 bit clocks is output as a signal 109. Thereafter, the signal 102 is selected again. As a result, the fifth byte of the cell data output from the signal 109 becomes (r [8], r
[7] (+) 1, r [6], r [5] (+) 1, r
[4], r [3] (+) 1, r [2], r [1] (+)
1), which means that the HEC portion has been added.

In this circuit, the signal 102 has no delay,
The signal 109 becomes a signal to the selector 13, and the circuit scale of the shift register circuit can be reduced as compared with FIG. Further, since 8 bits from a [1] to a [8] are not used as input data to the circuit of FIG.
The 8 bits in the input signal 102 may be any value.

FIG. 8 is a circuit diagram when the multiplication / division circuit in FIG. 7 calculates in 8-bit parallel. The MSB (Most Significant) at the top of FIG.
Cant Bit) and the LSB at the bottom is
(Least Significant Bit). The MSB is the highest order of the 8-bit parallel signal,
The head of the cell is always the MSB. Each signal of 4 bytes of the cell header which is input in parallel as 8 bits as the signal 210 is exclusive-ORed using each data of 1 byte before, and as a result, each flip-flop 20 receives r [8] to r [1]. The data comes in as a result. The even-numbered bits are inverted and output as a parallel signal 211.

FIG. 9 is a block diagram showing one embodiment of the cell synchronization operation circuit in the ATM receiving circuit system according to the present invention.

As an input signal, the bit clock signal 30
There is a cell data signal 301 scrambled as 2, and the bit clock signal 302 goes to all parts of the receiving system circuit and is input to the clock monitor circuit 37. Normally, data transmission to the receiving side is assumed to be performed by light, so it is necessary to confirm that bit clock extraction is performed correctly in the photoelectric converter at the preceding stage of this circuit.
This is the purpose of the monitor circuit 37. Therefore, the frequency of the bit clock 302 is divided and output as a signal 310 so that it can be monitored that the clock is correctly input to the circuit.

As the input data signal 301, two types of signal input patterns, ie, the signal 110 and the signal 111 in FIG. 1, can be considered. If the input is from signal 110,
Since the scramble (Q) has not been applied to the entire cell data, the selector (A) 34 directly connects the signal 301 to the signal 304. When the input is from the signal 111, the selector (A) 34 passes the signal 301 through the cell descramble circuit 30 and connects the signal 303 which is descrambled output data to the signal 304. This will be referred to as a descrambling (q) to distinguish it from a descrambling described later.

The cell descramble (q) circuit 30
It is used in a pair with the cell scramble (Q) circuit 14 of FIG. 1 and its circuit structure is basically the same as that of the embodiment of the cell scramble (Q) circuit 14 of FIGS. These scramble (Q) circuits 14
The descramble (q) circuit 30 is a modification of the self-synchronous type. Therefore, when a bit error occurs in the transmission path, the error may be enlarged when the descramble (q) occurs.

In the case of the embodiment shown in FIG. 4, an H or L signal was received continuously for 7 bits due to an error in the transmission path, or a 7-bit H or L signal should have been originally continuous. If this is not so received due to a bit error, the error may be spread by the descramble circuit, but otherwise no spread of the error occurs.

Further, in the case of the embodiment of FIG. 5, in addition to the same error expansion as in FIG. 4 when the L signal continues, the descrambling (q) by the polynomial E1 (X) in the equation (7) is used. ) Causes error propagation. The extent of the expansion depends on the number of terms in the polynomial used for descrambling (q). For example, in the case of the polynomial E1 (X), a one-bit error during transmission becomes a three-bit error because it is a three-nominal.

It is inevitable that the error is enlarged by the descrambling (q) as described above.
In order to minimize erroneous cell delivery, an increase in errors in the cell header section should be detected as much as possible. For this reason, for a one-bit error during transmission, the error is expanded to cause erroneous correction of the header part or an undetectable error,
It is necessary to select a scramble (Q) polynomial so as not to have a cell header shape different from the original. Some similar polynomials of the same degree may or may not be appropriate, and these will be described using the following E2 (X) polynomial as an example.

E2 (X) = X ⁷ + X ⁶ +1 (11) If there is a 1-bit error in the k-th bit of the cell header, the polynomial E
2 (X) header enlarged errors by descramble (q) by ERR (X) has a ^{ERR (X) = (X 7} + X + 1) X 33-k + H (X) (12). From ERR (X), the aforementioned 34, 36, 3
After subtracting the polynomial corresponding to the bit inversion of the 8th and 40th bits, the remainder S obtained by dividing by the generator polynomial G (X) of the HEC part
(X) When determining the S (X) = (ERR ( X) - (X 6 + X 4 + X 2 +1)) modG (X) = (H (X) - (X 6 + X 4 + X 2 +1)) modG ( X) + (X ⁷ + X + 1) X ^33-k mod G (X) = (X ⁷ + X + 1) X ^33-k mod G (X) X ¹²⁶ mod G (X) = X ⁷ + X + 1 ∴S (X) = X ¹²⁶ · X ^33-k mod G (X) = X ¹²⁷ · X ^32-k mod G (X) = 1 · X ^32-k mod G (X) = X ^32-k mod G (X) (13) where k is 32 or less The header error at the k-th bit in the transmission is (32) as a result of the descrambling (q)
-K) It is regarded as an error of the bit and erroneously corrects the header. If k is larger than 32, there is no 1-bit correction pattern for the error expansion, so that no error is corrected and an error is detected. Some of such phenomena do not occur due to the polynomial. For example, the descramble (q) based on the polynomial E1 (X) is
Despite being a dual polynomial with (X), any one-bit error in the cell does not cause erroneous correction of the cell header. Therefore, it is better to select such a polynomial.

Output signal 304 from selector (A) 34
Is data in which the header portion is the original cell header type and only the payload portion is scrambled (P) by F (X). This signal is branched into two, one is input to the shift register circuit (C) 31 and the other is input to the cell synchronization / header error control circuit 33. The feature of the circuit 33 resides in that both the function of cell synchronization and the function of error correction / detection of the cell header are realized by sharing the same circuit.

Normally, in the case of cell synchronization, it is necessary to input 40 bits, and it is necessary to delay data during this period. Also, a delay circuit for at least a 40-bit clock is required to correct the error of the cell header. However, if the cell synchronization and the header error correction / detection circuit are shared, and the delay shift register circuit required for that is shared, the circuit scale can be reduced. Further, in order to achieve cell synchronization as soon as possible, it is preferable to search for each bit in the HUNT state, but this requires data obtained by delaying the input signal of the cell synchronization circuit by exactly 40 bit clocks. As this delay circuit, the shift register circuit (C) 31 shared for cell synchronization and header error control can be used.

FIG. 10 shows an embodiment of the cell synchronization / header error control circuit. The operation of this circuit is based on the HUNT, P
Since it differs depending on each state of RESYNC and SYNCH,
The operation in each state will be described in order.

Reference numeral 315 denotes a signal from the shift register circuit (C) 31, which is obtained by simply delaying the signal 304 by a 40-bit clock. The signal 316 indicates that the values of the eight D flip-flops 20 are (L,
H, L, H, L, H, L, H). When the signal 316 becomes H, this means that the most recently input signal for 40 bits is a cell header candidate. The signal 317 is
The signal is such that it always becomes H when the values of the eight D flip-flops 20 become (L, H, H, L, L, L, H, L) in order from the right overhead.

In the HUNT state, switches 43 and 44 are turned on, and switches 45 and 46 are turned off.
It has become. The signal 304 is exclusive-ORed with the eighth output of the eight D flip-flops 20, and
The signal is input to the first D flip-flop 20. At this time, the output of the eighth D flip-flop 20 also takes the exclusive OR with the first and second D flip-flops 20 at the same time. The above operation is the same as the operation of a general division circuit as shown in FIG.

Here, the signal 315 is further exclusive-ORed with the outputs of the first, fifth, and sixth D flip-flops 20, which are exclusive-ORed with the eighth D flip-flop 20, respectively. , And enters the D flip-flop 20 at the next stage. By using this special division circuit, the latest 40
The remainder of the division on the bits can be determined. This principle will be described below.

In a general division circuit as shown in FIG. 11, the remainder obtained by dividing an arbitrary input in GF (2) by a polynomial G (X) is stored in eight D flip-flops 20. It is configured to store. It is assumed that a certain 40-bit input is input as the signal 304A.
This signal is represented by P (X) in a polynomial expression, and the remainder obtained by dividing the signal by a polynomial G (X) is represented by B (X). B
(X) and P (X) are represented as follows.

P (X) = p [40] X ³⁹ + p [39] X ³⁸ +... + P [1] B (X) = P (X) mod (X ⁸ + X ² + X + 1) (14) = _{^{b 8 X 7 + b 7 X}} 6 + b 6 X 5 + b 5 X 4 + b 4 X 3 + b 3 X 2 + b 2 X + b 1 p [i] (i = 1~40) = 0 or ₁ b 1 (i = 1~ 8) = 0 or 1 Next, when a new bit (p [0]) is input, the circuit calculates the remainder C (X) for the 41-bit input.

C (X) = (XP (X) + p [0]) mod (X ⁸ + X ² + X + 1) (15) = c ₈ X ⁷ + c ₇ X ⁶ + c ₆ X ⁵ + c ₅ X ⁴ + c ₄ X ³ + c ₃ X ² + c ₂ X + c ₁ c ₁ (i = 1 to 8) = 0 or 1 Remainder D (X) and C (X) for the latest 40-bit input
Is as follows.

C (X) = (p [40] X ⁴⁰ + p [39] X ³⁹ +... + P [1] X + p [0]) mod (X ⁸ + X ² + X + 1) = (p [39] X ^{39 + ···· + p [1]} X + p [0]) mod (X 8 + X 2 + X + 1) (+) p [40] X 40 mod (X 8 + X 2 + X + 1) = D (X) (+) p [ ^{40] X 40 mod (X 8} + X 2 + X + 1) (16) = D (X) (+) (X 6 + X 5 + X) p [40] ∴D (X) = C (X) (+) (X 6 + X ⁵ + X) p [40] Therefore, in order to always set the remainder for the latest 40-bit input to the value of the eight D flip-flops 20, in addition to the ordinary division circuit as shown in FIG. The exclusive OR of the input data bits according to equation (16) may be performed. In this manner, since the test can be performed for each bit, if the signal 304 is input with correct data without error, the signal 316 becomes H at least once with input of about one cell.

Once the signal 316 goes high, the state changes from the HUNT state to the PRESYNC state. At this time, the head of the cell is temporarily determined. Thereafter, 40 bits considered to be a cell header are input for each cell, and the remainder may be confirmed by eight D flip-flops. Therefore, in the PRESYNC state, the switches 43 and 4
4 is turned off, and the D flip-flop is reset before the arrival of 40 bits, which is considered to be the next cell header. Then, when the next cell header arrives at 304, only the switch 44 is turned ON while 40 bits are input, and the same division is performed on the data. If the operation returns to the HUNT state thereafter, the operation returns to the operation in the HUNT state again.

Even when the state changes from the PRESYNC state to the SYNCH state, the basic cell synchronization operation is performed by the PRESYNC state.
It is not different from the time of C state. However, in the SYNCH state, error control is performed, and the number of operations for the error control increases. That is, in the error correction mode in the SYNC state, the remainder of the division of the input 40 bits by turning on the switch 44 is (L, H, L, H, L, H, L,
H), the control circuit 38 determines that the signal 316 does not go to H, and the control signal therefrom gives
At the same time that the switch 44 is turned off,
Turn ON only for the bit clock. This gives 1,3
The fifth and seventh D flip-flops 20 are inverted with respect to the input of the normal operation, respectively, and input to the second, fourth, sixth and eighth D flip-flops 20. At the next timing, the switch 45 is turned off and the switch 46 is turned on at the same time.
Becomes In this state, the division circuit for the 40-bit clock is operated, and the signal 306 is output. This signal is a header error correction pattern. If the i-th output bit of the signal 306 is H, it means that the i-th bit of the header is incorrect. If all the 40-bit clocks are L signals, this means that there is an error but it cannot be corrected. This signal 306 is used at the output of the control circuit 38 and the shift register circuit (C) 31. In the error detection mode, since the determination can be made only by the signal 316, the above-described complicated operation is not performed, and the PRESYNC is not performed.
It behaves exactly like the state.

Here, the principle that the signal 306 becomes a header error correction pattern will be described. As described above, the error-free cell header starts from the fifth byte (L, H, L,
40 bits obtained by subtracting the pattern of (H, L, H, L, H) on GF (2) is a shortened cyclic code in which G (X) is a generator polynomial. Is divisible by G (X). This code can perform one-bit error correction and two-bit error detection when performing error correction, and can detect errors of up to three bits when only error detection is performed.

Now, assuming that there is an error in the i-th one bit of the cell header, (L, H, L, H, L, H,
L, H) after removing the pattern, the following T
(X).

T (X) = X ^39-1 modG (X) (17) When this is shifted i + 1 times by the division circuit, X ^{i + 1} · X ^39-1 mod G (X) = X ⁴⁰ mod (X ⁸ + X ^{2 + X + 1) = X} 6 + X 5 + X (18) , and becomes the same value. In other words, if the value of the D flip-flop becomes (L, H, H, L, L, L, H, L) when it is shifted i + 1 times, it is known that there is an i-th error. The signal 306 utilizes this, and in this example, it is shifted i + 1 times, but the number of shifts may be an appropriate value equal to or more than i times.

The shift register circuit (C) 31 has a length of 40 bits or more, and outputs a signal 305 obtained by simply delaying the signal 304 by the bit clock. If the error correction signal 306 is shifted i + m times when it is created, a 40 + m bit length is required due to the delay of the output of the correction signal. In this example, since it is shifted i + 1 times,
It is 41 bits long. Only when the header error can be corrected in the error correction mode, at most one bit of the value of H is output from the signal 306. At this time, the signal 305 becomes the signal 306
Is exclusive-ORed, and becomes a signal 307 as a signal having a correct cell header. In other states, the signal 305 becomes the signal 307 as it is.

The signal 307 is directly used as the selector (B) 35
, And also enters the shift register circuit (D) 32. This shift register circuit is 43 bits long and has 4 bits.
Eight enable terminals are provided to receive control from the control circuit. In the HUNT state, the signal 307 enters the shift register circuit (D) 32 in order, but in the PRESYNC state and the SYNCH state, the operation of the shift register circuit is stopped while the cell header data flows in the signal 307.
In this way, the latest 43-bit payload is always stored in the shift register circuit (D) 32.

The signal 308 output from the shift register circuit (D) 32 is exclusive-ORed with the signal 307 to obtain the signal 30
As 9, the selector (B) 35 is reached. That is, the signal 309 corresponds to the descrambled data of the payload portion of the cell represented by the polynomial F (X). This descrambling is paired with the scrambling (P) on the transmitting side, and is referred to as descrambling (p) to distinguish it from others. In the selector (B) 35, H
In the UNT state, the signal 307 is always selected. In other states, the signal 307 is selected for the header portion, and the signal 309 is selected for the payload portion, and is output as the signal 311. The signal 311, in the SYNCH state, is basically in the original cell shape except for the cell having an error.

The cell counter 36 outputs H
A signal indicating whether the state is the UNT state or any other state is always received. In the HUNT state, when the signal 316 from the cell synchronization / header error control circuit 33 becomes H, the counter is reset. Thereafter, in the PRESYNC state and the SYNCH state, since the head of the cell is known, the count for exactly one cell length is repeated regardless of the external signal. Therefore PRESY
In the NC state and the SYNCH state, the output value from the counter indicates which part of the current cell is being input or output. Then, the control circuit 38 which has received the output signal of the counter value outputs a necessary control signal as appropriate based on these values.

This counter always operates even during HUNT. Since this circuit is designed without using an external reset signal, this counter is used as a timer for outputting an internal reset signal for recovery from an abnormal condition.
For example, in the HUNT state, if cell synchronization is difficult to achieve even though signal synchronization for one cell would normally be possible in a HUNT state, the cell synchronization / header error control circuit should be used after several turns of the cell counter. There is a usage such as resetting 33.

The status display circuit 40 is HUNT, PRESY
The error correction mode and the error detection mode in the NC and SYNCH states and the SYNCH state are externally displayed. Therefore, the signal 314 is composed of a plurality of signal lines. Further, this circuit always informs the control circuit 38 of the current state and mode, and according to this information, the control circuit 38 sends a control signal to each circuit.

In the HUNT state, information that the signal 316 from the cell synchronization / header error control circuit 33 has become H is received from the control circuit 38, and the state display circuit 40 outputs
Display the YNC status display. The control circuit 38 that has received this information operates the DELTA counter 41. DEL
When the output of the cell counter 36 has a certain value, the TA counter 41 increases its own counter value by one when the signal 316 is H, and resets it when it is L. The control circuit 38 passes the information of this counter to the status display circuit 40. When the DELTA counter 41 is reset, the status display circuit 40
When the NT state is displayed and it is found that the value matches the number of times given from the outside, the state is changed from the PRESYNC state to S.
The display is changed to the YNCH state and sent to the control circuit 38. As a result, the control circuit 38 resets the DELTA counter 41 and operates the ALPHA counter 42 this time. A
When the output of the cell counter 36 has a certain value, the LPHA counter 42 increases its own counter value by one when the signal 316 is L, and resets it when it is H. The control circuit 38 passes the information to the status display circuit 40, and the status display circuit 40 sets the error correction mode when the value of the ALPHA counter 42 is 0, and displays the error detection mode otherwise. Further, when it is determined that the value of the counter matches the number of times given from the outside, the display is changed from the SYNCH state to the HUNT state and sent to the control circuit 38.

The cell clock generation circuit 39 has a SYNCH
In the state, the cell clock signal 312 and the cell valid display signal 313 at a timing having some relationship with the head of the cell.
Put out. The cell clock signal 312 is a signal simply indicating a cell division in a state where synchronization is established. In addition, the cell valid display signal 313 displays, for example, L for a cell which is known to have a header error and cannot be corrected.
In this way, this cell can be deleted by the next stage circuit.

In this figure, the configuration excluding the enable terminal 48 is an embodiment in which a cell header is included as descrambling data of the payload descrambling (p) described in the section of the prior art. In this case, the header and the scrambled (P) data are inserted into the shift register circuit (D) 32, and either the data 309 descrambled (p) or the data 307 as it is by using the header is selected by the selector ( B) Selected by 35. The selection method is the same as that described above.

In the above, only the case of serial input has been described with reference to FIG. 9. However, in the case of using an external frame conforming to the CCITT standard, phase information for each byte can be obtained. The same circuit configuration can cope with the case where 8-bit parallel input is performed.

FIG. 12 shows 31, 32, 3 of FIG.
Embodiments corresponding to connection portions 3 and 35 are shown. Since the basic data flow is the same as that in FIG. 9, only a brief description will be given here. As described above, the MSB is located at the top of the drawing and the LSB is located at the bottom of the drawing, and the head of the cell is always located at the MSB.

The input signal 501 branches into the 8-bit parallel shift register circuit (A) 52 and the cell synchronization / header error control circuit 51, and enters the shift register circuit (A) 52.
Then, data is output as a signal 502 after shifting by 5 byte clocks. The signal 502 is used as an input to the circuit 51 and a header error correction pattern signal 503 from the circuit 51.
An exclusive OR is obtained, and one of the signals 505 becomes an input to the selector 50 and the other becomes an input to the 8-bit parallel shift register circuit (B) 53. However, the switch 55 is turned off at the part regarded as the cell header.
So that it is not entered. Then, a signal 504 obtained by performing an exclusive OR operation on the output data from the circuit 53 and the 3-bit parallel D flip-flop circuit 54 and the signal 505 reaches the selector 50. The selector 50 selects the signal 505 if the signal is in the HUNT state or the cell header portion in any other state, and otherwise the signal 5 is selected.
04 is selected as the output signal 506.

FIG. 13 shows the configuration of the cell synchronization / header error control circuit 51 of FIG. The basic operation flow is the same as that of FIG. The signal 502 is a signal obtained by delaying the signal 501 by 5 byte clocks. This is input to the erasure pattern generation circuit 59 so that the remainder for the latest 5 bytes can be calculated every byte at the time of the HUNT state.
Generate an erasure pattern of a signal input in the past. HU
The switch 60 is turned ON only in the NT state, and this pattern is exclusive ORed with each bit of the signal 501.

Reference numeral 57 denotes a division pattern generation circuit, which outputs G from data obtained by shifting the output signal from the 8-bit parallel D flip-flop 56 by 8 bits.
The remainder of the 8-bit pattern divided by (X) is generated. This signal is further exclusive-ORed with the exclusive OR of the signal 501 and the signal 502, and input to the 8-bit parallel D flip-flop 56. When the value of the D flip-flop 56 is viewed from the MSB side, (L, H,
(L, H, L, H, L, H) signal 507
Becomes H. This signal 507 is the signal 31 in FIG.
6 is supported.

When it is found that there is an error in the header in the error correction mode, the switch 61 is turned ON for the output signal 56 for only one byte clock, and the second, fourth, sixth and eighth bits are inverted. After that, one enters the division pattern generation circuit, and generates a pattern shifted in order by 8 bits. At this time, the switch 62 is turned off, and the signal 501 is not input. The other side enters a correction pattern generation circuit 58 and outputs a correction pattern to a signal 50.
Output as 3.

The operation of the erasure pattern generation circuit 59 is as follows. When the input signal is f [j] and the output signal is fo [j] (j is an integer from 1 to 8), and binary representation of 0 and 1 is given, respectively.
It is represented by the following equation. However, it is assumed that f [8] and fo [8] are MSBs.

Fo [8] = f [2] (+) f [3] (+) f [7] (+) f [8] fo [7] = f [1] (+) f [2] ( +) F [6] (+) f [7] fo [6] = f [1] (+) f [5] (+) f [6] fo [5] = f [4] (+) f [ 5] (+) f [8] fo [4] = f [3] (+) f [4] (+) f [7] (19) fo [3] = f [2] (+) f [3 ] (+) F [6] (+) f [8] fo [2] = f [1] (+) f [3] (+) f [5] (+) f [8] fo [1] = f [3] (+) f [4] (+) f [8] Next, the operation of the division pattern generation circuit 57 is as follows.
[J], and the output signal is go [j] (j is an integer from [1] to 8), and is represented by the following formula, when it is expressed in binary of 0 and 1, respectively. However, it is assumed that g [8] and go [8] are each MSB. “(+)” Indicates exclusive OR for each bit.

Go [8] = g [6] (+) g [7] (+) g [8] go [7] = g [5] (+) g [6] (+) g [7] go [6] = g [4] (+) g [5] (+) g [6] go [5] = g [3] (+) g [4] (+) g [5] (20) go [ 4] = g [2] (+) g [3] (+) g [4] (+) g [8] go [3] = g [1] (+) g [2] (+) g [3 ] (+) G [7] go [2] = g [1] (+) g [2] (+) g [7] go [1] = g [1] (+) g [7] (+) g [8] Finally, the operation of the correction pattern generation circuit 58 is based on the input signal h.
[J], the inverted signal of the input signal is hb [j], and the output signal is ho [j] (j is an integer from 1 to 8). Is done. However, h [8], hb [8] and ho [8] are MS
Suppose B. "." Represents AND logic.

Ho [8] = (h [4] · h [6] · h [7]) · (hb [1] · hb [2] · hb [3] · hb [5] · hb [8] ) Ho [7] = (h [3] · h [5] · h [6]) · (hb [1] · hb [2] · hb [4] · hb [7] · hb [8]) ho [6] = (h [2] · h [4] · h [5] · h [8]) · (hb [1] · hb [3] · hb [6] · hb [7]) ho [5 ] = (H [1] · h [3] · h [4] · h [7] · h [8]) · (hb [2] · hb [5] · hb [6]) (21) ho [ 4] = (h [2] · h [3] · h [6] · h [7]) · (hb [1] · hb [4] · hb [5] · hb [8]) ho [3] = (H [1] · h [2] · h [5] · h [6]) · (hb [3] · hb [4] · hb [7] · hb [8]) h o [2] = (h [1] · h [5] · h [6] · h [7]) · (hb [2] · hb [3] · hb [4] · hb [8]) ho [ 1] = (h [5] · h [7] · h [8]) · (hb [1] · hb [2] · hb [3] · hb [4] · hb [6])

[0112]

As described above, on the transmitting side, when generating redundant bits for the whole or a part of the cell, the output of the multiplication of the original data by a certain polynomial is directly applied to the polynomial of the corresponding division circuit. By using the remainder divided by, it is possible to generate a redundant bit immediately after the original data is input, and by immediately adding this to the packet, the circuit can be used in the circuit from the input of the data signal to the output of the data signal. Can be minimized. This also eliminates the need for a delay circuit required when there is a delay, thereby reducing the circuit scale.

On the receiving side, a data storage function of a cell header portion necessary for simultaneously realizing descrambling applied to a payload portion of a cell and cell synchronization, and an input to an inspection circuit for cell synchronization. When updating data at least every 1 bit in the case of serial input, and at least every 1 byte in the case of 8 bit parallel input, store 1 bit or more data or 1 byte or more data to be removed from the check circuit. The function and the redundancy bits are used to check the whole or a part of the cell for errors. If an error is found, the error correction data is stored until the error correction pattern is generated. With the use of a shift register circuit having the function of storing data simultaneously, the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram of an overall configuration of a cell generation circuit according to an embodiment of the present invention.

FIG. 2 is a diagram of a scrambling operation in a payload portion of a cell.

FIG. 3 is another configuration diagram of a scrambling operation in a payload portion of a cell.

FIG. 4 is a diagram of a scrambling circuit for the entire cell.

FIG. 5 is another configuration diagram of a scramble circuit of the whole cell.

FIG. 6 is a diagram of a conventional HEC generation circuit.

FIG. 7 is a diagram of an HEC generation circuit according to an embodiment of the present invention.

8 is a circuit diagram of the same function as that of the circuit of FIG. 7 and 8-bit parallel input / output.

FIG. 9 is a diagram of an overall configuration of a cell synchronous operation circuit according to an embodiment of the present invention.

FIG. 10 is a diagram of a cell synchronization / header error control circuit.

FIG. 11 is a diagram of a conventional ordinary division circuit.

FIG. 12 shows a case where the circuit of FIG.
FIG. 3 is a diagram showing a flow of data.

FIG. 13 is a diagram of a cell synchronization / header error control circuit in the case of parallel input / output.

[Explanation of symbols]

 12 HEC generation circuit 14 cell scramble circuit 15 shift register circuit (A) 16 shift register circuit (B) 18 cell header 19 cell payload 25 8-bit shift register 30 cell descramble circuit 31 shift register circuit (C) 32 shift register circuit (D) 33 Cell Synchronization / Header Error Control Circuit 51 Cell Synchronization / Header Error Control Circuit 52 Parallel Shift Register Circuit (A) 53 Parallel Shift Register Circuit (B) 57 Division Pattern Generation Circuit 58 Correction Pattern Generation Circuit 59 Erase Pattern Generation Circuit 101 Cell Clock 102 Cell length data signal 110 Payload scramble output signal 111 Cell scramble output signal 301 Received data 302 Bit clock 306 Error correction pattern signal 310 Clock monitor Data signal 311 cell data output 312 cell clock 313 cell valid display signal 314 status display signal 315 5 byte delay signal 502 5 byte delay signal 503 error correction pattern signal 506 cell data output

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 7/08 H04L 12/28

Claims (1)

(57) [Claims] 1. A receiving circuit system of an ATM system for communicating information in the form of a packet of a fixed length called a cell by utilizing the property of redundant bits added in a device of a transmitting circuit system. A cell synchronization operation circuit that synchronizes by examining a part of a cell and finding a corresponding redundant bit , wherein at least the cell
When updating the data input to the inspection circuit for
A function to store the data to be removed from the inspection circuit and a partial data of the cell to be inspected for cell synchronization
The function of placing, in performing the error correction of the entire or part of the data of the cell with the redundant bits, the correction target data correction pattern
Function to store the data to be corrected until the application is generated
And a shift register circuit having the following.