JPH04322530A - Bit interleaved parity arithmetic circuit - Google Patents

Abstract

PURPOSE:To reduce number of signal lines, to simplify the circuit constitution and to save number of pins in the case of large scale circuit integration, in the case of digital transmission. CONSTITUTION:A B1 (B3) calculation circuit 10 applies parity arithmetic operation to an 8-bit input signal. A P/S conversion circuit 11 converts the result of 8-bit calculation into a serial signal and a 1-bit parity arithmetic circuit 12 applies parity arithmetic operation to a serial signal whose low-order level is transferred one by one bit. The result of arithmetic operation is transferred one by one bit each and an S/P conversion circuit 13 is used to restore the signal into an 8-bit signal and the result is fetched in a register 14.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit interleaved parity calculation circuit for serially transferring parity signals.

0002

[Background Art] In recent years, CCIT related to digital transmission has been developed.
In the T standard recommendation, the Synchronous Digital Hierarchy (hereinafter S
DH) has been proposed. In SDH, STM-0
(51.840Mbps), STM-1 (155.52Mbps)
0Mbps), STM-4 (622.080Mbps)
has been made into a recommendation, and at an even higher level, STM-16 (2
488.320Mbps) is scheduled (for example,
CCITT Recommendation 1988 G. 707,G. 708
,G. 709, TTC standard 1989 edition JT-G70
7, JT-G708, JT-G709).

[0003] In the overhead part of the STM frame structure, BIP (bit int
(erleaved parity), B1,B
2 and B3 bytes are prepared. The B1 byte is for monitoring bit errors in the relay section, and is calculated for all bits of the scrambled STM-N for the previous frame, and placed in the scrambled B1 byte. The B3 byte is for bit error monitoring of the path, and is calculated through all bits of the STM-N virtual container and placed in the B3 byte. However, the B3 byte is
Applies only to connected operations. At that time, B1, B
A 3-byte STM interlevel transfer circuit is required.

FIG. 3 shows an example of a conventional bit interleaved parity calculation circuit, and FIG. 4 shows the configuration when STM-N is connected.

In FIG. 3, 1 is a B1 (B3) calculation circuit, 2 is an 8-bit parity calculation circuit, 3 is a register, 4 is an AND gate, and 5 is a bit interleaved parity calculation circuit.

In FIG. 4, 6 is the lowest level #N, 7
is #(N-1), 8 is top level #1, 9 is STM-
It has an N-connected configuration.

As shown in this figure, this circuit performs a parity operation on an 8-bit input signal using a B1 (B3) calculation circuit 1, and further performs an 8-bit parity operation in 8-bit parallel with the signal transferred from a lower level. circuit 2
Performs parity calculation. Then, at the same time as the calculation result is taken into the register 3, it is transferred to the upper level in 8-bit parallel. Therefore, only the highest level (#1) register receives the BIP value through all bits of STM-N. However, only in the case of B3 byte, AND
Since a concatenation signal (in concatenation operation = 1) is input to one input of gate 4, only its own operation result is taken into register 3 in decoupling operation.

[0008]

[Problems to be Solved by the Invention] However, in the above configuration, data transfer between STM frames is performed in 8-bit parallel mode, but B1 and B3 data is transferred once per frame (125 μsec). Since only data transfer is performed, the efficiency of pin usage is extremely poor and the number of pins increases, which poses a problem in realizing LSI implementation. Furthermore, when realizing a transmission device that has a large number of signal lines and is compliant with the SDH frame, the circuit configuration between each level becomes complicated.

An object of the present invention is to solve the above problems and reduce the number of pins of an IC.

0010

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a calculation circuit that performs a parity calculation on an m-bit input signal, and a P/S that converts the calculation result of the calculation circuit into a serial signal. A conversion circuit, an arithmetic circuit that performs parity calculations on the lower level serial signal bit by bit,
The configuration includes an S/P conversion circuit that converts into an M-bit signal based on the calculation result of the calculation circuit.

[0011]

[Operation] With the above-described configuration, the present invention can perform P/S conversion on the B1 and B3 bytes, which are originally transferred in 8-bit parallel mode, perform parity calculation on each bit, and serially transfer each bit on a bit-by-bit basis.

0012

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a bit interleaved parity calculation circuit showing an embodiment of the present invention, and FIG.
This shows the configuration when M-N is connected.

In FIG. 1, 10 is a B1 (B3) calculation circuit, 11 is a P/S conversion circuit, 12 is a 1-bit parity calculation circuit, 13 is an S/P conversion circuit, 14 is a register, 15
is an AND gate, and 16 is a bit interleaved parity calculation circuit.

In FIG. 2, 17 is the lowest level #N;
18 is #(N-1), 19 is the highest level #1, and 20 is the STM-N concatenation configuration.

The bit interleaved parity calculation circuit configured as described above is shown in FIGS. 1 and 2 below.
The operation will be explained using .

This circuit has B for an 8-bit input signal.
1 (B3) Parity calculation is performed by the calculation circuit 10, and 8
The bit operation result is converted into a serial signal by the P/S conversion circuit 11, and then the serial signal transferred from the lower level and the 1-bit parity calculation circuit 12 are used to convert the bit operation result into a serial signal.
Performs parity operation bit by bit. The operation result is transferred bit by bit, and at the same time, it is converted back to 8 bits by the S/P conversion circuit 13 and taken into the register 14. However, only in the case of the B3 byte, since a concatenation signal (=1 during concatenation operation) is input to one input of AND gate 15, only its own operation result is taken into register 14 during non-concatenation operation.

Note that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

Furthermore, although it is assumed that the data is transferred in one bit, the number of bits is not particularly limited to this.

[0020]

[Effects of the Invention] As described above, according to the present invention, B1,
By P/S converting the B3 data, it is possible to implement a configuration in which parity calculation is performed bit by bit and transferred bit by bit, thereby achieving a reduction in the number of pins.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a bit interleaved parity calculation circuit showing an embodiment of the present invention.

[Figure 2] STM-N connection configuration diagram in Figure 1

[Figure 3] Schematic configuration diagram of a conventional bit interleaved parity calculation circuit

[Figure 4] STM-N connection configuration diagram in Figure 3

[Explanation of symbols]

1 B1 (B3) calculation circuit 2 8-bit parity calculation circuit 3 Register 4 AND gate 5 Bit interleaved parity calculation circuit 6
Lowest level #N 7 #(N-1) 8 Highest level #1 9 STM-N connection configuration 10 B1 (B3) calculation circuit 11 P/S conversion circuit 12 1-bit parity calculation circuit 13 S/P conversion circuit 14 Register 15 AND gate 16 Bit interleaved parity calculation circuit 17
Bottom level #N 18 #(N-1) 19 Top level #1 20 STM-N connection configuration

Claims (2)

[Claims] 1. A bit interleaved parity arithmetic circuit comprising a P/S conversion circuit and an S/P conversion circuit and serially transferring a parity signal between a plurality of levels. 2. A calculation circuit that performs a parity calculation on an m-bit input signal, a P/S conversion circuit that converts the calculation result of the calculation circuit into a serial signal, and a parity calculation performed on a lower level serial signal bit by bit. A bit interleaved parity arithmetic circuit comprising an arithmetic circuit and an S/P conversion circuit that converts into an m-bit signal based on the arithmetic result of the arithmetic circuit.