JPH0454532A - Parity calculation circuit - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity of a calculation circuit, to miniaturize a device structure, and to simplify the constitution of a clock signal generating circuit by inputting the same clock to each delay circuit. CONSTITUTION:The signals (RESET signals) applied to the clock terminals of delay circuits 11 - 13 are inputted and all circuits 11 - 13 are reset. Then the 8-bit input transmission signals D(7) - D(0) are applied to each input of each exclusive OR circuit (EXOR) of an arithmetic circuit 14 via an input line D. The exclusive OR is secured between the data D(7) - D(0) applied to each input of each EXOR and the output signals D3(7) - D3(0) received from the circuit 13. Thus the parity calculation is carried out. The calculation result data D0(7) - D0(0) are given to the circuit 11 of the first stage, and the calculation results are outputted from the circuit 11 as the data D1(7) - D1(0). Then only the subject data of the parity calculation is extracted out of the circuit 11. Thus the circuit constitution is miniaturized and the constitution of a clock generating circuit is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parity calculation circuit that detects signal errors that occur during communication of transmission signals.

[Conventional technology]

SDR (Synchronous Digital Hierarchy) is one of the means to realize broadband l5DN (High Value-Added Digital Network).
rrchy), a standardized signal sequence is used. This signal sequence is called STM-N. N is an integer, and the standard value is 1, 4.16, etc., and the transmission speed varies depending on the value of N, and is 155.52M.
It is expressed as bpsXN.

Conventionally, in a signal transmission system using such a signal sequence, a parity calculation circuit having the configuration shown in FIG. 4 has been used. This circuit uses device circuits 1, 2.3 consisting of eight D-type flip-flops. The timings of the clock signals B21CLK, B22CLK, and B23CLK input to each of these delay circuits 1.2.3 are shown in FIGS. 5(c), (d), and (e). In addition, (a) in the same figure shows the timing of a transmission signal in which 8 bits constitute one byte, (b) shows a reset signal manually inputted to each delay circuit 1 to 3, and (f) shows the timing of a transmission signal input to each latch circuit 4 to 6. Indicates the input latch clock signal.

The transmission signal sent out serially in 8-bit units is input to an arithmetic circuit 7.8.9 consisting of 8 exclusive OR circuits (EXOR), and parity is calculated. Of this calculation result, the data to be inspected is B21CLK.
, B22CLK, and B23CLK by each delay circuit 1.2.3 in synchronization with the clock timing. Parity calculation is performed every 3 bytes, and when the calculation for one frame of data is completed, a latch clock signal is generated, the calculation results are latched in each latch circuit 4 to 6, and written to 82 bytes of the next frame. It will be done. Then, each delay circuit is reset by a reset signal RESET,
The above parity calculation is performed over and over again.

[Problem to be solved by the invention]

However, in the conventional parity calculation circuit described above, the exclusive OR operation for 3 bytes is performed separately in each of the calculation circuits 7 to 9. For this reason, the amount of hardware, especially the amount of hardware for the exclusive OR calculation portion, has increased, and the circuit configuration has become larger. Also,
The type of B2 clock input to each delay circuit 1 to 3 is B
21CLK, B22CLK, and B23CLK, and the timing clock generation circuit has become complicated due to the large number of types. Furthermore, in the explanation of the prior art described above, the case where the signal sequence is STM-1 was explained, but the STM-
As N becomes larger and the transmission speed becomes higher, the circuit configuration becomes larger and larger, and the structure of the clock generation circuit becomes increasingly complex.

[Means to solve the problem]

The present invention has been made to solve this problem, and consists of three stages of delay circuits in which eight D-type flip-flops are connected in parallel, and each reset terminal of these delay circuits and each clock The input terminals are commonly connected to each terminal, and eight EXORs are configured in parallel, and one input terminal of each of these EXORs is connected to each output terminal of the third stage delay circuit, and each other's input terminal is connected to each output terminal of the third stage delay circuit. The terminal is connected to each input line of a signal transmitted in 8-bit parallel, each output terminal is connected to each input terminal of the first stage delay circuit, and eight latch circuits are connected in parallel, one for each stage delay circuit. Each input terminal of each of these latch circuits is connected to each output terminal of each stage of the delay circuit, and each latch clock input terminal is connected in common.

[Effect]

By inputting the same clock to each delay circuit,
The 8-bit parallel transmission signal is delayed by 3 bytes. The delayed transmission signal is subjected to an exclusive OR operation with a new transmission signal that is subsequently transmitted using only 8 EXOHs, and parity calculation is performed every 3 bytes.

〔Example〕

Next, a parity calculation circuit in a synchronous digital hierarchy according to an embodiment of the present invention will be described.

The signal sequence in this embodiment is STM-1, and the frame structure of this signal sequence is shown in FIG.

One frame consists of 270 bytes and 9 lines. The frame range of 9 bytes and 3 lines in the upper left of the figure contains management information and frame synchronization information.

Data to be subjected to bit error detection is contained within the frame range indicated by the bold line in the figure, and 82 bytes are provided in which parity calculation results, which are bit error detection results, are written. Parity calculation is performed every 24 bits (3 bytes), and the resulting data is 3 bytes in total. 82 bytes corresponds to B21. B22
．． It consists of 3 bytes of B23 bytes. Further, the transmission signal is serially transmitted in parallel with 8 bits from the left to the right of the illustrated frame and from the top to the bottom. Its transmission speed is 155.52Mbps (
-270 bytes x 9 lines x 8 bits x 8 KHz).

The following explanation will be made for the case where the signal sequence is STM-1, but this is for convenience of explanation, and other STM
It is possible to apply the present invention to all -N signals.

FIG. 1 is a block diagram showing the configuration of a parity calculation circuit according to this embodiment.

Three stages of delay circuits 11, 12, and 13 each having eight D-type flip-flops configured in parallel are connected in series.

In other words, each of the eight data output lines of the delay circuit 11 is connected to each of the eight data input lines of the delay circuit 12.
Each of the eight data output lines of No. 2 is connected to each of the eight data input lines of the delay circuit 13. These delay circuits 11-1
The reset terminals and the clock input terminals of No. 3 are commonly connected to each other.

In addition, eight EXORs are configured in parallel to form the arithmetic circuit 14.
is formed. One input terminal of each of these EXOH is connected to each data output terminal of the third stage delay circuit 13,
Each other input terminal is connected to each input line of a signal transmitted in 8-bit parallel. Further, each a terminal of EXOH is connected to each data input terminal of the first stage delay circuit 11.

In addition, a holding circuit 1 in which eight latch circuits are configured in parallel.
5, 16, and 17 are provided for each delay circuit 11, 12, and 13 of each stage. Each input terminal of each of these holding circuits 15, 16, and 17 is connected to each data output terminal of delay circuits 11, 12, and 13, and the latch clock input terminals of each of holding circuits 15 to 17 are connected in common.

A timing chart of signals in each part of the parity calculation circuit configured as described above is shown in FIG. Same figure (
, a) is the timing of a transmission signal in which 8 bits input to the input signal line constitute 1 byte. timing 1
The period is 125μSee, and one byte of information is transmitted in one period.

(b) of the figure shows the timing of the reset (RESET) signal applied to the reset input terminal of each delay circuit 11 to 13, and E (C) shows the timing of the clock signal (B2CLK) applied to the clock terminal of each delay circuit 11 to 13. ) Signal timing, the figure (d) shows the latch clock of each holding circuit 15 to 17.
Latch clock (LCLK) given to the input terminal
Shows signal timing.

Next, the operation of this circuit will be explained.

First, a RESET signal is input to each of the delay circuits 11 to 13, and all the circuits are reset and sorted. The 8-bit input transmission signals D(7) to D(0) are applied to each EXOH of the arithmetic circuit 14 via the input line p. Note that signals D(7) to (0) are the 8-bit parallel expansion of the STM-1 signal, and data D(7) is the most significant bit (MS
B), data D(0) is the least significant bit (LSB). Input data D given to each EXOR member (
7) to D(0) are output signals D3(
7) to D3(0) and exclusive OR is performed to perform parity calculation.

This calculation result data DO(7) to D0(0) is given to the first-stage delay circuit 11, and at the timing when the first B2 clock power (input) is input, the calculation result is transferred from the delay circuit 11 to data D1(7) to D0(0). This 82 clock is output as Di(0). Since this 82 clock is generated only when the data within the thick line frame in FIG. 2 is input, only the data subject to parity calculation is extracted from the delay circuit 11. .

When the next B2 clock is input, the data Di(7) to D1(0) output from the delay circuit 11 are transferred to the delay circuit 1.
2 and output as data D2(7) to D2(0). Furthermore, when the next B2 clock is input, data D2 (7) to
D2(0) is taken into the delay circuit 13 and data DB(
7) to D3(0). Furthermore, when each B2 clock is input, in parallel with the above processing, the output signals D B(7) to D3(0) of the third stage delay circuit 13 and the input signal D(7) from the input signal line are ) to D(0) are both executed. As a result, parity calculation is executed every 3 bytes for the data within the bold line frame shown in FIG.

When the parity calculation for one frame of data is completed, the LCLK signal is input to each holding circuit 15 to 17, and the data output from each delay circuit 11 to 13 at the time of input is input to each holding circuit 15 to 17. 17. A total of 24 bits of latched data is the result of parity calculation, and this result is written into 82 bytes of the next frame. Thereafter, the RESET signal is input to each delay circuit 11-13, and each delay circuit 11-13 is reset to its initial state. The above processing is repeatedly executed for each frame.

This parity calculation is first performed on the data sending side. Then, parity calculation is performed again on the transmitted signal on the receiving side, and a match is made with the calculation result at the time of transmission stored in the B2 byte of the next frame.

If they match, it is assumed that no bit error has occurred in the data, and if they do not match, it is assumed that a bit error has occurred during transmission.

According to this embodiment, since the exclusive OR calculation section is constituted by only eight EXOHs, the amount of hardware in the circuit is reduced, the circuit configuration is miniaturized, and circuit control is facilitated. Further, since only one type of B2 clock is provided to each delay circuit 11 to 13, the circuit configuration of the clock signal generation section is simplified. Further, even if N of the STM-N increases and the signal transmission speed increases, the circuit configuration does not become large and the configuration of the clock generation circuit does not become complicated.

〔Effect of the invention〕

As described above, according to the present invention, the same clock is input to each delay circuit, so that the 8-bit parallel transmission signal is delayed by 3 bytes. The delayed transmission signal is subjected to an exclusive OR operation with a new transmission signal that is subsequently transmitted using only 8 EXORs, and parity calculation is performed every 3 bytes.

Therefore, the amount of node hardware in the calculation circuit is reduced, and the device becomes smaller. Furthermore, the configuration of the clock signal generation circuit is simplified. Therefore, a parity calculation circuit is provided which is convenient for circuit integration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a parity calculation circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the frame structure of an STM-1 signal, and FIG. 3 is an embodiment of the present invention shown in FIG. 1. A diagram showing a timing chart of signals in the calculation circuit of
FIG. 4 is a block diagram showing the configuration of a conventional parity calculation circuit, and FIG. 5 is a block diagram showing the configuration of a conventional parity calculation circuit. FIG. 6 is a diagram showing a timing chart of signals in the conventional calculation circuit shown in FIG. 11.12.13...Delay circuit configured with 8 D-type flip-flops in parallel, 14...Arithmetic circuit configured with 8 exclusive OR circuits (EXOR) in parallel, 15, 16.17...A holding circuit configured with eight latch circuits in parallel.

Claims (1)

[Claims] Three stages of delay circuits in which eight D-type flip-flops are configured in parallel are connected in series, and each reset terminal and each clock input terminal of these delay circuits are connected in common. , eight exclusive OR circuits are configured in parallel, one input terminal of each of these exclusive OR circuits is connected to each output terminal of the third stage delay circuit, and each other input terminal is connected to an 8-bit It is connected to each input line of signals transmitted in parallel, each output terminal is connected to each input terminal of the first stage delay circuit, and eight latch circuits are arranged in parallel for each stage of delay circuit. A parity calculation circuit characterized in that each input terminal of each of these latch circuits is connected to each output terminal of each stage of the delay circuit, and each latch clock input terminal is connected in common.