KR940007872B1 - Circuit for calculating crc of atm cell head - Google Patents

Abstract

The cyclic redundancy code (CRC) calculating circuit includes first and second 8-bit flip flops for retiming input and output data, an exclusive OR circuit for generating a next 8-bit register value for CRC calculation, an 8-bit register for latching data for CRC generation, a select circuit for inserting a CRC into a transfer data stream, and a delay circuit for supplying a control signal to the select circuit, thereby providing useful CRC calculation for high-speed data.

Description

Byte-based CRC calculation circuit for ATM cell head

1 is a circuit diagram of a conventional circuit.

2 is a block diagram of the present invention.

3 is an exclusive OR circuit diagram of the present invention.

4 is a circuit diagram of an 8-bit register, selection circuit, and delay circuit of the present invention.

5 is a timing diagram showing the relationship between main signals of the present invention.

* Explanation of symbols for main parts of the drawings

1, 5: 8-bit flip-flop 2: Exclusive OR circuit

3: 8-bit register 4: selection circuit

6: delay circuit

The present invention relates to a circuit for calculating a cyclic redundancy code (CRC) on a byte basis for an ATM (Asynchrous Transfer Mode) cell head.

The ATM cell head consists of 5 octets and the last octet is used as the CRC for 1 bit head error control and cell delineation for the head. The generator polynomial g (X) used here is x ⁸ + x ² + x + 1.

CRC calculations were performed mainly in bits, but due to the ease of processing in bytes and the speed of calculation in CRC calculations by software, byte calculations using table look-up algorithms were introduced in Perez in 1983. Proposed by. In recent years, high speed data transmission is inevitable due to the explosive increase in data volume. At this time, the CRC calculation circuit based on the conventional shift register for data integrity has difficulty in selecting and designing parts due to high speed data processing. .

An object of the present invention is to provide a byte-by-byte CRC calculation circuit having an eight times speed reduction effect to alleviate the above problem.

Exemplary OR operation table for calculating the result of the shift by the bit shifted by bit CRC calculation from the conventional CRC calculation circuit as shown in Table 1 to calculate the result in byte unit to achieve the above object Obtain In this case, the exclusive OR tap number is a CRC generation polynomial for the ATM cell head. In Table 1, SH represents shift number, IN represents input data, and R1 to R8 represent each register value. In addition, C1-C8 represent the initial value of a register. In Table 1, the four stages of the exclusive OR function, that is, the last stage of the final shift, are called communtative (A B = B A), associativity (A B C = A C B), involutlon (A A = 0), identity (A Simplified using 0 = A) is shown in Table 2. To find the exclusive OR calculation table from Table 2 X ₁ = C ₁ Using the relation of M ₁ can be re-expressed as shown in Table 3.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram showing the configuration of the present invention, where 1 and 5 are 8-bit flip-flops, 2 is an exclusive OR circuit, 3 is an 8-bit register, 4 is a selection circuit, and 6 is a delay circuit. The input data Din8 to Din1 are retimed by an 8-bit flip flop (1). The 8-bit flip-flop 1 is composed of a 74LS374 IC chip in this embodiment, and the waveform of the output data M ₁ (1 < i < 8) is the same as M ₁ in FIG. The exclusive OR circuit 2 inputs the substantially transmitted data M ₁ received from the 8-bit flip-flop ₁ and the state value C ₁ of the current 8-bit register 3 to the next stage 8-bit register 3. Creates a status value of. The exclusive OR circuit 2 is implemented by individual exclusive OR gates as in the third diagram by the relations in Table 3. The 8-bit register 3 temporarily stores the CRC and the CRC output from the exclusive OR circuit 2, and fits the status value to the exclusive OR circuit 2 at every byte shift to generate the CRC. Let it back. The selection circuit 4 inputs the data to be transmitted from the 8-bit flip-flop 1 and the CRC from the 8-bit register 3 to insert the CRC onto the data stream to be transmitted. The delay circuit 6 transmits a control signal to the selection circuit 4 by delaying the MR (Master Reset) by the corresponding position in order to load the CRC on the data stream to be transmitted. The final data to be transmitted from the selection circuit 4 is retimed by the 8-bit flip-flop 5 and output.

4 is a detailed circuit diagram of the 8-bit register 3, the selection circuit 4, and the delay circuit 6 in FIG. 2. In this embodiment, the 8-bit register 3 is 74LS273 (7) and the selection circuit 4 in this embodiment. The 74LS157 (9) 10 and the delay circuit 6 are implemented as 74LS374 (8), respectively. The 74LS273 (7) is reset in the "low" state of the ATM cell cycle clock MR of FIG. 5, and the output C ₁ is in the "0" state to initialize the CRC generation 74LS273 (7) to "0". After the input data M ₁ is shifted four times, 74LS273 (7) has the CRC value of the ATM cell head. Output waveform data C ₁ is equal to ₁ ° C third. The 74LS374 (8) receives MR as an input and feeds it back as many times as required by the clock CP to generate waveform Q of FIG. 5 and input it to the selection terminal of 74LS157 (9) (10). The 74LS157 (9) (10) outputs the data received from the 8-bit flip-flop (1) and 74LS273 (7) of FIG. In the state, the data M ₁ to be transmitted is selected, and in the "low" state, the CRC C ₁ is selected.

TABLE 1a

TABLE 1b

TABLE 2

TABLE 3

Therefore, the present invention configured and operated as described above has an effect of reducing the bit-by-bit CRC calculation speed by the conventional shift register by 8 times, and thus will be very useful when calculating CRC for high-speed data.

Claims (2)

An 8-bit flip-flop (1) (5) for retiming input and output data, an exclusive OR circuit connected to the 8-bit flip-flop (1) to generate the next 8-bit register value for cyclic redundancy code (CRC) calculations. (2) an 8-bit register (3) connected to the exclusive OR circuit (2) for latching data for CRC generation at every shifting, and connected to the 8-bit flip-flop (1) and 8-bit register (3). An ATM cell head comprising a selection circuit 4 for inserting a CRC on a transmission data stream and a delay circuit 6 for receiving a master reset (MR) and providing a control signal Q to the selection circuit 4. CRC calculation circuit for bytes. The delay circuit (6) according to claim 1, wherein the 8-bit flip-flop (1) (5) is 74LS374, the 8-bit register (3) is 74LS273, and the selection circuit (4) is two 74LS157. Denotes 74LS374, wherein the exclusive OR circuit (2) consists of a connection of individual exclusive ORs.