JP2830791B2 - Pointer processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pointer processing circuit, and more particularly to an AU (Administrator) in an ATM communication system.
rative Unit) -4-Xc (X is a natural number) The present invention relates to a pointer processing circuit for receiving a pointer.

[0002]

2. Description of the Related Art ATM (Asynchronous Transfer Mode)
SDH (Synchronous Digital Hi
erarchy) signal contains an AU pointer, which is the SO pointer in the SDH frame.
H (Section Over Head) is a combination of the pointer and the payload.
4Xc is specified in the ITU-T recommendation.

In this AU4-Xc pointer, 1
There are 3X pieces of data corresponding to 6-bit (2 bytes) H1H2 data, and H1H2 #
, H1H2 # 2, ..., H1H2 # (3X-1),
It will be referred to as H1H2 # 3X.

In this case, the data required to determine whether or not the pointer value has been changed and whether or not the stuff has been executed are H1H2 # 1, and (3X-1) H1H2 # n data are required.
(N = 2-3X), AIS (Alarm Indicati)
on Signal) status or CI (Concatenation)
It is necessary to determine two types of information (bit patterns), that is, information indicating “Indication”.

For this purpose, a conventional pointer processing circuit of this type has a configuration as shown in FIG. That is, 6
X 8-bit latch F / F (flip-flop)
The circuit is composed of 1.1 to 1.6X and (3X-1) AIS / CI determination circuits 11.1 to 11.3 (3X-1).

F / Fs 1.1 to 1 for these 8-bit latches
6X is H1 # m of the received input data synchronized with the clock
According to the timing (m = 1 to 3X) and the respective timings of the H2 # m data, H1 # m data and H2 # m data (1 byte) are latched and output from the input data.

F / Fs 1.1 and 1.2 for 8-bit latch
The H1 # 1 and H2 # 1 data, which are 8-bit outputs, become H1H2 # 1 data (2 bytes). It will be derived to the pointer determination unit.

[0008] Both data of H1 # 2 and H2 # 2 are latched by 8-bit latching F / Fs 1.3, 1.4 and A, respectively.
Both are input to the IS and CI determination circuits 11 and 1. The AIS of the H1H2 # 2 data is
The CI is determined, and the determination results are derived to the reception pointer determination unit.

Hereinafter, H1 # 3 and H2 # 3 to H1 # 3X
The same applies to each data of H2 # 3X and H2 # 3X.
Each determination result of 1H2 # 3X is derived.

In each of the AIS and CI determination circuits,
The bit pattern of the corresponding H1H2 # n (n = 2 to 3X) data is detected.
The two-byte bit pattern of H1H2 # n is all "1", and in the CI state, "1001 ** 11"
11111111 ", the bit pattern in the AIS state and the bit pattern in the CI state are respectively detected. The circuit configuration can be easily realized by a combination of gate circuits.

FIG. 5 shows AU-4-1c (X =
1) A diagram showing a pointer reception processing circuit, and an operation timing chart thereof is shown in FIG.

[0012]

In such a conventional pointer processing circuit, since the H1 # m data and the H2 # m data are all latched, the 8-bit latch F / F is 6X. And 3 × 1 AIS / CI determination circuits are required, which causes a problem that the overall circuit scale becomes large.

The present invention has been made in order to solve the problems of the prior art, and an object of the present invention is to provide an AU-4-Xc pointer reception processing circuit capable of greatly reducing the circuit size. To provide.

[0014]

According to the present invention, an ATM is provided.
AU (Administrative Unit) in a communication system
4-Xc (X is a natural number) a pointer processing circuit for receiving a pointer, the first and second latches respectively latching a predetermined first byte and a predetermined second byte in received input data Means, all "1" determining means for determining whether one byte of the input data is all "1", and pattern determining means for determining whether one byte of the input data is a predetermined bit pattern A plurality of determination result latching means for respectively latching the determination results of the all "1" determination means and the pattern determination means at a plurality of predetermined timings; and a plurality of these determination result latching means A 2-byte bit pattern is provided using the all- "1" determination result of the corresponding-determination-result latch means and the current determination result of the all- "1" determination means. IS (Alarm Indication Signal
AIS determining means for determining whether or not the pattern indicates information; and bit pattern determination results of the corresponding determination result latching means provided corresponding to the plurality of determination result latching means and the current all "1" determining means. Using the determination result and the 2-byte bit pattern, the CI (Concatenatio
(n Indication) CI determination means for determining whether the bit pattern indicates information.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention is as follows.
Only the H1H2 # 1 data necessary for determining whether or not the pointer value has been changed and whether or not the stuff has been executed are latched by the latching F / F.
Information necessary for the determination of IS and CI is latched in accordance with the timing of H1 # n, AIS and CI are determined using the latch information and current input data, and the determination result is latched in accordance with the timing of H2 # n. Is what you do.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as those in FIGS. 8
The bit latch F / Fs 1.1 and 1.2 receive H1 # 1 data and H1 # 1 of the input data in accordance with the respective timings of H1 # 1 and H2 # 1 of the received input data synchronized with the clock.
Each of the 2 # 1 data (1 byte) is latched.

The two latching F / Fs 1.1 and 1 · 1
The two latch outputs 2 are derived as 16-bit H1H2 # 1 data to a reception pointer determination unit (not shown), and are used to determine whether the pointer value has changed or whether stuff has been executed.

The all "1" determination circuit 3 determines whether the input data is 1 or not.
The H1 byte CI determination circuit 4 determines whether the 8 bits corresponding to one byte of the input data are a predetermined bit pattern, that is, "1001 **". 11 "(* is undefined).

(3X-1) F / Fs for 2-bit latch
2.1-2. (3X-1) are all "1" determination circuits 3
, And the H1 byte CI determination circuit 4 latches the paired results in accordance with the respective timings of H1 # 2, H1 # 3,..., H1 # 3X.

AIS determination circuits 5-1 to 5 (3X-1)
Are provided corresponding to the two-bit latch F / Fs 2.1２2 （(3X−1), respectively.
It is determined whether or not the 2-byte bit pattern is an all- "1" pattern indicating AIS information using the all- "1" determination result of / F and the all- "1" determination result of the current input data.

The CI determination circuits 6-1 to 6- (3X-1) are also provided corresponding to the 2-bit latch F / Fs 2.1 to 2- (3X-1), respectively. F /
The bit pattern determination result of F and the bit pattern of the current input data indicate CI information “1001 ** 11111”.
11111 "is determined.

Further, F / Fs 7-1 to 7 for 2-bit latch
(3X-1) is provided corresponding to the AIS determination circuit 5.1 and the CI determination circuits 6-1 to 5. (3X-1) and 6. (3X-1), respectively, and the corresponding AIS determination circuit And C
H2 # 2 to H2 # 3 using the two determination results of the I determination circuit as a pair
It latches at each timing of X.

These two-bit latching F / Fs 7
The two-bit outputs of 1 to 7 (3X-1) are derived to the reception pointer determination unit as AIS determination result # 2 and CI determination results # 2 to # 3 and # 3X, respectively.

FIG. 2 shows AU-4-1c (X =
1) A diagram showing a pointer reception processing circuit, and an operation timing chart thereof is shown in FIG.

Two 8-bit latching F / Fs 1.1,1
2 is H1 # 1 data and H2 # from the input data 101
1 data and 16-bit H1H2 # 1
The data is output to the reception pointer determination unit as data 113.

The all "1" determination circuit 3 determines whether the input data 10
It is determined whether 1 is all “1” and output as a determination result 121. The H1 byte CI determination circuit determines whether the input data 101 is “1001 ** 11” and outputs the result as a determination result 122.

The 2-bit latching F / F2.1 immediately after the all "1" determination circuit 3 determines whether the H1 # 2 data is all "1" or "1001 ** 11". The result is latched and a 2-bit decision result 123,
Output as 124. Similarly, F / F for 2-bit latch
2 · 2 latches the determination result for the H1 # 3 data and outputs it as 2-bit determination results 125 and 126.

The AIS determination circuit 5.1 assumes that the output 121 of the all "1" determination circuit 3 is the determination result for the H2 # 2 data, and adds the information of the output 123 to the 16-bit H.
Determine whether 1H2 # 2 data is AIS and output 12
7 is assumed. Similarly, the determination circuits 5.2 are 16-bit H1
Determine whether H2 # 3 data is AIS and output 129
And

The CI determination circuit 6-1 assumes that the output 121 of the all "1" determination circuit 3 is the determination result for the H2 # 2 data, and adds the information of the output 124 to the 16-bit H1.
It is determined whether or not the H2 # 2 data is CI and output 128. Similarly, the judgment circuits 6.2 are 16-bit H1H2
It is determined whether the # 3 data is CI and output 130 is obtained.

The two F / Fs for 2-bit latch at the last stage
The F / F 7-1 of the F2 latches the information of the outputs 127 and 128 at the timing when the input data 101 is H2 # 2, and thereby the AIS for the H1H2 # 2 data is latched.
, And CI are latched as outputs 131 and 132. Similarly, the F / F 7.2 latches the AIS and CI determination results for the H1H2 # 3 data and outputs
3,134.

All "1" determination circuit 3 and H1 byte C
Each of the 2-bit latching F / Fs 2, 1, 2 that latches both determination results of the I determination circuit 4 latches the determination result at the timing when the current input data is the H1 byte. Therefore, two determination results of whether the H1 byte data are all “1” or “1001 ** 11” are latched and output.

Each of the AIS determination circuits 5, 1, 5 and 2
It is assumed that the result of determining whether the H1 byte data is all "1" and the result of determining whether the current input data is all "1" are input, and that the current input data is H2 byte data. And the result of the determination as to whether the 16-bit data is all "1" is output.

Similarly, each of the CI determination circuits 6 1 and 6 2 determines whether the H1 byte data is “1001 ** 11” and the current input data is all “1”. Is input, the current input data is treated as H2 byte data, and the result of determining whether the 16-bit data is "1001 ** 1111111111" is output.

The final stage 2-bit latching F / F 7-1,
Each of 7.2 and 2 latches the respective determination results of the AIS determination circuits 5, 1, 5.2 and CI determination circuits 6, 1, 6.2 at the timing of H2 bytes from the input data. Therefore, the H1 and H2 byte data are all “1” (AI
S) and whether or not “1001 ** 11
The result of determination as to whether or not the data is 11111111 "(CI) is latched and output.

Comparing FIG. 4 which is a block diagram of the prior art with FIG. 1 which is a block diagram of the present invention, the number of 8-bit latch F / Fs (6X-2) is two-bit latch F / Fs.
It can be seen that (6X-2) pieces have been replaced, and the circuit scale of this part is reduced to about one-fourth. In addition, since various judgment circuits can be configured by simple gate circuits, when simply comparing with input signals, 16 (3X-
1) The input is replaced by {4 (3X-1) +14}, and it can be seen that the circuit scale of this portion is also reduced to 1/4.

The input signal necessary to configure the H1 byte CI determination circuit is only 6 bits excluding 2 bits which are undefined among the 8 bit data.

[0038]

According to the present invention, H1H2 # n (n = 2
3X) Since an 8-bit latch F / F for data is not required, there is an effect that the overall circuit scale is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment when applied to an AU-4-1c pointer processing circuit.

FIG. 3 is a timing chart showing the operation of the block in FIG. 2;

FIG. 4 is a block diagram of a conventional pointer processing circuit.

FIG. 5 is a block diagram of a conventional example of an AU-4-1c pointer processing circuit.

FIG. 6 is a time chart showing the operation of the block shown in FIG. 5;

[Explanation of symbols]

 1.1, 1 and 2 F / F for 8-bit latch 2.1 and 2- (3X-1) F / F for 2-bit latch 3 All "1" determination circuit 4 H1 byte CI determination circuit 5.1 and 5 -(3X-1) AIS determination circuit 6.1-6-(3X-1) CI determination circuit 7.1-7-(3X-1) F / F for 2-bit latch

Continuation of the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H04J 3/00-3/26 H04L 12/28

Claims (3)

(57) [Claims] 1. An AU (Admi) in an ATM communication system.
nistrative Unit) -4-Xc (X is a natural number) A pointer processing circuit for receiving a pointer, wherein a predetermined specific first byte and second predetermined byte in the received input data are
First and second latch means for respectively latching bytes; all "1" determining means for determining whether one byte of the input data is all "1"; one byte of the input data is predetermined Pattern judgment means for judging whether or not the bit pattern is determined, and a plurality of judgment results each latched at a plurality of predetermined timings, each pair of the judgment results of the all "1" judgment means and the pattern judgment means. Latch means; and a plurality of judgment result latch means provided corresponding to the plurality of judgment result latch means, respectively, using an all "1" judgment result of the corresponding judgment result latch means and a current judgment result of the all "1" judgment means.
The bit pattern of the byte is AIS (Alarm Indication S)
ignal) AIS to determine whether the pattern is informational
Determining means, provided in correspondence with each of the plurality of determination result latch means, using a bit pattern determination result of the corresponding determination result latch means and a current determination result of the all "1" determination means;
Byte bit pattern is CI (Concatenation Indica)
Option) C to determine whether the bit pattern indicates information
A pointer processing circuit, comprising: I determination means. 2. The apparatus according to claim 1, wherein each of the determination result latch means comprises a two-bit latch circuit that latches the determination results of the all “1” determination means and the pattern determination means as one bit. Item 2. The pointer processing circuit according to Item 1. 3. The predetermined bit pattern is “1001 *
* 11 "(* is undefined).
Or the pointer processing circuit according to 2.