JP2639178B2 - M-bit receiving circuit for ISDN subscriber line - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an integrated service digital network (ISDN) user / network interface structure based on CCITT recommendation I series, and a multi-frame composed of a primary group interface. The present invention relates to an m-bit receiving circuit of an ISDN subscriber line that receives information from a data link using m bits out of F bits.

[Conventional technology]

The frame structure of the ISDN user / network interface having a primary group B channel interface and a "23B + D" structure (speed 1.544 Mbit / s) is based on Recommendation G.704 with 24 multiframes. That is, each frame is 193 bits, and is composed of one F bit followed by 24 consecutive time slots (numbers 1 to 24 are assigned).

Of the F bits of 24 multiframes, frame numbers 4,
The F bits for every four bits of 8, 12, 16, 20, 24 form the multi-frame synchronization signal 001011. Frame numbers 1, 3, 5, ...
M bits are assigned to the F bits 21 and 23 for every two bits, and are used for maintenance operation information and the like.

The data link layer procedure of the second layer of the ISDN user / network interface is based on the HDLC procedure used in CCITT recommendation X.25, and the frame format uses the address part of the HDLC frame format extended by 2 octets. . Therefore, the flag 01111110 is added as a start flag and an end flag before and after the frame. (For example, Electronic Information Communication Handbook, edited by the Institute of Electronics, Information and Communication Engineers, 1988 edition,
Therefore, an m-bit receiving circuit that receives a digital code on a data link and extracts m bits detects and receives data according to the HDLC frame format.

[Problems to be solved by the invention]

The above-mentioned conventional m-bit receiving circuit of the ISDN subscriber line is:
Since it is configured to take in data from the data link by means of HDLC frame detection and reception, it cannot be applied to data transmission with a frame configuration other than HDLC frame, for example, reception of information using 16-bit configuration frame There was a problem that can not be.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an ISDN subscriber line m-bit receiving circuit which has a 16-bit frame detection unit together with an HDLC frame detection unit, and solves the above problem.

[Means for solving the problem]

The basic configuration of the m-bit receiving circuit of the ISDN subscriber line according to the present invention is an integrated service digital network (ISDN) user-network interface structure based on CCITT recommendation I series.
In an m-bit receiving circuit of an ISDN subscriber line for receiving information from a data link using m bits out of F bits in a multiframe constituted by a subgroup interface,
High-level data link control procedure (HD) to extract m bits transmitted on the data link and use it in CCITT Recommendation X.25
LC) The frame detection circuit accumulates the m bits only when detecting the m bits formed into the frame with the predetermined bit configuration to be discarded, and the microprocessor that processes the received data sets the m bits according to the predetermined bit configuration. Means for processing the accumulated m bits with a predetermined bit configuration when the storage notification is received.

One embodiment for the basic configuration is an integrated services digital network (ISD) based on CCITT recommendation I series.
N) ISDN that receives information from the data link using m bits out of F bits in the multiframe composed of the primary interface in the user / network interface structure
In the m-bit receiving circuit of the subscriber line, CCITT Recommendation X.25
An HDLC frame receiving circuit for extracting an HDLC frame from the data link according to a high-level data link control procedure (HDLC) and storing the HDLC frame, and converting serial data on the data link to parallel data and outputting the parallel data A parallel conversion circuit, an HDLC frame detection circuit that outputs m bits from parallel data output from the serial-parallel conversion circuit and outputs an HDLC detection bit when detecting an HDLC frame configuration, and extracts m bits from the parallel data When detecting a predetermined 16-bit configuration frame, a 16-bit configuration frame detection circuit that outputs a 16-bit configuration detection bit,
A register for connecting the parallel data and the 16-bit configuration detection bit to the input and storing the parallel data to be input when the 16-bit configuration detection bit is received, and connecting the HDLC frame receiving circuit and the register to the HDLC detection bit by connecting to the data bus. A microprocessor that processes the m-bit string stored in the HDLC frame receiving circuit as an HDLC frame when received, and processes the m-bit string stored in the register as a 16-bit frame when receiving a 16-bit detection bit; And

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing one embodiment of the present invention. As shown in FIG. 1, the data link 1 is connected to an HDLC frame receiving circuit 2, and the HDLC frame receiving circuit 2 is connected to a microprocessor 4 via a data bus 3. The data link 1 is connected to a serial-parallel conversion circuit 5, and the output of the serial-parallel conversion circuit 5 is connected to an HDLC frame detection circuit 6, a 16-bit frame detection circuit 7, and a register 8.

As for the digital code on the data link 1, in the example of the interface of 1544 Kbit / s, one frame of 125 μs is composed of time slots 1 to 24 every 8 bits and 193 bits of F bits. That is, the frame period is 1544M / 193
= 8K frames / s. As described above, m bits are transmitted every two frames and transmitted on the data link 1 at a speed of 4 Kbit / s.

The HDLC frame receiving circuit 2 transmits 4Kbit /
The m bits of s are received and the flag “0111111” of the HDLC frame is received.
When "0" is detected, the data of the HDLC frame is received and stored.

The serial-parallel conversion circuit 5 receives m serial bits of 4 Kbit / s from the data link 1, converts the serial m bits into parallel data, and outputs the data as parallel data. When detecting the HDLC frame flag 01111110 from the parallel data, the HDLC frame detection circuit 6
The detection bit is output to the microprocessor 4 to urge the microprocessor 4 to call the HDLC frame receiving circuit 2 via the data bus 3.

The 16-bit configuration frame detection circuit 7 is provided in the present invention, and outputs a 16-bit configuration detection bit to the microprocessor 4 when a predetermined 16-bit configuration frame is detected from the parallel data. Prompts the call of register 8 via 3; The 16-bit configuration frame is 16 bits of code 0XXXXXX011111111 and is 1 bit.
The octet consists of a binary code of one.

When the register 8 receives the 16-bit configuration detection bit, the register 8 stores the parallel data being received.

When receiving the HDLC detection bit, the microprocessor 4 takes out the necessary stored data from the HDLC frame receiving circuit 2 via the data bus 3 and processes it. When the microprocessor 4 receives the 16-bit configuration detection bit, it retrieves necessary stored data from the register 8 via the data bus 3 and processes it.

Even if the HDLC frame receiving circuit 2 and the HDLC frame detecting circuit 6 receive the 16-bit code 0XXXXXX011111111, the received code is discarded because the binary code 1 does not continue eight times in the HDLC frame.

That is, an m-bit receiving circuit capable of handling both the HDLC frame and the 16-bit frame was able to be experimented.

〔The invention's effect〕

As described above, according to the present invention, m bits out of the F bits in the multiframe composed of the primary group interface in the ISDN user / network interface structure are taken out from the data link, and discarded in the HDLC frame detection circuit. By adding a configuration in which the detected m-bit sequence is stored and processed by the microprocessor only when an m-bit sequence configured in a frame with a predetermined bit configuration is detected,
There is an effect that another bit configuration frame can be processed in addition to the LC frame.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of an m-bit receiving circuit for an ISDN subscriber line according to the present invention. 1 ... data link, 2 ... HDLC frame receiving circuit, 3
... Data bus, 4 microprocessor, 5 serial conversion circuit, 6 HDLC frame detection circuit, 7 16
Bit configuration frame detection circuit, 8 ... register.

Claims (1)

(57) [Claims] 1. An integrated service digital network (ISDN) based on the CCITT recommendation I series, on a data link using m bits out of F bits in a multi-frame constituted by a primary group interface in a user network interface structure. Frame receiving circuit for extracting an HDLC frame by the high-level data link control procedure (HDLC) used in CCITT Recommendation X.25 from the data link and storing it in an m-bit receiving circuit of an ISDN subscriber line receiving information from When,
A serial-parallel conversion circuit that receives the serial data on the data link, converts the data into parallel data, and outputs the data; and extracts m bits from the parallel data output from the serial-parallel conversion circuit,
An HDLC frame detection circuit that outputs an HDLC detection bit when an LC frame configuration is detected, and a 16-bit configuration frame that outputs a 16-bit configuration detection bit when m bits are extracted from the parallel data and a predetermined 16-bit configuration frame is detected A detection circuit, a register for storing the parallel data input when the parallel data and the 16-bit configuration detection bit are connected to the input and receiving the 16-bit configuration detection bit,
When the HDLC frame receiving circuit is connected to the register and the data bus and receives an HDLC detection bit, the m-bit string stored in the HDLC frame receiving circuit is processed as an HDLC frame, while when a 16-bit configuration detection bit is received, A m-bit receiving circuit for an ISDN subscriber line, comprising: a microprocessor for processing the m-bit string stored in the register as a 16-bit frame.