JP2001196539A - Scan flip flop and semiconductor integrated device having scan flip flop inside - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scan flip flop, which enables a test device to be designed without user's consideration of the state of reset signal/set signal, in a scan shift operation mode in a test of a semiconductor integrated device. SOLUTION: The device has a selection circuit 1, where first data and second data are input parallel and one of first and second data is selected and output in accordance with a selection signal, a flip-flop circuit 2 where data output from the selection circuit 1 is held synchronized with a clock signal and output, and the output state is reset/set, in response to reset signal/set signal and a gate circuit 3 which checks application of reset signal/set signal to the flip/clop circuit 2 when a selection signal is in a prescribed state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan flip-flop used for testing a semiconductor integrated device such as an IC and an LSI, and further easily inspects a combination circuit by incorporating the combination circuit and the scan flip-flop. The present invention relates to a semiconductor integrated device that can be used.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated device such as an IC or LSI, in a test mode, input data applied to a combinational circuit in the semiconductor integrated device and output data read out from the combinational circuit are serially transferred. In some cases, scan cells are used. Note that in the present application, a combinational circuit is a circuit that does not include a sequential circuit that operates in synchronization with a clock signal, such as a flip-flop, and refers to a circuit formed by combining a plurality of gates.

[0003] By connecting a plurality of scan cells in series to form a full scan configuration, it is easy to apply an arbitrary signal to a combinational circuit in a semiconductor integrated device or to read out a signal output from the combinational circuit. Can be. In order to perform such an operation, each scan cell has a scan flip-flop.

The scan flip-flop is reset by a reset signal or set by a set signal. In addition, a scan shift operation mode is set by the scan enable signal. In the scan shift operation mode, serially input data is sequentially supplied to and held by a plurality of scan flip-flops in synchronization with a clock signal. The input data held in each scan flip-flop is applied to a combinational circuit for testing. Data output from the combinational circuit as a result of the test is sequentially read from each scan flip-flop in synchronization with a clock signal, and output as serial output data.

[0005]

However, in the conventional scan flip-flop, the reset signal /
Since the path of the set signal and the path of the scan enable signal are independent, there is a problem that the scan flip-flop is reset / set when the reset signal / set signal becomes active during the scan shift operation. For this reason, the user has to design the test apparatus in consideration of the state of these signals.
Further, when switching from the scan shift operation mode to the normal operation mode, a minute pulse may be generated in the negative logic reset signal / set signal due to a timing error between the reset signal / set signal and the scan enable signal in the test apparatus. The scan flip-flop may malfunction.

In view of the above, a first object of the present invention is to design a test apparatus without considering the state of a reset signal / set signal in a scan shift operation mode in a test of a semiconductor integrated device. Is to be able to do it. A second object of the present invention is to
An object of the present invention is to provide a scan flip-flop that does not malfunction when switching from the scan shift operation mode to the normal operation mode. Further, a third object of the present invention is that
An object of the present invention is to provide a semiconductor integrated device incorporating such a scan flip-flop.

[0007]

In order to solve the above-mentioned problems, a scan flip-flop according to the present invention is configured such that first data and second data are inputted in parallel, and the first and second data are inputted in accordance with a selection signal. A selection circuit for selecting and outputting one of the data, and holding and outputting the data output from the selection circuit in synchronization with a clock signal, and resetting the output state in response to a reset signal / set signal. A flip-flop circuit for setting; and a gate circuit for preventing a reset signal / set signal from being applied to the flip-flop circuit when the selection signal is in a predetermined state.

A semiconductor integrated device according to the present invention is a semiconductor integrated device having a combinational circuit and a plurality of scan flip-flops connected to the combinational circuit and connected in series with each other. At least one of the scan flip-flops is input in parallel with the first data supplied from the combinational circuit and the second data supplied from the preceding scan flip-flop, and the scan enable signal is not active. A selection circuit for selecting the first data and selecting and outputting the second data when the scan enable signal is active; a combination circuit for holding the data output from the selection circuit in synchronization with the clock signal; Output to the next stage scan flip-flop and output state in response to reset signal / set signal A flip-flop circuit for resetting / set, the scan enable signal; and a gate circuit for preventing the reset signal / set signal when the active is applied to the flip-flop circuit.

According to the above configuration, the reset signal / set signal is not carelessly applied to the flip-flop circuit in the scan shift operation mode. Therefore, the user can design the test apparatus without considering the state of the reset signal / set signal in the scan shift operation mode.

Here, the gate circuit includes an element for delaying a selection signal or a scan enable signal, and a logic circuit for performing a logical operation on a signal delayed by the element and a reset signal / set signal. You may. In this case, even when a small pulse is generated in the reset signal / set signal when switching from the scan shift operation mode to the normal operation mode, the scan flip-flop does not malfunction.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. The same components are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 1 shows a circuit configuration of a scan flip-flop according to a first embodiment of the present invention. This scan flip-flop has a selection circuit 1. The selection circuit 1 selects one of the input data IN1 and the input data IN2 input to the input X and the input Y in accordance with the selection signal SE, and outputs the selected data from the output Q. The data output from the selection circuit 1 is supplied to a data input D of a D flip-flop 2. The D flip-flop 2 holds the data in synchronization with the clock signal CLK input to the clock input C, and outputs the data from the output Q as output data OUT.

The D flip-flop 2 resets its output state in response to a reset signal RST input to a reset input R. In the present embodiment, as an example, the reset input R has negative logic. Selection signal S
When E is in a predetermined state (in this case, high level), the reset signal RST (in this case, active at low level)
Has an OR circuit 3 as a gate circuit in order to prevent the application to the flip-flop circuit 2.

A selection signal S is applied to two inputs of the OR circuit 3.
E and a reset signal RST are input, respectively, and an output of the OR circuit 3 is connected to a reset input R of the D flip-flop 2. When the selection signal SE is at a high level, the reset input R of the D flip-flop 2 is maintained at a high level even if the reset signal RST is at a low level. Therefore, when the selection signal SE is at the high level, the D flip-flop 2 does not enter the reset state.

Next, a scan flip-flop according to a second embodiment of the present invention will be described with reference to FIG. The second embodiment is different from the first embodiment in that the selection signal SE is supplied to the OR circuit 3 via buffer circuits 4 and 5 as delay elements.

This is because even if a small pulse of low level is generated in the reset signal RST at the moment when the selection signal SE changes from high level to low level, this small pulse is not applied to the reset input R of the flip-flop circuit 2. It is like that. That is, even if a low-level minute pulse is generated in the reset signal RST at one input of the OR circuit 3, the high-level selection signal SE delayed by the buffer circuits 4 and 5 is supplied to the other input of the OR circuit 3. Therefore, the output of the OR circuit 3 does not go low. Therefore, it is possible to prevent the flip-flop circuit 2 from being reset by mistake when the selection signal SE changes.

Next, a semiconductor integrated device according to an embodiment of the present invention will be described with reference to FIG.

In the semiconductor integrated device 10, the input terminal 2
A plurality of scan cells connected in series are inserted between 0 and the output terminal 40. FIG. 3 shows an N-th stage scan cell 31 and an (N + 1) -th stage scan cell 32 as examples. Further, these scan cells are connected to a combinational circuit 50. As a result, an arbitrary signal can be given from the input terminal 20 to the combinational circuit 50, and a signal output from the combinational circuit 50 can be read out at the output terminal 40. In order to perform such an operation, each scan cell must be configured as shown in FIG.
Alternatively, it includes a scan flip-flop 30 as shown in FIG. The scan flip-flop 30 is reset by a reset signal RST. The scan shift operation mode is set by the scan enable signal SE.

In the scan shift operation mode, data SI serially input from the input terminal 20 is sequentially supplied to and held by the plurality of scan flip-flops 30 in synchronization with the clock signal CLK. The input data held in each scan flip-flop 30 is applied to the combinational circuit 50 for testing. Data output from the combinational circuit 50 as a result of the test is sequentially read out as serial data SO from each scan flip-flop 30 in synchronization with the clock signal, and output from the output terminal 40.

Next, the operation in the case where the scan cells 31 and 32 include a scan flip-flop as shown in FIG. 1 will be described. As shown in FIG. 3, the scan flip-flop inputs data supplied from the combinational circuit 50 as input data IN1 and inputs data supplied from the preceding scan flip-flop to input data IN2.
Enter as

The selection circuit 1 included in the scan flip-flop of FIG. 1 selects the input data IN1 when the scan enable signal SE is not active, and selects the input data I when the scan enable signal SE is active.
N2 is selected and output. The data output from the selection circuit 1 is supplied to a data input D of a D flip-flop 2. The D flip-flop 2 holds this data in synchronization with the clock signal CLK input to the clock input C, and outputs the data from the output Q to the output
And output to the next-stage scan flip-flop.

The D flip-flop 2 has a reset input R
Resets the output state in response to a reset signal RST input to. In the present embodiment, as an example, the reset input R has negative logic. In the scan shift operation mode, when the scan enable signal SE is active (in this case, active at a high level),
To prevent the reset signal RST (in this case, active at low level) from being applied to the flip-flop circuit 2, an OR circuit 3 is provided as a gate circuit.

A scan enable signal SE and a reset signal RST are input to two inputs of the OR circuit 3, respectively. An output of the OR circuit 3 is connected to a reset input R of the D flip-flop 2. When the scan enable signal SE is at a high level, the reset input R of the D flip-flop 2 is maintained at a high level even if the reset signal RST is at a low level. Therefore, when the scan enable signal SE is at the high level, the D flip-flop 2 does not enter the reset state.

When the scan cells 31 and 32 in FIG. 3 have the scan flip-flops as shown in FIG. 2, there are the following advantages. That is, when a low-level minute pulse is generated in the reset signal RST at the moment when the scan enable signal SE changes from the high level to the low level, the minute pulse is applied to the reset input R of the flip-flop circuit 2. There is a risk. Even in such a case, since the high-level scan enable signal delayed by the buffer circuits 4 and 5 is supplied to the other input of the OR circuit 3, the output of the OR circuit 3 does not go low. Therefore, it is possible to prevent the flip-flop circuit 2 from being reset by mistake at the time of mode switching.

In the above embodiment, the D flip-flop 2 outputs the reset signal R input to the reset input R.
Although the case where the output state is reset in response to ST has been described, instead of this or in conjunction with this, D
The flip-flop 2 may set the output state in response to a set signal input to the set input.
In this case, the circuit configuration for performing the adjustment between the set signal and the control signal (scan enable signal) SE is a circuit for performing the adjustment between the reset signal RST and the control signal (scan enable signal) SE. The configuration may be the same.

[0026]

As described above, according to the present invention, inadvertent application of the reset signal / set signal to the flip-flop circuit in the scan shift operation mode is prevented. Therefore, the user can design the test apparatus without considering the state of the reset signal / set signal in the scan shift operation mode. Also,
By providing the delay element for delaying the scan enable signal, the scan flip-flop does not malfunction when switching from the scan shift operation mode to the normal operation mode.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a circuit configuration of a scan flip-flop according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a circuit configuration of a scan flip-flop according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a semiconductor integrated device according to one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 selection circuit 2 D flip-flop 3 OR circuit 4, 5 buffer circuit 10 semiconductor integrated device 20 input terminal 30 scan flip-flop 31, 32 scan cell 40 output terminal 50 combination circuit

Claims (8)

[Claims] 1. A selection circuit to which first data and second data are input in parallel, and selects and outputs one of the first and second data according to a selection signal; A flip-flop circuit which holds and outputs data to be output in synchronization with a clock signal and resets an output state in response to a reset signal; and wherein the flip-flop circuit outputs the reset signal when the selection signal is in a predetermined state. And a gate circuit for preventing application to the circuit. 2. The device according to claim 1, wherein the gate circuit includes an element for delaying the selection signal, and a logic circuit for performing a logical operation on the selection signal delayed by the element and the reset signal. Scan flip-flop as described. 3. A selection circuit that receives first data and second data in parallel, selects one of the first and second data according to a selection signal, and outputs the selected data. A flip-flop circuit that holds and outputs data to be output in synchronization with a clock signal, and sets an output state in response to a set signal; and when the select signal is in a predetermined state, the set signal is the flip-flop. And a gate circuit for preventing application to the circuit. 4. The gate circuit includes an element for delaying the selection signal, and a logic circuit for performing a logical operation on the selection signal delayed by the element and the set signal. Scan flip-flop as described. 5. A semiconductor integrated device having a combinational circuit and a plurality of stages of scan flip-flops connected to the combinational circuit and connected in series with each other, wherein at least one of the plurality of stages of scan flip-flops is provided. One is that the first data supplied from the combinational circuit and the second data supplied from the preceding-stage scan flip-flop are inputted in parallel, and the first data is selected when the scan enable signal is not active. A selection circuit for selecting and outputting the second data when the scan enable signal is active; holding the data output from the selection circuit in synchronization with a clock signal; A flip-flop that outputs to a scan flip-flop and resets the output state in response to a reset signal The semiconductor integrated device comprising a drop circuit, said reset signal when the scan enable signal is active is anda gate circuit for preventing from being applied to the flip-flop circuit. 6. The gate circuit includes an element for delaying the scan enable signal, and a logic circuit for performing a logical operation on the scan enable signal delayed by the element and the reset signal. Item 6. A semiconductor integrated device according to item 5. 7. A semiconductor integrated device having a combinational circuit and a plurality of stages of scan flip-flops connected to the combinational circuit and connected in series with each other, wherein at least one of the plurality of stages of scan flip-flops is provided. One is that the first data supplied from the combinational circuit and the second data supplied from the preceding-stage scan flip-flop are inputted in parallel, and the first data is selected when the scan enable signal is not active. A selection circuit for selecting and outputting the second data when the scan enable signal is active; holding the data output from the selection circuit in synchronization with a clock signal; A flip-flop that outputs to a scan flip-flop and sets the output state in response to a set signal The semiconductor integrated device of the flop circuit, wherein the set signal when the scan enable signal is active is anda gate circuit for preventing from being applied to the flip-flop circuit. 8. The gate circuit includes an element that delays the scan enable signal, and a logic circuit that performs a logical operation on the scan enable signal delayed by the element and the set signal. Item 8. A semiconductor integrated device according to item 7.