JP2709219B2 - Memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage circuit incorporated in a MOS type semiconductor integrated circuit, and more particularly to a storage circuit having a structure suitable for testing a semiconductor integrated circuit using a so-called scan test method.

[0002]

2. Description of the Related Art In recent years, there has been a tendency that more and more functions are mounted in a semiconductor integrated circuit, and accordingly, the chip size has also tended to become larger and larger. How tests are performed is becoming very important. Here, as the chip size increases, the scale of the circuit incorporated therein increases in proportion to the square of the length d of one side of the chip. However, the size of the circuit for transmitting and receiving signals to and from an external circuit is increased. The number of input / output terminals (pads) can be increased only in proportion to the length d of one side of the chip. Therefore, the number of input / output terminals tends to become insufficient as more functions are mounted in a semiconductor integrated circuit. Therefore, the number of input / output terminals occupied for the test needs to be reduced as much as possible.

From such a viewpoint, a scan test method, which is one of the test methods for a semiconductor integrated circuit, is often used. 9 and 10 are diagrams for explaining the scan test method. FIG. 9 is a diagram conceptually showing a shift register circuit wired for testing in a semiconductor integrated circuit. FIG. 10 is a diagram showing the shift register circuit. FIG. 3 is a diagram illustrating only one flip-flop circuit included in the circuit. In FIG. 10 and other figures described later, for the sake of simplicity, for example, a signal to be input or output, such as a data input signal D input from the data input terminal D, and a terminal to input or output the signal are the same. Reference numerals are given.

As shown in FIG. 10, each flip-flop circuit 10 is connected to an output terminal of a multiplexer 12 at a D input terminal. Each flip-flop circuit 1
To 0, the data input signal D in the normal mode and the test signal SI in the test mode, which are input to the multiplexer 12, are switched by the test enable signal TE and input.

In the scan test method, each flip-flop circuit 10 in a semiconductor integrated circuit is configured as shown in FIG. 10, for example, and these flip-flop circuits 10 form a shift register as shown in FIG. Incorporating such test wiring into the semiconductor integrated circuit,
During the test, the serial signal Sc is supplied to the shift register circuit.
This is a method of inputting anIN and a clock signal CLK, observing the output signal ScanOUT of the final stage, and testing whether or not many internal flip-flop circuits 10 operate properly.

By using this scan test method, a test can be performed using only a small number of input / output terminals even if a large number of flip-flop circuits are incorporated in a semiconductor integrated circuit.

[0007]

However, each flip-flop circuit incorporated in a semiconductor integrated circuit for the scan test method is originally incorporated for a purpose other than a shift register circuit wired for testing. Therefore, they are often arranged at discrete positions on a semiconductor chip. In this case, the arrival time of the clock signal to each flip-flop circuit constituting the shift register circuit wired for the test varies due to a difference in a wiring path, a difference in a load capacity, and the like, so-called clock skew occurs. If the queue is not sufficiently considered, a malfunction may occur such that data that should shift to the next stage by one clock pulse shifts to the next stage, and a correct test cannot be performed.

However, as described above, each flip-flop circuit incorporated in a semiconductor integrated circuit is originally incorporated for a purpose different from that of a test shift register circuit, and satisfies the intended applications. There is a problem that it is very difficult to design with sufficient consideration for clock skew and the like so as to satisfy the above and to function correctly as a shift register circuit. In particular, as the speed of a semiconductor integrated circuit increases, as in recent years, the possibility of a malfunction occurring even with a slight clock skew increases, and it becomes a problem how to perform a highly reliable test using a scan test method.

In view of the above circumstances, it is a first object of the present invention to provide a storage circuit capable of performing a highly reliable test by a scan test method without paying particular attention to clock skew at the time of design. I do. A latch circuit is a main storage circuit other than a flip-flop circuit incorporated in a semiconductor integrated circuit.
The conventional scan test method tests a flip-flop circuit, but cannot test a latch circuit.

A second object of the present invention is to make it possible to test a latch circuit by a scan test method in consideration of this point.

[0011]

A first storage circuit of the storage circuit of the present invention relates to a flip-flop circuit, and has a first signal input terminal and a clock signal input terminal.
Input at a predetermined clock edge of the clock signal.
A flip-flop circuit inserted between the first signal input terminal and the input terminal of the flip-flop circuit.
The first switch circuit, the second signal input terminal, and the second signal input terminal, which are kept in a non-conductive state in a predetermined test mode;
And between the signal input terminal of the flip-flop circuit and the input terminal of the flip-flop circuit, in the test mode,
Before the timing of a given clock edge
Transitions to a non-conducting state and is longer than the predetermined clock edge
A second switch circuit that is controlled so as to transit to a conductive state later .

Further, a second storage circuit of the storage circuit of the present invention relates to a latch circuit, and includes a first signal input terminal, a latch circuit, the first signal input terminal, and the latch circuit. intervening, predetermined test between the input terminal of the
A first switch circuit is maintained in a non-conducting state in Tomodo, interposed the tape between the second signal input terminal, a second signal input terminal and the input terminal of said latch circuit
In the strike mode, the latch circuit is connected to the latch circuit.
While the signal is in the latched state, the
State is controlled to return to the non-conductive state again ,
A second switch circuit having a tri-state buffer on the output side.

Further, a third storage circuit of the present invention comprises: a first-stage latch circuit forming a flip-flop circuit; a second-stage latch circuit forming the flip-flop circuit;
Interposed either between at the input frames of the input terminals or al the subsequent stage of the latch circuit of the latch circuit of the preceding stage, the first switch circuit is maintained in a non-conducting state in a predetermined test mode And a test signal input terminal, and a test signal input terminal and an input terminal of the post-stage latch circuit interposed between the test signal input terminal and the post-stage latch circuit, and in the test mode, the post-stage latch circuit outputs a signal to the post-stage latch circuit. while in the latched condition it is latched, and is characterized in that a controlled belt-stated buffer back to the non-conducting state again transitions to the conductive state.

Each of the switch circuits and the tri-state buffers in the second and third storage circuits may output an input signal as it is, depending on the overall circuit configuration and the like. May be inverted and output.

[0015]

[Action] The first remembers circuit of the present invention, in place of the multiplexer circuit 12 shown in FIG. 10, the test mode smell
And the first and second switch circuits controlled as described above. In a normal operation mode, the first switch circuit is held in a conductive state, and the second switch circuit is held in a non-conductive state. Thus, a desired signal is input from the first signal input terminal. In the test mode, the first switch circuit is turned off, and the second switch circuit to which a test signal is input is turned on. The second switch circuit is constantly turned on. Instead, the clock signal is turned off prior to the rising or falling timing at which data is taken into the flip-flop circuit, or at or before the maximum time during which clock skew may occur. . Even in this case, for example, 10 msec. During this period, the data immediately before the switch circuit becomes non-conductive at the input side of the first-stage latch circuit constituting the flip-flop circuit is held by the parasitic capacitance of the MOS circuit. On the other hand, the time interval of the clock pulse, the clock skew, and the like are, for example, several nsec. ~ Several 10 nsec. In the test mode, the clock repetition frequency and the like can be quite limited, so that the above-described dynamic test method can be performed. In this way, irregular changes in data due to clock skew are prevented by the second switch circuit, whereby a large number of the first storage circuits are connected for testing to form a shift register, and malfunction due to clock skew is caused. A highly reliable test without problems can be achieved.

In the second storage circuit according to the present invention, the second switch circuit has a tri-state buffer on the output side, and the first switch circuit is in a conductive state in a normal operation mode. The tri-state buffer is kept in a non-conductive state, and a desired signal is input from the first signal input terminal. In the test mode,
The first switch circuit is turned off and the second switch circuit is turned on. However, the second switch circuit is not constantly turned on. Prior to the rise or fall timing when the signal shifts to a state in which the signal is transmitted as it is as the output signal of the latch circuit, the non-conductive state is set before the maximum time during which clock skew may occur .
By controlling the timing of the transition of the second switch circuit to conduction and non-conduction in this way, even if the second switch circuit transitions to the non-conduction state, for example, 10 msec. As a circuit operation for the equal test, the data immediately before the second switch circuit is turned off at the output side of the tristate buffer is held by the parasitic capacitance of the MOS circuit for a sufficiently long time. In the second storage circuit, the second
There is also a limit on the timing at which the switch circuit of the second embodiment shifts to the conductive state, and the second switch circuit operates at the falling or rising of the clock signal, the data being held in the latch circuit, which is opposite to the rising or falling. Is shifted to the conduction state later than the timing.

In this way, before the latch circuit shifts to a state where the input signal of the latch circuit is transmitted as it is as the output signal of the latch circuit, the latch circuit waits for the maximum clock skew, and By shifting the second switch circuit to the non-conductive state, malfunction due to clock skew is prevented. Further, since the data temporarily held on the output side of the transstate buffer is held in the latch circuit and the second switch circuit is again turned on, the dynamic circuit is formed by the tristate buffer and the latch circuit. Is configured. Therefore, the second storage circuit relating to the latch circuit is mixed with the first storage circuit according to the present invention relating to, for example, a flip-flop circuit, or a large number of the second storage circuits are connected to each other so as to provide a test shift register. And a highly reliable test without malfunction due to clock skew can be performed.

A third storage circuit according to the present invention is provided for inputting a test signal to a connection point between an output terminal of a preceding latch circuit and an input terminal of a subsequent latch circuit constituting a flip-flop circuit. A tri-state buffer is connected. In this case, the transition of the tri-state buffer between the conducting state and the non-conducting state is controlled at the same timing as that of the second storage circuit, thereby scanning the latch circuit at the subsequent stage of the third storage circuit. And a test without malfunction due to clock skew can be performed by incorporating it into a shift register circuit.

[0019]

Embodiments of the present invention will be described below. FIG. 1 is a circuit block diagram of one embodiment of the first storage circuit of the present invention, and FIG. 2 is a timing chart of control signals of the circuit shown in FIG. A data input terminal D of the flip-flop circuit 10 is connected to a transmission gate 21 as an example of a first switch circuit according to the present invention and an output side of a transmission gate 22 as an example of a second switch circuit according to the present invention. The data input signal D in the normal operation mode and the test signal SI in the test mode are input from the input sides of these two transmission gates 21 and 22, respectively. Each transmission gate 21, 22 is shown in FIG.
It is controlled by the control signals N and SGO as shown in FIG. Here, N 'and SGO' are control signals N and S, respectively.
This is a signal obtained by inverting the logic of GO. The clock signal CLK is also input to the flip-flop circuit 10.

In the circuit shown in FIG. 1, during normal operation mode, control signals N and SGO are held at logic "1" and logic "0", respectively, so that transmission gates 21 and 22 are turned on. And the data input signal D reaches the data input terminal D of the flip-flop circuit 10 via the transmission gate 21.
Is taken into the flip-flop circuit at the rising timing of the clock signal CLK, and a signal having the same logic as the data input signal D is output from the output terminal Q.

On the other hand, in the test mode, the control signal N is held at logic "0" and the transmission gate 21 is kept off, but the control signal SGO is turned on / off at the timing shown in FIG. That is, the clock signal CL
Prior to each rising edge of K, the signal changes to logic '0' by the maximum time width t in which a clock skew may occur, thereby changing the transmission gate 22 to a non-conductive state. Here, the flip-flop circuit 10 is constituted by a two-stage latch circuit.
The output of the latch circuit of the stage is, for example, 10 msec. Since the data is held for such a sufficiently long time, the test signal SI immediately before the non-conductive state is output from the output terminal Q of the flip-flop circuit 10 at the subsequent rising edge of the clock signal CLK. Therefore, if a test shift register circuit is constructed by sequentially connecting the storage circuits shown in FIG. 1 so that the output terminal Q of the preceding flip-flop circuit 10 is connected to the input side of the transmission gate 22 of the next stage, the clock Signal CL
A highly reliable test that does not cause a malfunction due to the clock skew of K can be performed.

Although the control signal SGO is turned on / off at the timing shown in FIG. 2 in the embodiment shown in FIG. 1, the embodiment shown in FIG. Similarly, the control signal SGO may be turned on / off at the timing shown in FIG. FIG. 4 will be described later. FIG. 3 is a circuit block diagram of one embodiment of the second storage circuit of the present invention, and FIG. 4 is a timing chart of control signals of the circuit shown in FIG.

The data input terminal D of the latch circuit 30
The transmission gate 41 and the output terminal of the tri-state buffer 42 are connected. A transmission gate 43 is connected to an input terminal of the tri-state buffer 42. From each input side of each of the transmission gates 41 and 43, a data input signal D in a normal operation mode and a test input signal SI in a test mode are input. Here, the transmission gates 41 and 43 are controlled by the control signals N and SGO shown in FIG. 3B, respectively, as in the embodiment shown in FIG. The clock signal CLK is also input to the latch circuit 30. In the present embodiment, the tristate buffer 42 and the transmission gate 43 constitute a second switch circuit referred to as a second storage circuit of the present invention.

In the circuit shown in FIG. 3, in a normal operation mode, control signal N is held at logic "1", whereby transmission gate 41 is kept conductive and tri-stated buffer 42 is shut off. This is a bad state (a state where the output side of the tri-state buffer 42 is kept at high impedance). Further, in this embodiment, in this operation mode, the transmission gate 43 may be in either a conductive state or a non-conductive state, but here, the control signal SGO is held at logic '0',
Therefore, transmission gate 43 is kept off. In this operation mode, the data input signal D becomes valid, and when the clock signal CLK rises, the data input signal D that has reached the input terminal D of the latch circuit 30 via the transmission gate 41 remains at the output terminal Q while maintaining its logic. Output. When the data input signal D is inverted in this state, the signal Q output from the output terminal Q is also inverted.
Thereafter, when the clock signal CLK falls, the data input signal D input from the input terminal D of the latch circuit 30 is latched by the latch circuit 30 at the falling timing, and the output terminal Q of the latch circuit 30 The output signal Q having the same logic as the data input signal D at the falling timing continues to be output.

On the other hand, in the test mode, the control signal N is held at logic "0", whereby the transmission gate 41 is kept in a non-conductive state, and the tri-state buffer 42 is connected to the input terminal of the tri-state buffer 42. The logic "1" or logic "0" signal input from the
An operation state for transmitting the signal to the output terminal 2 is obtained. In this state, the control signal SGO is turned on / off as shown in FIG. That is, prior to each rising timing of the clock signal CLK, the logic signal changes to logic "0" in advance of the maximum time width t in which a clock skew may occur, thereby changing the transmission gate 43 to a non-conductive state. After that, for example, 10 msec. For a sufficiently long time, the data immediately before the transmission gate 43 changes to the non-conductive state is held at the output side of the tri-state buffer 42. When the clock signal CLK rises in this state, the output signal Q from the output terminal Q of the latch circuit 30 becomes a signal of the same logic as the output signal of the tri-state buffer 42. This state is maintained. Since the timing of the rise of the control signal SGO is after the fall of the clock signal CLK, the rise of the control signal SGO turns on the transmission gate 43 and the test input signal SI is applied to the input terminal D of the latch circuit 30. Even if it reaches, no change occurs in the state of the latch circuit 30. Therefore, if the output terminal Q of the previous-stage latch circuit 30 is connected to any number of stages so as to be connected to the input side of the next-stage transmission gate 43,
The circuit shown in FIG. 3 operates as a flip-flop circuit at the time of dynamic operation in spite of being a latch circuit as a static circuit, thereby forming a test shift register circuit, and malfunctioning due to clock skew of the clock signal CLK. A highly reliable scan test that does not occur can be performed. Incidentally, it is needless to say that a shift register circuit in which the latch circuit shown in FIG. 3 and the flip-flop circuit shown in FIG. 1 are mixed can be formed.

FIG. 5 is a circuit block diagram showing a state where a plurality of the storage circuits shown in FIG. 1 and / or the plurality of storage circuits shown in FIG. 3 are connected. Here, each storage circuit is represented by one block. By holding the control signal N at logic “1” and the control signal SGO at logic “0”, each storage circuit operates as an independent storage circuit, and the control signal N
Is held at the logic '0' and the control signal SGO is turned on / off at the above-described timing, thereby operating as a shift register in which data is shifted one by one every time a clock pulse is input.

Although the respective memory circuits are arranged adjacent to each other in this figure, they are actually often arranged at positions separated from each other on the semiconductor chip. FIG. 6 (A), (B)
FIG. 4 is a circuit diagram showing each embodiment of the first recording circuit of the present invention which is different from the embodiment shown in FIG. 1 and different from each other. Note that a circuit corresponding to FIG. 1B is not illustrated here.

FIG. 6A shows an example in which the transmission gates 21 and 22 in the embodiment shown in FIG. 1 are replaced by one transmission gate 23 and 24, respectively, and FIG. The transmission gates 21 and 22 in the illustrated embodiment are replaced with tri-state buffers 25 and 26. Further, since these tri-state buffers 25 and 26 are of the type whose logic is inverted on the output side, an inverter 27 is added. It is an example. As described above, the first switch circuit and the second switch circuit in the first storage circuit of the present invention are not limited to a specific configuration, but can be variously configured.

FIGS. 7A and 7B are circuit diagrams showing embodiments of the second storage circuit according to the present invention which are different from the embodiment shown in FIG. 3 and different from each other. Here, however, as in the case of FIG. 6, the illustration of the circuit corresponding to FIG. 3B is omitted. FIG. 7A shows transmission gates 41 and 43 in the embodiment shown in FIG.
FIG. 7B shows an example in which the transmission gates 41 and 43 in the embodiment shown in FIG. 3 are replaced with tri-state buffers 46 and 47, respectively. This is an example in which an inverter 48 is added because the logic is inverted. As described above, the first switch circuit and the second switch circuit in the second storage circuit of the present invention can be variously configured.

FIG. 8 is a circuit diagram showing an embodiment of the third storage circuit of the present invention. As shown in FIG.
The input terminal D is connected to the input side of the transfer gate 51, and the output side of the transfer gate 51 is connected to the input terminal of the inverter 52 and one end of the transfer gate 53. The other end of the transfer gate 53 is connected to the output terminal of the inverter 54. Also,
The output terminal of the inverter 52 is connected to the input terminal of the inverter 54 and one end of the transfer gate 55. The other end of the transfer gate 55 is connected to one end of another transfer gate 56, and the other end of the transfer gate 56 is connected to the input terminal of the inverter 57 and one end of the transfer gate 58. The other end of the transfer gate 58 is connected to an inverter 59
Output terminal. The output terminal of the inverter 57 is connected to the input terminal and the output terminal Q of the inverter 59. Also, two transfer gates 55,
The output terminal of the tri-state buffer 60 is connected to the connection point 56, and the trans-state buffer 60
The test signal SI is inputted from the input terminal side of.

In order to operate the circuit constructed as described above, the clock signals CLK and CL whose phases are opposite to each other are used.
K ', control signals N and N', and control signals SGO and SGO 'are required, but the clock signal CLK, the control signals N and SG
O is input from the outside, and signals CLK ', N' and SGO 'whose logic is inverted are generated by the inverter circuit shown in FIG.

In the memory circuit configured as described above, in the normal operation mode, the transfer gate 5
5 is held in a conductive state, and the tri-state buffer 60 is held in a cut-off state in which the output side has a high impedance. In this state, when the clock CLK rises in a state where an H-level signal is input to the input terminal D as the data input signal D, the transfer gate 51 which has been conductive until then transitions to a non-conductive state,
At the same time, the transfer gate 53, which was in the non-conductive state, changes to the conductive state, and the inverters 52, 5
4 and the transfer gate 53 latch the H-level signal in the loop. At the same time, the transfer gate 56 shifts to the conductive state, and the H-level signal is output to the outside of the storage circuit via the inverter 57. . In this state, it is assumed that the signal at the input terminal D has transitioned to the L level, and when the clock signal CLK falls in that state, the transfer gate 58 transitions to the conducting state and
The level signal is latched in the second-stage loop. At the same time, the transfer gates 53 and 56 are turned off and the transfer gate 51 is turned on to transfer the L-level signal input from the input terminal D. The light is transmitted to the transfer gate 56 via the gate 51.

By repeating the above operation in synchronization with clock signal CLK, an H-level or L-level signal input from input terminal D is output at each rising timing of clock signal CLK. In the test mode, the control signal N is held at logic '0', the transfer gate 55 is held in a non-conductive state, and the control signal SGO is turned on / off at the timing shown in FIG.
Since the timing shown in FIG. 4 has been described above, the description thereof is omitted here. With this configuration, the second-stage latch circuit shown in FIG. 8 can be incorporated into a test shift register, and a test using a highly reliable scan test method without malfunction due to clock skew can be performed. .

[0034]

As described in detail above, the storage circuit of the present invention has the first switch circuit and the second switch circuit which are controlled independently of each other, and thus these switch circuits are appropriately controlled. By doing so, when a large number of storage circuits are connected to form a shift register and a test is performed by the scan test method, a highly reliable test without malfunction due to clock skew can be performed.
By providing a tri-state buffer on the output side of the second switch circuit, the latch circuit can be incorporated into the test shift register to perform a test.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of one embodiment of a first storage circuit of the present invention.

FIG. 2 is a timing chart of control signals of the circuit shown in FIG.

FIG. 3 is a circuit block diagram of one embodiment of a second storage circuit of the present invention.

FIG. 4 is a timing chart of a control signal of the circuit shown in FIG. 3;

5 is a circuit block diagram showing a state where a plurality of storage circuits shown in FIG. 1 and / or a plurality of storage circuits shown in FIG. 3 are connected.

FIG. 6 is a circuit block diagram of each embodiment of the first storage circuit of the present invention.

FIG. 7 is a circuit block diagram of each embodiment of the second storage circuit of the present invention.

FIG. 8 is a circuit diagram showing one embodiment of a third storage circuit of the present invention.

FIG. 9 is a diagram conceptually showing a shift register circuit wired for testing in a semiconductor integrated circuit.

FIG. 10 is a diagram illustrating only one flip-flop circuit included in the shift register circuit illustrated in FIG. 9;

[Explanation of symbols]

 Reference Signs List 10 flip-flop circuit 21, 22, 23, 24 transfer gate 25, 26 tristate buffer 30 latch circuit 41, 43, 44, 45 transfer gate 42, 46, 47 tristate buffer 55 transfer gate 60 tristate buffer

Claims (3)

(57) [Claims] A first signal input terminal and a clock signal;
Input at a predetermined clock edge of the clock signal
A flip-flop circuit incorporating, interposed between the input terminal of the first signal input terminal the flip-flop circuit, maintained in non-conductive state in a predetermined test mode
A first switch circuit, a second signal input terminal, and interposed between the second signal input terminal and the input terminal of the flip-flop circuit, in the test mode,
Temporally relative to the timing of the predetermined clock edge
Transitions to a non-conducting state earlier than the predetermined clock edge.
The second is controlled to transit to the conductive state later in time .
And a switch circuit. 2. A first signal input terminal, a latch circuit,
A non-conductive state in a predetermined test mode interposed between the first signal input terminal and the input terminal of the latch circuit;
A first switch circuit is kept, and a second signal input terminal, and interposed between the second signal input terminal and the input terminal of said latch circuit, in the test mode, the
A latch circuit that latches a signal in the latch circuit;
Transitions to the conductive state while the switch is in the
A second switch circuit having a tri-state buffer on an output side, the storage circuit being controlled to return to a state. A latch circuit of the preceding stage side constituting the 3. The flip-flop circuit, a latch circuit in the subsequent stage side constituting the flip-flop circuit, the input <br/> pin or al the subsequent latch circuit of the preceding stage interposed either between the input end frame of the latch circuit side, a first switch circuit to be kept in the non-conductive state in a predetermined test mode, a test signal input terminal, and said test signal input terminal A conductive state intervenes between the input terminal of the subsequent-stage latch circuit and a latch state in which the signal is latched in the latter-stage latch circuit in the test mode. storage circuit, characterized in that a transition to be controlled to return to the non-conducting state again belt <br/>-state buffer to.