JPH05160682A - Flip-flop - Google Patents

Abstract

PURPOSE:To expedite to make a fast logic integrated circuit device, etc., employing an LSSD system into low cost without impairing the speediness of the circuit by realizing a fast and low-cost edge trigger flip-flop provided with a data-through function. CONSTITUTION:A slave latch SL is kept in a data transmitting state or a data holding state by a clock signal CK when an inversion internal control signal SMB is kept at a high level, and in kept in the data transmitting state stationarily when the signal SMB is kept at a low level. A master latch ML goes to the holding state or the transmitting state under a condition complementary with the slave latch SL when it is kept at the high level, and it goes to the transmitting state stationarily when it is kept at the low level. In an operating mode, a series circuit of those two latch circuits functions as the edge trigger flip-flop by setting the signal SMB at the high level, and in a diagnostic mode, it functions as a data through circuit by setting the signal SMB at the low level, thereby, it is possible to efficiently perform the test of the fast logic integrated circuit device, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop, and more particularly to a technique which is particularly effective for use in an edge trigger flip-flop mounted on a high speed logic integrated circuit device adopting the LSSD system.

[0002]

2. Description of the Related Art There is a high-speed logic integrated circuit device in which a combinational circuit for performing a predetermined logical operation processing and a plurality of flip-flops for temporarily holding input or output data of the combinational circuit are combined. Further, in such a high-speed logic integrated circuit device, flip-flops provided on the input side or the output side of the combinational circuit are serially coupled and predetermined diagnostic data is scanned in or out to obtain a high-speed logic integrated circuit device. LSSD (Level Sensitiv) for efficiently performing tests and diagnoses such as
e Scan Design) method.

A high-speed logic integrated circuit device or the like adopting the LSSD system is disclosed in, for example, 19 of Nikkei McGraw-Hill.
It is described on pages 57 to 63 of Nikkei Electronics, April 16, 1979.

[0004]

Conventionally, the logical operation processing in the above-mentioned high-speed logic integrated circuit device or the like has been controlled according to the clock signals of a plurality of phases. Phase conversion is becoming an essential condition. In this case, an edge trigger flip-flop adaptable to a single-phase clock signal is used as the flip-flop provided on the input side or the output side of each combinational circuit.

On the other hand, in a high-speed logic integrated circuit device or the like adopting the LSSD system, the flip-flops forming the scan-in or scan-out path are required to have a predetermined shift function as well, and a normal flip-flop having no shift function is required. Its cost is higher than that of a flip-flop. However, in a high-speed logic integrated circuit device or the like, not all flip-flops mounted are effective for diagnosis, and if possible, these flip-flops are removed from the scan-in or scan-out path, and the high-speed logic integrated circuit device It is desirable to reduce costs. in this case,
Flip-flops that are not included in the scan-in or scan-out path must have a so-called data-through function that allows input data to pass therethrough and transmit it to subsequent circuits. However, edge triggers used in conventional high-speed logic integrated circuit devices, etc. The flip-flop does not have this data through function, as illustrated in FIG. Further, if these edge trigger flip-flops are to be replaced with other types of flip-flops having a data-through function, it is necessary to make the clock signals in multiple phases, and on the contrary, the high speed of the high speed logic integrated circuit device is impaired.

An object of the present invention is to provide a high speed and low cost edge trigger flip-flop having a data through function. Another object of this invention is LSS.
It is to promote the cost reduction of the high-speed logic integrated circuit device adopting the D method without impairing the high-speed performance.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a pair of a slave latch and a master latch in which the edge-trigger flip-flop is formed in a serial form and is in a data transmission state or a data holding state complementary to each other in a normal operation mode and both are in a data transmission state in a predetermined diagnostic mode. Compose by.

[0009]

According to the above means, it is possible to realize a high-speed and low-cost flip-flop which can function as an edge trigger flip-flop in a normal operation mode and a data through circuit in a predetermined diagnostic mode with a relatively simple circuit configuration. realizable. As a result, flip-flops that are not effective for diagnosis can be removed from the scan-in or scan-out path without requiring multiple phases of the clock signal, so that high-speed logic integrated circuit devices adopting the LSSD method can be implemented at high speed. The cost reduction can be promoted without loss.

[0010]

1 is a circuit diagram of an embodiment of an edge trigger flip-flop FF to which the present invention is applied. An outline of the configuration and operation of the edge trigger flip-flop FF of this embodiment will be described with reference to FIG. The edge trigger flip-flop FF of this embodiment is mounted on a high-speed logic integrated circuit device adopting the LSSD system together with a large number of similar edge trigger flip-flops. The circuit element forming the edge trigger flip-flop FF is formed on one semiconductor substrate such as single crystal silicon together with other circuit elements forming the high speed logic integrated circuit device. In the circuit diagram below, a MOSFET with an arrow on its channel (back gate) part
(Metal oxide semiconductor field effect transistor. In this specification, MOSFET is a generic term for an insulated gate field effect transistor) is a P-channel type and is shown separately from an N-channel MOSFET without an arrow. .. Please refer to FIG. 2 to FIG. 4 for specific circuit configurations of the inverter, the NOR gate, and the NAND gate that form the edge trigger flip-flop FF.

In FIG. 1, the edge trigger flip-flop FF includes a pair of slave latches SL (first latch circuit) and a master latch ML provided in series.
(Second latch circuit). Among them, the slave latch SL is a P channel and N channel MOSFE.
It includes a switch S1 (first switch means) in which Ts are connected in parallel. The input node of the switch S1 is supplied with an inverted signal of the input data D by the inverter N1, and its output node is coupled to the output terminal of the slave latch SL, that is, the internal node P (first internal node), and It is coupled to the input terminal of N2 (first logic gate circuit). The gate of the N-channel MOSFET forming the switch S1 has an output signal of the NAND gate NA1, that is, an inverted internal clock signal CK2B (here, a so-called inverted signal which is selectively brought to a low level when it is enabled has its name. Of the P channel MO
The SFET gate has an inverted internal clock signal CK2B.
An inverted signal of the inverter N9, that is, the internal clock signal CK2 is supplied. As a result, the switch S1 is
The internal clock signal CK2 is a logical "0" (here, the state in which the non-inverted signal is at the low level and the inverted signal is at the high level is referred to as the logical "0", and the opposite state is referred to as the logical "1". The same applies hereinafter), and it is selectively turned on to transmit the inverted signal of the input data D to the internal node P and the input terminal of the inverter N2.

A predetermined inverted internal control signal SMB is supplied from a control circuit (not shown) of the high-speed logic integrated circuit device to one input terminal of the NAND gate NA1, and an output signal of the NOR gate NO1, ie, an inverted signal, is supplied to the other input terminal. An inverted signal of the internal clock signal CK1B by the inverter N8, that is, the internal clock signal CK1 is supplied. Further, the inverted signal of the inverted internal control signal SMB by the inverter N7 is supplied to one input terminal of the NOR gate NO1 and the clock signal CK is supplied to the other input terminal. Here, the clock signal CK is a pulse signal having a predetermined cycle, and the inverted internal control signal SMB is selectively set to a low level when the high-speed logic integrated circuit device is in a predetermined diagnostic mode, as described later. It

As a result of these, the internal clock signal CK1
Is a pulse signal according to the clock signal CK when the high-speed logic integrated circuit device is in the normal operation mode and the inverted internal control signal SMB is at the high level, and the high-speed logic integrated circuit device is in the predetermined diagnostic mode. Inverted internal control signal S
When MB is at low level, it is fixed at high level. Similarly, the internal clock signal CK2 is the inverted internal control signal S when the high speed logic integrated circuit device is set to the normal operation mode.
When MB is at a high level, it is a pulse signal according to the clock signal CK, and when the high-speed logic integrated circuit device is in a predetermined diagnostic mode and the inverted internal control signal SMB is at a low level, it is fixed at a low level. Needless to say, the inverted internal clock signals CK1B and CK2B are complementary signals to the internal clock signal CK1 or CK2.
Further, from the above, the switch S1 forming the slave latch SL selectively operates on condition that the clock signal CK is logic "0" when the high-speed logic integrated circuit device is in the normal operation mode. When the high-speed logic integrated circuit device is turned on and the high-speed logic integrated circuit device is set to a predetermined diagnostic mode, it is constantly turned on.

Slave latch SL further includes an inverter N3 (second logic gate circuit) receiving the output signal of inverter N2. The output terminal of inverter N3 is coupled to internal node P via switch S2. The internal clock signal CK2 is supplied to the gate of the N-channel MOSFET that constitutes the switch S2, and the inverted internal clock signal CK is supplied to the gate of the P-channel MOSFET.
2B is supplied. As a result, when the internal clock signal CK2 is set to logic "1", in other words, the switch S2 sets the high-speed logic integrated circuit device to the normal operation mode and the clock signal CK is set to logic "1" (first When it is set to the logic level), it is selectively turned on, whereby the inverters N2 and N3 are latched. When the high-speed logic integrated circuit device is set to the predetermined diagnostic mode and the inverted internal control signal SMB is set to the low level, the switch S2 is constantly turned off.

That is, when the high-speed logic integrated circuit device is set to the normal operation mode, the slave latch SL is set to the data transmission state by receiving the logic "0" of the clock signal CK, and the input data D is inverted to the internal state. While transmitting to the node P, it receives the logic "1" of the clock signal CK and is brought into a data holding state, and holds the logic level immediately before the input data D. When the high speed logic integrated circuit device is set to a predetermined diagnostic mode, the slave latch SL is constantly in the data transmission state.

Next, the master latch ML includes a switch S3 (second switch means) in which P-channel and N-channel MOSFETs are similarly connected in parallel. The input node of switch S3 is coupled to internal node P,
The output node is coupled to the input terminal (second internal node) of the inverter N6, and
It is coupled to the input terminal of (third logic gate circuit). The output terminal of the inverter N6 is coupled to the output terminal of the master latch ML, that is, the output terminal Q of the edge trigger flip-flop. The internal clock signal CK is applied to the gate of the N-channel MOSFET that constitutes the switch S3.
1 is supplied, and the inverted internal clock signal CK1B is supplied to the gate of the P-channel MOSFET. As a result, the switch S3 is selectively turned on when the internal clock signal CK1 is logic "1", and the output signal of the slave latch SL, that is, the potential of the internal node P is transmitted to the input terminals of the inverters N4 and N6. To do.

Master latch ML further includes an inverter N5 (fourth logic gate circuit) receiving the output signal of inverter N4. The output terminal of inverter N5 is coupled to the input terminal of inverter N6 via switch S4. N-channel MOSFE that constitutes the switch S4
The inverted internal clock signal CK1B is supplied to the gate of T, and the internal clock signal CK1 is supplied to the gate of the P-channel MOSFET. Thus, the switch S4 sets the internal clock signal CK1 to the logic "0", in other words, sets the high-speed logic integrated circuit device to the normal operation mode and sets the clock signal CK to the logic "0".
When it is set to (second logic level), it is selectively turned on, whereby the inverters N4 and N5 are latched. When the high-speed logic integrated circuit device is set to the predetermined diagnostic mode and the inverted internal control signal SMB is set to the low level, the switch S4 is constantly turned off.

As described above, the master latch ML receives data "1" on the complementary condition of the slave latch SL when the high-speed logic integrated circuit device is set to the normal operation mode, that is, the logic "1" of the clock signal CK is received. In the transmission state, the potential of the output terminal of the slave latch SL, that is, the internal node P is inverted and transmitted to the output terminal Q of the edge trigger flip-flop. Further, the logic level "0" of the clock signal CK is received so that the data is held, and the logic level immediately before the output signal Q is held. When the high-speed logic integrated circuit device is set to the predetermined diagnostic mode, the master latch ML and the slave latch SL are constantly brought into the data transmission state.

FIG. 5 shows a truth diagram of the edge trigger flip-flop FF of FIG. 1, and FIG. 6 shows a signal waveform diagram thereof. The operation and characteristics of the edge trigger flip-flop of this embodiment will be described with reference to these drawings.

When the high-speed logic integrated circuit device is set to the normal operation mode, the inverted internal control signal SMB is set to the high level (H) as described above, and the internal clock signal CK1.
(Here, with the internal clock signal CK1, the non-inverted internal clock signal CK1 and the inverted internal clock signal CK1B
On behalf of. The same applies hereinafter) and CK2 are pulse signals according to the clock signal CK, as shown in FIG. As shown in FIG. 5, the input data D is inverted and transmitted to the internal node P while the internal clock signal CK2 is at logic "0", that is, the clock signal CK is at the low level (L), and is transmitted. Is a logic "1", that is, while the clock signal CK is at a high level, the slave latch SL holds the logic level Pn-1 immediately before the internal node P. That is, the logic level at the output terminal of the slave latch SL, that is, at the internal node P is changed according to the input data D while the clock signal CK is at the low level, but at the rising edge of the clock signal CK when it is at the high level. It is fixed to hold the logic level.

On the other hand, the logic level Pn-1 of the internal node P
Is inverted and transmitted to the output terminal Q of the edge trigger flip-flop while the internal clock signal CK1 is logical "1", that is, the clock signal CK is at a high level, and the internal clock signal CK1 is logical "0", that is, the clock signal. C
While K is at low level, the logic level Qn-1 immediately before that is held by the master latch ML.
As a result, the logic level at the output terminal of the master latch ML, that is, the output terminal Q of the edge trigger flip-flop FF is changed according to the input data D at the rising edge of the clock signal CK, but the clock signal CK is set to high level or low level. After that, the logic level of the input data D at the rising edge of the clock signal CK is held and fixed. As a result, the flip-flop FF1 of FIG. 1 sets the high-speed logic integrated circuit device to the normal operation mode and inverts the internal control signal SM.
Clock signal C provided that B is at a high level
It functions as an edge-triggered flip-flop whose state is transitioned at the rising edge of K. At this time, the so-called signal transmission delay time from when the clock signal CK is logic "1" to when the logic level of the output signal Q of the edge trigger flip-flop is determined is only the transmission delay time by the inverter N6. The operation of the edge trigger flip-flop FF is extremely speeded up.

Next, when the high speed logic integrated circuit device is set to a predetermined diagnostic mode, the inverted internal control signal SMB is set to the low level as described above. Therefore, the internal clock signal CK1 is, as shown in FIG.
It is fixed to logic "0" regardless of K, and the internal clock signal CK2 is fixed to logic "1". Therefore, in the slave latch SL, the switch S1 is constantly turned on and the switch S2 is constantly turned off. In the master latch ML, the switch S3 is constantly turned on and the switch S4 is normally turned off. As a result, the input data D is transmitted to the output terminal Q of the flip-flop FF substantially as it is, without depending on the clock signal. That is, the flip-flop FF of FIG. 1 functions as an edge trigger flip-flop when the high-speed logic integrated circuit device is in the normal operation mode, the high-speed logic integrated circuit device is in a predetermined diagnostic mode, and the inverted internal control signal SMB is While it is at the low level, it functions as a data through circuit and transmits the input data D as it is to its output terminal. As is apparent from FIG. 1, the flip-flop FF has a data through function and can operate at high speed, but has a relatively simple circuit configuration, and thus has a relatively low cost.

FIG. 7 shows a circuit block diagram of an embodiment of a logical operation circuit LC using the edge trigger flip-flop shown in FIG. A method of using the edge trigger flip-flop of this embodiment and an outline of the LSSD system will be described with reference to FIG.

In FIG. 7, the logical operation circuit LC of this embodiment is not particularly limited, but two combinational circuits CB1.
(First combination circuit) and CB2 (second combination circuit)
including. Each of these combinational circuits is composed of a plurality of logic gate circuits and executes a predetermined logical operation process. Four flip-flops SFF1 to SFF4 are provided on the input side of the combinational circuit CB1.
On the output side of B2, four flip-flops SFF5 to
SFF8 is provided. These flip-flops SF
F1 to SFF8 have a shift function for realizing the LSSD method and have a relatively complicated circuit configuration.

Data input terminals D of the flip-flops SFF1 to SFF4 are respectively supplied with corresponding input data D1 to D4 from a pre-stage circuit (not shown) of the high-speed logic integrated circuit device, and the output signal Q thereof corresponds to the combinational circuit CB1. Are supplied to the respective input terminals. On the other hand, the scan-in data SID is supplied to the diagnostic data input terminal S of the flip-flop SFF1 via a test circuit (not shown) of the high-speed logic integrated circuit device, and its diagnostic output terminal QS is used for diagnostic purposes of the flip-flop SFF2. It is coupled to the data input terminal S. Similarly, the flip-flop SF
The diagnostic output terminals QS of F2 to SFF3 are sequentially coupled to the diagnostic data input terminals S of the next stage flip-flops SFF3 to SFF4, and the final stage flip-flop SFF4.
The diagnostic output terminal QS (QS4) is coupled to the diagnostic input terminal S of the flip-flop SFF5, for example. Alternatively, the scan-out data SOD may be output from the subsequent circuit. Flip-flop SFF
A clock signal CK is commonly supplied to the clock input terminals CK of 1 to SFF4, and a predetermined shift clock signal SCK is commonly supplied to the diagnostic clock input terminal C. The control terminal SMB of each flip-flop is commonly supplied with an inverted internal control signal SMB that is selectively set to a low level in a predetermined diagnostic mode.

Next, the flip-flops SFF5 to SFF.
The corresponding output signals from the combinational circuit CB2 are supplied to the data input terminals D of 8 respectively, and the output signal Q thereof is
The output data Q1 to Q4 of the logical operation circuit LC are supplied to a not-shown subsequent circuit of the high-speed logic integrated circuit device.
On the other hand, the diagnostic data input terminal S of the flip-flop SFF5 is coupled to, for example, the diagnostic output terminal QS (QS4) of the flip-flop SFF4, and the diagnostic output terminal Q thereof is connected.
S is coupled to the diagnostic data input terminal S of flip-flop SFF6. Alternatively, the flip-flop S
Scan-in data may be input to the diagnostic data input terminal S of the FF5 like the diagnostic data input terminal S of the flip-flop SFF1. Similarly, the diagnostic output terminals Q of the flip-flops SFF6 to SFF7.
S is sequentially coupled to the diagnostic data input terminal S of the next-stage flip-flops SFF7 to SFF8, and the diagnostic output signal QS of the final-stage flip-flop FF8 is supplied to a subsequent circuit (not shown) as scan-out data SOD. .. The clock signal CK is commonly supplied to the clock input terminals CK of the flip-flops SFF5 to SFF8, and the shift clock signal SCK is commonly supplied to the diagnostic clock input terminal C. The inverted internal control signal SMB is commonly supplied to the control terminal SMB of each flip-flop.

The logical operation circuit LC of this embodiment further includes a flip-flop group including four flip-flops FF1 to FF4 provided between the combinational circuits CB1 and CB2. In this embodiment, the flip-flop F
F1 to FF4 are less effective in diagnosing the high-speed logic integrated circuit device and are not included in the scan-in or scan-out path. Therefore, all of these flip-flops are the edge-triggered flip-flops F of FIG.
It is composed of F. Flip-flops FF1 to FF
The data input terminals D of 4 are supplied with the corresponding output signals of the combinational circuit CB1, the output terminals Q of which are respectively coupled to the corresponding input terminals of the combinational circuit CB2. The inverted internal control signal SMB is commonly supplied to the control terminal SMB of each flip-flop, and the clock signal CK is commonly supplied to its clock input terminal CK.

When the high-speed logic integrated circuit device is in the normal operation mode and the inverted internal control signal SMB is at the high level, the flip-flops SFF1 to SFF4 function as edge trigger flip-flops and the corresponding input data D1 to D4. Are taken in at the rising edge of the clock signal CK and transmitted to the combinational circuit CB1. Similarly, the flip-flops SFF5 to SFF8 also function as edge trigger flip-flops, and the combinational circuit CB2.
At the rising edge of the clock signal CK, and outputs it as the output data Q1 to Q4 of the logical operation circuit LC to the subsequent circuit. At this time, the flip-flops FF1 to FF4 also function as edge trigger flip-flops, take in the corresponding output signals of the combinational circuit CB1 at the rising edge of the clock signal CK, and transfer them to the corresponding input terminals of the combinational circuit CB2.

On the other hand, when the high-speed logic integrated circuit device is set to a predetermined diagnostic mode and the inverted internal control signal SMB is set to the low level, the flip-flops SFF1 to SFF4 are in the form of a shift register to form a so-called scan-in path and scan-in. The diagnostic data supplied as the data SID is sequentially taken in according to the diagnostic clock signal SCK and transmitted to the combinational circuit CB1. Similarly, the flip-flops SFF5 to SFF8 have a shift register form to form a so-called scan-out path, and the combinational circuit C
The output signal of B2 is sequentially transmitted according to the diagnostic clock signal SCK, and is output as scan-out data SOD to a test circuit (not shown). At this time, the flip-flops FF1 to FF4 function as a data through circuit, and the output signal of the combination circuit CB1 is transmitted as it is to the combination circuit CB2.

As a result, in the high-speed logic integrated circuit device of this embodiment, the predetermined diagnostic data is scanned in even though the flip-flop group consisting of the flip-flops FF1 to FF4 is provided between the combinational circuits CB1 and CB2. Logical operation circuit L serially as data SID
Input to C and the calculation result is scan out data SO
Serially output as D and combining circuits CB1 and C
The normality of B2 can be confirmed accurately and efficiently. At this time, the flip-flops FF1 to FF4 are not included in the scan-in or scan-out path and function as a data through circuit. As described above, the edge-trigger flip-flops that form the flip-flops FF1 to FF4 have a relatively simple circuit configuration even though they have a data-through function, can be manufactured at low cost, and can operate at high speed. It is said that. As a result, the high-speed logic integrated circuit device of this embodiment is promoted for cost reduction without impairing high-speed performance.

As shown in the above embodiment, by applying the present invention to the edge trigger flip-flop mounted on the high speed logic integrated circuit device or the like adopting the LSSD system, the following operational effects can be obtained. .. That is, (1) the edge trigger flip-flops mounted on a high-speed logic integrated circuit device or the like are made into a serial form and are in a data transmission state or a data holding state complementarily to each other in a normal operation mode, and both are in a predetermined diagnostic mode. With a relatively simple circuit configuration, it functions as an edge trigger flip-flop in a normal operation mode, and as a data through circuit in a predetermined diagnostic mode, by configuring it with a pair of slave latches and master latches that are in a data transmission state. The effect that a possible high-speed and low-cost flip-flop can be realized is obtained. (2) According to the above item (1), it is possible to remove the edge-triggered flip-flops that are not effective for diagnosis from the scan-in or scan-out path without requiring the use of multiple phase clock signals. (3) According to the above items (1) and (2), it is possible to obtain the effect that the cost reduction can be promoted without impairing the high speed of the high speed logic integrated circuit device or the like adopting the LSSD system.

The invention made by the present inventor has been specifically described above based on the embodiments. However, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, P channel and N channel MO
The switches S1 to S4 composed of SFETs may be composed of any one of the MOSFETs, or other switch means may be used. Also, slave latch SL
As the inverters N2 and N3 and N4 and N5 that form the master latch ML, other kinds of logic gate circuits such as a NAND gate and a NOR gate can be used. The NAND gate NA1, NOR gate NO1 and inverters N7 to N9 for forming the internal clock signals CK1 and CK2 can be commonly provided in a plurality of flip-flops, and the logical configuration thereof is not limited by this embodiment. The slave latch SL and the master latch ML may have an arbitrary circuit configuration provided that they are in a data transmission state or a data holding state complementary to each other in a normal operation mode and both are in a data transmission state in a diagnostic mode. it can. In FIG. 6, the logic levels of the clock signal CK and the inverted internal control signal SMB, the logical combination of these signals, and the like can take various embodiments. In FIG. 7, the number of combinational circuits and flip-flops provided in the logical operation circuit LC can be set arbitrarily. Further, the inverted internal control signal SMB can be selectively set to the low level in the test modes other than the diagnostic mode, and the specific configuration of the logical operation circuit LC is not restricted by this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the edge trigger flip-flop included in the high-speed logic integrated circuit device which is the field of application of the background has been described, but the invention is not limited thereto. However, the present invention can be applied to a similar flip-flop included in a general-purpose gate array integrated circuit or various semiconductor memory devices, for example. This invention is at least LS
The present invention can be widely applied to edge-triggered flip-flops and semiconductor devices including such flip-flops, which are required to be compatible with the SD method.

[0034]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the edge-trigger flip-flops mounted on the high-speed logic integrated circuit device or the like are made into a serial form and are in a data transmission state or a data holding state complementarily to each other in a normal operation mode, and both are in a data transmission state in a predetermined diagnostic mode. By configuring with a pair of slave latch and master latch,
It is possible to realize a high-speed and low-cost flip-flop that can function as an edge trigger flip-flop in a normal operation mode and can function as a data through circuit in a predetermined diagnostic mode with a relatively simple circuit configuration.
As a result, edge trigger flip-flops that are not effective for diagnosis can be removed from the scan-in or scan-out path without requiring multiple phases of the clock signal, so that high-speed logic integrated circuit devices adopting the LSSD method can be used at high speed. The cost reduction can be promoted without spoiling the property.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an edge trigger flip-flop to which the present invention is applied.

FIG. 2 is a circuit diagram showing an embodiment of an inverter included in the edge trigger flip-flop shown in FIG.

3 is a circuit diagram showing an embodiment of a NOR gate included in the edge trigger flip-flop shown in FIG.

FIG. 4 is a circuit diagram showing an embodiment of a NAND gate included in the edge trigger flip-flop shown in FIG.

5 is a truth diagram of the edge-triggered flip-flop of FIG.

FIG. 6 is a signal waveform diagram showing an embodiment of the edge trigger flip-flop shown in FIG.

7 is a circuit block diagram showing an embodiment of a logical operation circuit using the edge trigger flip-flop shown in FIG.

FIG. 8 is a circuit diagram showing an example of a conventional edge trigger flip-flop.

[Explanation of symbols]

FF ... Edge trigger flip-flop, SL ...
Slave latch, ML ... Master latch, S1 to S
4 ... switch. LC ... Logical operation circuit, FF1
FF4 ... Edge trigger flip-flop, SFF1
-SFF8 ... Edge trigger flip-flop with shift function, CB1-CB2 ... Combination circuit. N1 to N1
1 ... Inverter, NO1 ... NOR gate, NA1 to NA7 ... NAND gate,
Q1-Q5 ... P-channel MOSFET, Q11-
Q15 ... N-channel MOSFET.

Claims (4)

[Claims] 1. A data through functioning as an edge-trigger flip-flop that operates in accordance with a predetermined clock signal in a normal operation mode and transmitting input data supplied to an input terminal to the output terminal substantially as it is in a predetermined test mode. A flip-flop characterized by functioning as a circuit. 2. The first and second flip-flops are formed in a serial form and are in a data transmission state or a data holding state complementary to each other in a normal operation mode, and both are in a data transmission state in the test mode. The flip-flop according to claim 1, comprising a latch circuit. 3. The first latch circuit selectively transmits input data to a first internal node in the test mode or when the clock signal is at a first logic level. And first and second logic gate circuits selectively latched so that their input / output nodes are coupled to the first internal node when the first switch means is turned off. The second latch circuit selectively outputs the output signal of the first latch circuit to the second internal node in the test mode or when the clock signal is at the second logic level. The second switch means for transmitting and the input / output node thereof is selectively latched to be coupled to the first internal node when the second switch means is turned off. 3. The flip-flop according to claim 2, including a third and a fourth logic gate circuit. 4. The flip-flop is included in a high-speed logic integrated circuit device adopting an LSSD method, and the test mode is a diagnostic mode of the high-speed logic integrated circuit device. Is a first combinational circuit having a scan-in path on its input side and a second combinational circuit having a scan-out path on its output side.
2. The combinational circuit according to claim 1 and a flip-flop group including the flip-flops provided between the first and second combinational circuits.
The flip-flop according to claim 2 or 3.