JP2659952B2 - Scannable flip-flop circuit and scan clock setting method - Google Patents

Description

[Detailed Description of the Invention] (Object of the Invention) (Industrial application field) The present invention relates to facilitation of test of a logic circuit.

(Prior Art) In scan design, it is important to minimize a decrease in system operation speed with a minimum number of additional circuits.
For this purpose, various attempts have been made as scan-capable flip-flops, and FIGS. 6 and 7 show examples thereof. In the figure, C is a clock in the system mode and is operated with a one-phase clock for speeding up. A
And B are two-phase clocks in the scan mode, and are both turned off in the system mode. DI is data input, Q
Is the output. In the scan mode, A and B are set so that the ON states do not overlap to avoid a clock skew problem. C is off. SI is scan input, SO
Is a scan output.

In FIG. 5, the inverted data is scanned in and scanned out. FIGS. 6 and 7 are characterized in that they operate as a master-slave type flip-flop in both the system mode and the scan mode.

(Problems to be Solved by the Invention) In FIG. 6, since Q and SO are common, there is a disadvantage that the speed of the system operation is affected by the wiring of the scan path. FIG. 7 removes this disadvantage, but adds the disadvantage that the number of elements increases.

[Configuration of the invention]

(Means for Solving the Problems) In order to prevent the deterioration of the system operation speed due to the wiring of the scan path without increasing the number of elements, the operation in the scan mode is not a master-slave type flip-flop operation but a two-phase clock. The signal transfer is performed by alternately repeating the static state holding by the latch and the dynamic state holding by the load capacitance.

(Operation) By making one of the latches a dynamic circuit based on the load capacitance, the number of elements can be reduced, and data can be scanned in and out in a stable shift register operation. Scan input data can be statically held in a latch portion and used in a system mode. Further, in the system mode, it is possible to prevent the speed deterioration due to the scan path wiring and to eliminate the floating node in the dynamic circuit, thereby preventing the generation of the through current.

(Embodiment) FIG. 1 shows a first embodiment of the present invention, in which C is a one-phase clock in a system mode, A and B are two-phase clocks in a scan mode, and DI and Q are in a system mode. Are data input and output, and SI and SO are scan input and scan output. In FIG. 1, scan input of the inverted data is performed,
Scan output will be performed. FIG. 2 shows the second embodiment of the present invention.
This is an embodiment of the present invention. C is a one-phase clock in system mode, A and B are two-phase clocks in scan mode, DI and Q
Is data input and output in the system mode, and SI and SO are scan input and scan output.

In the case of the first embodiment, in the scan mode, although C is in the off state, scan data is taken into the latch when B is on and A is off, and the latch is stable when both B and A are off. State. Next, when A is turned on and B is turned off, the load capacity of SO is charged. This charge is A, B
It is sufficient that both are held until the both are turned off.

 The same applies to the operation in the second embodiment.

As described above, in the system mode, in a flip-flop operating as a 1-bit shift register of a two-phase clock in the scan mode in a master-slave type of one-phase clock, the system operation speed by the scan path wiring is increased without increasing the number of elements. Can be prevented from deteriorating.

FIGS. 3 and 4 show third and fourth embodiments of the present invention, wherein C is a one-phase clock in the system mode, A and B are two-phase clocks in the scan mode, and DI and Q are Data input and output in system mode, and SI and SO are scan input and scan output.

In FIG. 3, the inverted data is scanned in and scanned out.

In the scan mode, C is in the off state, but when B is in the on state and A is in the off state, scan data is taken into the latch, and when both B and A are in the off state, the latch is in a stable state. Next, when A is turned on and B is turned off, the load capacity of SO is charged. This charge only needs to be held until both B and B are turned on and A is turned off again after both A and B are turned off.

In system mode, if both A and B are turned off,
In FIG. 4 and FIG. 4, the node N is in a floating state. Therefore, in the case of CMOS, the potential of the node N fluctuates, and a through current is generated in the next stage inbeta, so that power consumption is wasted. In order to prevent this, in the system mode, B is turned off but A may be turned on.

FIG. 5 is an example of a timing chart for testing the scan design circuit, in which three bits are scanned in, and after a system operation of one clock, three bits are scanned out. In FIG. 5, the timing at which data is taken in bit by bit at the time of scan input is indicated by arrows. Also, the range in which data is output during scan output is shown for each bit.

The scan clock A is set to the ON state in the system mode, and is set to have the same waveform periodically in the scan mode in consideration of the timing generator of the LSI tester.

In each of the above embodiments, a D-type flip-flop having no set and reset functions in the system mode has been described as an example. However, a set function and a reset function may be added as necessary, and a JK type may be used instead of the D type. good.

〔The invention's effect〕

In a system mode, a one-phase clock master-slave type, and in a scan mode, a flip-flop that operates as one bit of a two-phase clock shift register,
By partially performing the dynamic operation in the scan mode, it is possible to prevent the deterioration of the system operation speed due to the wiring of the scan path without increasing the number of elements. Further, by eliminating the floating state of the dynamic circuit in the system mode, waste of power consumption can be prevented.

[Brief description of the drawings]

1, 2, 3, and 4 are diagrams of an embodiment of the present invention, FIG. 5 is a timing chart for testing a scan design circuit, and FIG. 6 is a conventional scan-capable flip-flop. FIG. 7 is a diagram of a first example of a flip-flop, and FIG. 7 is a diagram of a second example of a conventional scannable flip-flop.

Claims (3)

(57) [Claims] 1. A configuration comprising a master latch and a slave latch capable of statically retaining a state, and a latch capable of dynamically retaining a state, wherein the slave latch is connected to the master latch, and the dynamic latch is connected to one of the master latch and the slave latch. In the system mode, it operates as a one-phase clock master-slave flip-flop in the system mode, and in the scan mode, holds the static state by one of the master latch and the slave latch by the two-phase clock and charges the load capacity of the latch capable of dynamically holding the state. A scan-capable flip-flop circuit for transferring a signal by alternately repeating a dynamic state holding determined by a state. 2. A circuit as claimed in claim 1, wherein said circuit realized by CMOS has a dynamic state that is controlled by one of two-phase clocks and a transfer gate, or an inverter connected to said transfer gate and an inverter connected thereto. 2. The scannable flip-flop circuit according to claim 1, wherein the scannable flip-flop circuit is realized by an equivalent circuit. 3. The system mode operates as a one-phase clock master-slave flip-flop in a system mode. In the scan mode, a dynamic latch is connected to one of the master latch and the slave latch according to claim 1 to provide a two-phase clock. Test by transferring the signal by
A transfer gate whose dynamic state is controlled by one of two-phase clocks and an inverter connected thereto, or a scanable CMOS flip-flop circuit realized by a circuit functionally equivalent to the transfer gate and the inverter connected thereto Wherein the transfer gate controlled by one of the two-phase clocks is turned on in the system mode in order to prevent a dynamic operation portion of the scan mode from having a floating mode in the system mode and generating a through current. Setting method.