JPS6336535B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a serial loop scan method in which flip-flops inside an LSI are configured as shift registers, and the flip-flops inside the LSI are The present invention relates to a scan method that prevents the values of flip-flops other than the desired flip-flops from being destroyed during scan-in.

[Conventional technology and problems]

When a circuit is converted into an LSI, the limit of input/output pins
Although it is difficult to directly know the state of an LSI's internal circuits, the scan-out method is an effective method for knowing the state of internal circuits with a small number of input/output pins.

In the conventional scan-out method, when attempting to read the contents of an arbitrary flip-flop or gate, it is possible to arbitrarily read the contents by applying the scan address assigned to each from outside the logic block. However, LSI
As the degree of integration increases, the number of flip-flops and logic gates to be read increases, the number of addresses X also increases, and the number of address lines n also increases. Since the relationship between address X and address line n is n=1og ₂ but,
Since there is a limit to the number of input/output pins per unit area, it will not be possible to keep up as the degree of integration increases.

Therefore, methods have been devised to enable scan-out without increasing the number of input/output pins even if the integration density of LSI increases. In this method, all the flip-flops in a logic block are connected in a cylindrical manner as a shift register, and when scan-out is performed, the data is sequentially shifted and read out using a scan clock. In this way, by combining the flip-flops in a logic block as a shift register and outputting the output of the last flip-flop to the outside of the logic block as a scan result, the necessary signals for scan-out can be transferred to the scan clock. This eliminates the need for scan address signals and reduces the number of input/output pins.

FIG. 2 is a diagram illustrating the problems of the serial loop scan-out method.

In FIG. 2, 1 indicates an LSI logic block, and 2 indicates an external processing device. All flip-flops in logic block 1 are in a shift register configuration, with the last flip-flop connected to the scan-out terminal and the first flip-flop connected to the scan-in terminal. In the conventional method shown in FIG. 2, if you want to scan out N-bit data from the M-th bit inside logic block 1, shift M+N bits to the target address and scan out the required N-bit data. Data was read from the shift register and then shifted again until all data returned to its original position. Since this is destructive reading, it is easy for erroneous operations to occur.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
In the serial loop scanning method,
It is an object of the present invention to provide a scanning method in which the contents of flip-flops in a logic block are not destroyed by scanning.

[Structure of the invention]

Therefore, in the scan method of the present invention, a plurality of flip-flops are connected in series to form a shift register, the last flip-flop is connected to the scan-out terminal, and the first flip-flop is connected to the scan-in terminal. a logic block, a shift register, a signal line connecting the serial input of the shift register to the scan-out terminal, an output connected to the scan-in terminal, one input terminal connected to the scan-out terminal, and a signal line connecting the serial input of the shift register to the scan-out terminal; a multiplexer whose terminals are connected to the serial output of the above shift register; a register to which any value can be set; an up counter whose value increases by a unit amount each time a shift signal is generated; The comparison circuit that compares the value of the up counter and the down counter that is set to an arbitrary value and whose value decreases by a unit amount each time a shift signal is generated in the counting enabled state match the above comparison circuit. control signal generating means for setting the down counter in a counting enabled state and outputting a signal of a predetermined value when the value of the down counter reaches zero; means for supplying the shift signal as a shift clock to the shift register when the control signal generating means is outputting a signal of a predetermined value; and means for supplying the shift signal as a shift clock to the shift register while the shift clock is being supplied to the shift register and the scan-in signal has a predetermined value; and means for supplying to the multiplexer a signal instructing that the serial output of the shift register should be selected.

[Embodiments of the invention]

FIG. 1 shows one embodiment of the present invention.
In FIG. 1, 3-1 to 3-3 are logic gates, 4-0 to 4-3 are flip-flops,
5 is a shift register, 6 is a multiplexer, 7-
1 and 7-2 are AND circuits, 8 is a register, 9 is an up counter, 10 is a down counter, 11
Reference numeral 12 indicates a comparison circuit, and 12 indicates a gate circuit. Note that the same reference numerals as in FIG. 1 indicate the same parts. All flip-flops 4-0, 4-1, 4-2, and 4-3 in logic block 1 are connected in series to form a shift register. Skiyan
The clock flips and flops 4-0, 4-1,
4-2 and 4-3, the contents of the flip-flop are shifted to the right. The last flip
Flop 4-0 is connected to the scanout terminal of logic block 1 and is connected to the first flip-flop 4-0.
-3 is connected to the scan-in terminal of logic block 1. The serial input of the shift register 5 is connected to a scan-out terminal, and the serial output is connected to one input of a multiplexer 6. The external processing device 2 can read data into the shift register 5 in parallel, and can write data into the shift register 5 in parallel.

The output of the AND circuit 7-2 is connected to the shift clock terminal of the shift register 5. The other input terminal of the multiplexer 6 is connected to the scan-out terminal of the logic block 1 by a signal line, and the output terminal of the multiplexer 6 is connected to the scan-in terminal of the logic block 1 by a signal line.
When the output of -1 becomes logic "1", the multiplexer 6 selectively outputs the data output from the shift register 5. A scan address is set in register 8. The up counter 9 counts the number of times the SIST signal becomes logic "1". The shift signal is a clock and is synchronous with the scan clock; when the scan clock is generated, the shift signal is also generated, and when the scan clock is stopped, the shift signal is also stopped. The up counter 9 is an M-ary counter. M is equal to the number of flip-flops forming the shift register in logic block 1. The comparison circuit 11 compares the value of the register 8 and the value of the up counter 9, and outputs a logic "1" on the signal line _S1 when the two match. When the signal on signal line _S1 becomes logic "1", gate circuit 12 outputs logic "1" on signal lines _S3 and _S4 . When the signal on the signal line _S4 becomes logic "1", the down counter 10 becomes ready for counting, and its value is decremented by one each time a shift signal is generated. down counter 1
When the value of 0 becomes zero, the signal on signal line _S2 becomes a logic "1". When the signal on the signal line S ₂ becomes logic "1", the gate circuit 12 makes the signals on the signal lines S ₃ and S ₄ logic "0". Note that the external processing device 2 is
Any value can be set in register 8 and down counter 10.

If you want to scan out N bits of data from a certain address, set it in the start address register 8 and set N in the down counter 10. The shift signal causes logic block 1 to be scanned out, and at the same time, up counter 9 is incremented. logic block 1
Since the flip-flops inside are connected in a ring, scan-out data becomes scan-in data and is not destroyed. When the value of up counter 9 matches the start address set in register 8, comparison circuit 11 turns on signal _S3 of gate circuit 12.
(Logic "1"). Shift signal and signal _S3 are ON
As a result, the output of AND circuit 7-2 turns ON.
Then, the scan-out data is stored in the shift register 5. At the same time, down counter 10 is decremented. When the down counter 10 is decremented and reaches zero, the signal _S3 is turned off.
(logic “0”), and the output of AND circuit 7-2 is also
It becomes OFF. This causes scan-out and
The data has finished being stored in the shift register 5.

Note that M scan clocks and shift signals are generated. If you want to scan in N bits from a certain address, set the start address in register 8 and set N to down counter 1.
Set to 0. The scan clock causes all flip-flops in the ring-connected logic block 1 to shift. When the up counter 9 is incremented and matches the first address, the output of the comparison circuit 11 is turned ON.
Signal _S3 turns ON. This signal and the shift signal turn the output of the AND circuit 7-2 ON. AND by the output of AND circuit 7-2 and the scan-in signal
When the output of the circuit 7-1 turns ON and the multiplexer 6 selects the shift register 5 side, the data prepared in advance in the shift register 5 by the external processing device 2 is read out and the previous logic block is read out. It is scanned in replacing the flip-flop value within 1. When the down counter 10 is decremented and becomes zero, the signal _S3 becomes
OFF, the multiplexer 6 selects the scan result side, and the scan result is written as it is as scan-in data. The operation is completed when the ring-shaped shift register completes one revolution.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the scan-out terminal not only prevents the values of flip-flops in the logic block from being destroyed, but also prevents the values of the flip-flops in the logic block from being destroyed by the scan-out terminal. Flips and flops other than
Destruction of the flop value can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a diagram explaining the problems of the conventional scan method. 1...Logic block, 2...External processing device, 3-1
or 3-3...logic gate, 4-0 or 4-3
…Flip-flop, 5…Shift register, 6
...Multiplexer, 7-1 and 7-2...AND circuit,
8...Register, 9...Up counter, 10...Down counter, 11...Comparison circuit, 12...Gate circuit.

Claims (1)

[Claims] 1 A logic block in which a plurality of flip-flops are connected in series to form a shift register, the last flip-flop is connected to a scan-out terminal, and the first flip-flop is connected to a scan-in terminal; , a signal line connecting the serial input of the shift register to the scan-out terminal, an output connected to the scan-in terminal, one input terminal connected to the scan-out terminal, and the other input terminal connected to the serial output of the shift register. A connected multiplexer, a register that can be set to any value, an up counter whose value increases by a unit amount each time a shift signal is generated, and a comparison between the value of the register and the value of the up counter. A comparison circuit, a down counter whose value is set to an arbitrary value and whose value decreases by a unit amount each time a shift signal is generated in a counting enabled state; control signal generating means for enabling counting and outputting a signal of a predetermined value and outputting a signal of another predetermined value when the value of the down counter reaches zero; means for supplying the shift signal as a shift clock to the shift register when the shift clock is outputting the shift register; and means for selecting the serial output of the shift register only while the shift clock is supplied to the shift register and the scan-in signal has a predetermined value. and means for supplying a signal instructing what to do to the multiplexer.